NRIIT/7.5.1/RC 08 NRI INSTITUTE OF TECHNOLOGY (Approved by AICTE, New Delhi :: Affiliated to JNTUK, Kakinada) POTHAVARAPPADU (V), (via) Nunna, Agiripalli (M), Krishna District, A.P. PIN : 521 212 Ph : 08656-324999 Website : nrigroupofcolleges.com e-mail : nrigroupofcolleges@gmail.com LIC APPLICATIONS LAB MANUAL III B.TECH I SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING R13 REGULATION, ACADEMIC YEAR: 2016-17
NRI INSTITUTE OF TECHNOLOGY (Approved by AICTE, New Delhi :: Affiliated to JNTUK, Kakinada) POTHAVARAPPADU (V), (via) Nunna, Agiripalli (M), Krishna District, A.P. PIN : 521 212 Ph : 08656-324999 Website : nrigroupofcolleges.com e-mail : nrigroupofcolleges@gmail.com LIC APPLICATIONS LAB OBSERVATION BOOK III B.TECH I SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING R13 REGULATION, ACADEMIC YEAR: 2016-17
INDEX STUDENT NAME: REG.NO: BRANCH/SEC: III/IV ACADEMIC YEAR:2016-17 S.No Date NAME OF THE EXPERIMENT PAGE MARKS SIGNATURE NO. 1. Study of op amp IC-741, IC555, IC565, IC566, 3 IC1496-functioning,parameters and specifications. 2. Op amp applications-adder, subtractor, comparator 17 circuits. 3. Integrator, differentiator circuits using op amp 741 25 4. Active Filter Applications LPF, HPF (first order) 37 5. Active Filter Applications BPF & Band Reject 45 (Wideband and Notch Filters) 6. IC741 oscillator circuits-phase shift and wien 57 bridge oscillators 7. Function Generator using OPAMPs 61 8. IC 555 Timer-Monostable Operation Circuit 67 9. IC 555 Timer - Astable Operation Circuit 75 10. Schmitt Trigger Circuits- using IC 741 & IC 555 83 11. IC565-PLL applications. 89 12. IC 566 VCO Applications 93 13. Voltage Regulator using IC723 99 14. Three Terminal Voltage Regulators- 7805, 7809, 107 7912 15. 4 bit DAC using OP AMP 117 No. of Experiments Completed: Average marks Awarded for day to day work: Signature of the Staff Member/date
LIC APPLICATIONS LAB Minimum Twelve Experiments to be conducted : 1. Study of OP AMPs IC 741, IC 555, IC 565, IC 566, IC 1496 functioning, parameters and Specifications. 2. OP AMP Applications Adder, Subtractor, Comparator Circuits. 3. Integrator and Differentiator Circuits using IC 741. 4. Active Filter Applications LPF, HPF (first order) 5. Active Filter Applications BPF, Band Reject (Wideband) and Notch Filters. 6. IC 741 Oscillator Circuits Phase Shift and Wien Bridge Oscillators. 7. Function Generator using OP AMPs. 8. IC 555 Timer Monostable Operation Circuit. 9. IC 555 Timer Astable Operation Circuit. 10. Schmitt Trigger Circuits using IC 741 and IC 555. 11. IC 565 PLL Applications. 12. IC 566 VCO Applications. 13. Voltage Regulator using IC 723. 14. Three Terminal Voltage Regulators 7805, 7809, 7912. 15. 4 bit DAC using OP AMP. Equipment required for Laboratories: 1. RPS 2. CRO 3. Function Generator 4. Multi Meters 5. IC Trainer Kits (Optional) 6. Bread Boards 7. Components:- IC741, IC555, IC565, IC1496, IC723, 7805, 7809, 7912 and other essential components. 8. Analog IC Tester
Block Diagram of Op-Amp: Pin Configuration:
EXP NO: DATE: STUDY OF OP AMPs - IC 741, IC 555, IC 565, IC 566, IC 1496-FUNCTIONING, PARAMETERS AND SPECIFICATIONS IC 741 General Description: The IC 741 is a high performance monolithic operational amplifier constructed using the planer epitaxial process. High common mode voltage range and absence of latch-up tendencies make the IC 741 ideal for use as voltage follower. The high gain and wide range of operating voltage provide superior performance in integrator, summing amplifier and general feedback applications. Features: 1. No frequency compensation required. 2. Short circuit protection 3. Offset voltage null capability 4. Large common mode and differential voltage ranges 5. Low power consumption 6. No latch-up Specifications: 1. Voltage gain A = α typically 2,00,000 2. I/P resistance R L = α Ω, practically 2MΩ 3. O/P resistance R =0, practically 75Ω 4. Bandwidth = α Hz. It can be operated at any frequency 5. Common mode rejection ratio = α (Ability of op amp to reject noise voltage) 6. Slew rate + α V/μsec (Rate of change of O/P voltage)
Block Diagram of IC 555: Pin Configuration: 7. When V 1 = V 2, V D=0 8. Input offset voltage (Rs 10KΩ) max 6 mv 9. Input offset current = max 200nA 10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF 12. Offset voltage adjustment range : ± 15mV 13. Input voltage range : ± 13V 14. Supply voltage rejection ratio : 150 μv/v 15. Output voltage swing: + 13V and 13V for R L > 2KΩ 16. Output short-circuit current: 25mA 17. supply current: 28mA 18. Power consumption: 85mW 19. Transient response: rise time= 0.3 μs Overshoot= 5% Applications: 1. AC and DC amplifiers 2. Active filters 3. Oscillators 4. Comparators 5. Regulators IC 555: Description: The operation of SE/NE 555 timer directly depends on its internal function. The three equal resistors R 1, R 2, R 3 serve as internal voltage divider for the source voltage. Thus one-third of the source voltage V CC appears across each resistor. Comparator is basically an Op amp which changes state when one of its inputs exceeds the reference voltage. The reference voltage for the lower comparator is +1/3 V CC. If a trigger pulse applied at the negative input of this comparator drops below +1/3 V CC, it causes a change in state. The upper comparator is referenced at voltage +2/3 V CC. The output of each comparator is fed to the input terminals of a flip flop.
Block Diagram of IC 565
The flip-flop used in the SE/NE 555 timer IC is a bistable multivibrator. This flip flop changes states according to the voltage value of its input. Thus if the voltage at the threshold terminal rises above +2/3 V CC, it causes upper comparator to cause flip-flop to change its states. On the other hand, if the trigger voltage falls below +1/3 V CC, it causes lower comparator to change its states. Thus the output of the flip flop is controlled by the voltages of the two comparators. A change in state occurs when the threshold voltage rises above +2/3 V CC or when the trigger voltage drops below +1/3 V cc. The output of the flip-flop is used to drive the discharge transistor and the output stage. A high or positive flip-flop output turns on both the discharge transistor and the output stage. The discharge transistor becomes conductive and behaves as a low resistance short circuit to ground. The output stage behaves similarly. When the flip-flop output assumes the low or zero states reverse action takes place i.e., the discharge transistor behaves as an open circuit or positive V CC state. Thus the operational state of the discharge transistor and the output stage depends on the voltage applied to the threshold and the trigger input terminals. Function of Various Pins of 555 IC: Pin (1) of 555 is the ground terminal; all the voltages are measured with respect to this pin. Pin (2) of 555 is the trigger terminal, If the voltage at this terminal is held greater than one-third of VCC, the output remains low. A negative going pulse from Vcc to less than Vec/3 triggers the output to go High. The amplitude of the pulse should be able to make the comparator (inside the IC) change its state. However the width of the negative going pulse must not be greater than the width of the expected output pulse. Pin (3) is the output terminal of IC 555. There are 2 possible output states. In the low output state, the output resistance appearing at pin (3) is very low (approximately 10 Ω). As a result the output current will goes to zero, if the load is connected from Pin (3) to ground, sink a current I Sink (depending upon load) if the load is connected from Pin (3) to ground, and sinks zero current if the load is connected between +VCC and Pin (3). Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the potential of Pin (4) is drives below 0.4V, the output is immediately forced to low state. The reset terminal enables the timer over-ride command signals at Pin (2) of the IC.
Pin Configuration:
Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels at which the time comparators change state. A resistor connected from Pin (5) to ground can do the job. Normally 0.01μF capacitor is connected from Pin (5) to ground. This capacitor bypasses supply noise and does not allow it affect the threshold voltages. Pin (6) is the threshold terminal. In both astable as well as monostable modes, a capacitor is connected from Pin (6) to ground. Pin (6) monitors the voltage across the capacitor when it charges from the supply and forces the already high O/p to Low when the capacitor reaches +2/3 VCC. Pin (7) is the discharge terminal. It presents an almost open circuit when the output is high and allows the capacitor charge from the supply through an external resistor and presents an almost short circuit when the output is low. Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V. Features of 555 IC 1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or between pin 3 & VCC (supply) 2. 555 can be reset by applying negative pulse, otherwise reset can be connected to +Vcc to avoid false triggering. 3. An external voltage effects threshold and trigger voltages. 4. Timing from micro seconds through hours. 5. Monostable and bistable operation 6. Adjustable duty cycle 7. Output compatible with CMOS, DTL, TTL 8. High current output sink or source 200mA 9. High temperature stability 10. Trigger and reset inputs are logic compatible.
Block Diagram of IC 565 Pin Configuration:
Specifications: 1. Operating temperature : SE 555-- -55 o C to 125 o C NE 555-- 0 o to 70 o C 2. Supply voltage : +5V to +18V 3. Timing : μsec to Hours 4. Sink current : 200mA 5. Temperature stability : 50 PPM/ o C change in temp or 0-005% / o C. Applications: 1. Monostable and Astable Multivibrators 2. dc-ac converters 3. Digital logic probes 4. Waveform generators 5. Analog frequency meters 6. Tachometers 7. Temperature measurement and control 8. Infrared transmitters 9. Regulator & Taxi gas alarms etc. IC 565: Description: The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE 560, 561, 562, 564, 565, & 567 differ mainly in operating frequency range, power supply requirements and frequency and bandwidth adjustment ranges. The device is available as 14 Pin DIP package and as 10-pin metal can package. Phase comparator or phase detector compare the frequency of input signal f s with frequency of VCO output f o and it generates a signal which is function of difference between the phase of input signal and phase of feedback signal which is basically a d.c voltage mixed with high frequency noise. LPF remove high frequency noise voltage. Output is error voltage. If control voltage of VCO is 0, then frequency is center frequency (f o) and mode is free running mode. Application of control voltage shifts the output frequency of VCO from f o to f. On application of error voltage, difference between f s & f tends to decrease and VCO is said to be locked. While in locked condition, the PLL tracks the changes of frequency of input signal
PIN DIAGRAM BLOCK DAGRAM OF IC 566
Specifications: 1. Operating frequency range : 0.001 Hz to 500 KHz 2. Operating voltage range : ±6 to ±12V 3. Inputs level required for tracking : 10mV rms minimum to 3v (p-p) max. 4. Input impedance : 10 KΩ typically 5. Output sink current : 1mA typically 6. Drift in VCO center frequency : 300 PPM/ o C typically (f out) with temperature 7. Drif in VCO centre frequency with : 1.5%/V maximum supply voltage 8. Triangle wave amplitude : typically 2.4 V PP at ± 6V 9. Square wave amplitude : typically 5.4 V PP at ± 6V 10. Output source current : 10mA typically 11. Bandwidth adjustment range : <±1 to >± 60% Center frequency f out = 1.2/4R 1C 1 Hz = free running frequency F L = ± 8 f out/v Hz V = (+V) (-V) f f c = ± L 1/ 2 3 2 (3.6) x10 xc2 Applications: 1. Frequency multiplier 2. Frequency shift keying (FSK) demodulator 3. FM detector IC 566: Description: The NE/SE 566 Function Generator is a voltage controlled oscillator of exceptional linearity with buffered square wave and triangle wave outputs. The frequency of oscillation is determined by an external resistor and capacitor and the voltage applied to the control terminal. The oscillator can be programmed over a ten to one frequency range by proper selection of an external resistance and modulated over a ten to one range by the control voltage with exceptional linearity.
Schematic of IC1496: Pin Configuration:
Specifications: Maximum operating Voltage --- 26V Input voltage --- 3V (P-P) Storage Temperature --- -65 o C to + 150 o C Operating temperature --- 0 o C to +70 o C for NE 566-55 o C to +125 o C for SE 566 Power dissipation --- 300mv Applications: 1. Tone generators. 2. Frequency shift keying 3. FM Modulators 4. clock generators 5. signal generators 6. Function generator IC 1496 Description: IC balanced mixers are widely used in receiver IC s. The IC versions are usually described as balanced modulators. Typical example of balanced IC modulator is MC1496. The circuit consists of a standard differential amplifier (formed by Q 5 _ Q 6 combination) driving a quad differential amplifier composed of transistor Q 1 Q 4. The modulating signal is applied to the standard differential amplifier (between terminals 1 and 4). The standard differential amplifier acts as a voltage to current converter. It produces a current proportional to the modulating signal. Q 7 and Q 8 are constant current sources for the differential amplifier Q 5 Q 6. The lower differential amplifier has its emitters connected to the package pins ( 2 & 3) so that an external emitter resistance may be used. Also external load resistors are employed at the device output (6 and 12 pins).the output collectors are cross-coupled so that full wave balanced multiplication takes place. As a result, the output voltage is a constant times the product of the two input signals.
Circuit Diagrams: Fig 1: Adder Fig 2: Subtractor
EXP NO: DATE: OP AMP APPLICATIONS ADDER, SUBTRACTOR, COMPARATOR CIRCUITS Aim: To design adder, subtractor and comparator for the given signals by using operational amplifier. Apparatus required: S.No Equipment/Component name Specifications/Value Quantity 1 IC 741-1 2 Resistor 1kΩ 4 3 Diode 0A79 2 4 Regulated Power supply (0 30V),1A 2 5 Function Generator (.1 1MHz), 20V p-p 1 6 Cathode Ray Oscilloscope (0 20MHz) 1 7 Multimeter 3 ½ digit display 1 Theory: Adder: A two input summing amplifier may be constructed using the inverting mode. The adder can be obtained by using either non-inverting mode or differential amplifier. Here the inverting mode is used. So the inputs are applied through resistors to the inverting terminal and non-inverting terminal is grounded. This is called virtual ground, i.e. the voltage at that terminal is zero. The gain of this summing amplifier is 1, any scale factor can be used for the inputs by selecting proper external resistors. Subtractor: A basic differential amplifier can be used as a subtractor as shown in the circuit diagram. In this circuit, input signals can be scaled to the desired values by selecting appropriate values for the resistors. When this is done, the circuit is referred to as scaling amplifier. However in this circuit all external resistors are equal in value. So the gain of amplifier is equal to one. The output voltage V o is equal to the voltage applied to the non-inverting terminal minus the voltage applied to the inverting terminal; hence the circuit is called a subtractor.
Fig 3: Comparator
Comparator: The circuit diagram shows an op-amp used as a comparator. A fixed reference voltage V ref is applied to the (-) input, and the other time varying signal voltage V in is applied to the (+) input; Because of this arrangement, the circuit is called the non-inverting comparator. Depending upon the levels of V in and V ref, the circuit produces output. In short, the comparator is a type of analog-to-digital converter. At any given time the output waveform shows whether V in is greater or less than V ref. The comparator is sometimes also called a voltage-level detector because, for a desired value of V ref, the voltage level of the input V in can be detected Procedure: A) Adder: 1. Connect the circuit as per the diagram shown in Fig 1. 2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively. 3. Apply the inputs V 1 and V 2 as shown in Fig 1. 4. Apply two different signals (DC/AC ) to the inputs 5. Vary the input voltages and note down the corresponding output at pin 6 of the IC 741 adder circuit. 6. Notice that the output is equal to the sum of the two inputs. B) Subtractor: 1. Connect the circuit as per the diagram shown in Fig 2. 2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively. 3 Apply the inputs V 1 and V 2 as shown in Fig 2. 4. Apply two different signals (DC/AC ) to the inputs 5. Vary the input voltages and note down the corresponding output at pin 6 of the IC 741 subtractor circuit. 6. Notice that the output is equal to the difference of the two inputs.
Observations: Adder: V 1(V) V 2(V) V o(v)=-(v1+v2) 2.5 2.5 3.8 4.0 Subtractor: V 1(V) V 2(V) V o(v)=(v1-v2) 2.5 3.3 4.1 5.7 Comparator: V in(v) V ref(v) V o(v) 2 0.5 5 7.2 Precautions: Check the connections before giving the power supply. Readings should be taken carefully.
Result: For adder, subtractor and comparator circuits, the practical values are compared with the theoretical values and they are nearly equal. NAME THEORETICAL PRACTICAL ADDER SUBTRACTOR COMPARATOR
Model Calculations: a) Adder V o = - (V 1 + V 2) If V 1 = and V 2 =, then V o = b) Subtractor V o = V 2 V 1 If V 1= and V 2 =, then V o = c) Comparator If V in < V ref, V o = -V sat - V EE V in > V ref, V o = +V sat = +V CC
Inference: Different applications of opamp are observed. Viva Questions: 1. What is the saturation voltage of 741 in terms of V CC? Ans: 90% of V CC 2. What is the maximum voltage that can be given at the inputs? Ans: The inputs must be given in such a way that the output should be less than V sat.
CIRCUIT DIAGRAMS Integrator
EXP NO: DATE: INTEGRATOR AND DIFFERENTIATORCIRCUITS USING IC 741 Aim: To design and verify the operation of an integrator and differentiator for a given input. Apparatus required: S.No Equipment/Component name Specifications/Value Quantity 1 741 IC - 1 2 Capacitors 0.1μf, 0.01μf Each one 3 Resistors 159Ω, 1.5kΩ Each one 4 Regulated Power supply (0 30)V,1A 1 5 Function generator (1Hz 1MHz) 1 6 Cathode Ray Oscilloscope (0 20MHz) 1 Theory Integrator: In an integrator circuit, the output voltage is integral of the input signal. The output voltage of an integrator is given by V o = -1/R 1C f t o Vidt At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like an open circuit. The gain of an integrator at low frequency can be limited by connecting a resistor in shunt with capacitor. Differentiator: In the differentiator circuit the output voltage is the differentiation of the input voltage. The output voltage of a differentiator is given by V o = -RfC 1 dv i.the input dt impedance of this circuit decreases with increase in frequency, thereby making the circuit sensitive to high frequency noise. At high frequencies circuit may become unstable.
Differentiator Design equations: Integrator: Choose T = 2πR fc f Where T= Time period of the input signal Assume C f and find R f Select R f = 10R 1 V o (p-p) = 1 R C 1 f T / 2 o V i ( p p) dt Differentiator Select given frequency f a = 1/(2πR fc 1), Assume C 1 and find R f Select f b = 10 f a = 1/2πR 1C 1 and find R 1 From R 1C 1 = R fc f, find Cf Procedures: Integrator 1. Connect the circuit as per the diagram shown in Fig 1 2. Apply a square wave/sine input of 4V(p-p) at 1KHz 3. Observe the output at pin 6.
4. Draw input and output waveforms as shown in Fig 3. Differentiator 1. Connect the circuit as per the diagram shown in Fig 2 2. Apply a square wave/sine input of 4V(p-p) at 1KHz 3. Observe the output at pin 6 4. Draw the input and output waveforms as shown in Fig 4
Wave Forms: Integrator Fig 3: Input and output waves forms of integrator
Precautions: Check the connections before giving the power supply. Readings should be taken carefully.
Differentiator Fig 4 :Input and output waveforms of Differentiator
Result: For a given square wave and sine wave, output waveforms for integrator and differentiator are observed. NAME THEORETICAL PRACTICAL INTEGRATOR DIFFERENTIATOR
Sample readings: Integrator Input Square wave Amplitude(V P-P) Time period (V) (ms) 8 1 Output - Triangular Amplitude (V P-P) Time period (V) (ms) Input sine wave Amplitude(V P-P) Time period (V) (ms) 8 1 Output - cosine Amplitude (V P-P) Time period (V) (ms) Differentiator Input square wave Amplitude (V P-P) Time period (V) (ms) 8 1 Output - Spikes Amplitude (V P-P) Time period (V) (ms) Input sine wave Amplitude (V P-P) Time period (V) (ms) 8 1 Output - cosine Amplitude (V P-P) Time period (V) (ms) Inferences: Spikes and triangular waveforms can be obtained from a given square waveform by using differentiator and integrator respectively.
Viva Questions: 1. What are the problems of ideal differentiator? Ans: At high frequencies the differentiator becomes unstable and breaks into oscillation. The differentiator is sensitive to high frequency noise. 2. What are the problems of ideal integrator? Ans: The gain of the integrator is infinite at low frequencies. 3. What are the applications of differentiator and integrator? Ans: The differentiator used in waveshaping circuits to detect high frequency components in an input signal and also as a rate-of change detector in FM demodulators. The integrator is used in analog computers and analog to digital converters and signal-wave shaping circuits. 4. What is the need for R f in the circuit of integrator? Ans: The gain of an integrator at low frequencies can be limited to avoid the saturation problem if the feedback capacitor is shunted by a resistance R f 5. What is the effect of C 1 on the output of a differentiator? Ans: It is used to eliminate the high frequency noise problem.
Model Calculations: Integrator: For T= 1 msec f a= 1/T = 1 KHz f a = 1 KHz = 1/(2πR fc f) Assuming Cf= 0.1μf, R f is found from R f=1/(2πf ac f) R f=1.59 KΩ R f = 10 R 1 R 1= 159Ω Differentiator For T = 1 msec f= 1/T = 1 KHz f a = 1 KHz = 1/(2πR fc 1) Assuming C 1= 0.1μf, R f is found from R f=1/(2πf ac 1)
Circuit diagrams: Fig: Low pass filter
EXP NO: DATE: Active Filter Applications LPF, HPF (first order) Aim: To design and obtain the frequency response of i) First order Low Pass Filter (LPF) ii) First order High Pass Filter (HPF) Apparatus required: S.No Equipment/Component name Specifications/Value Quantity 1 IC 741-1 2 Resistors Variable Resistor 10k ohm 20kΩ pot 3 1 3 Capacitors 0.01μf 1 4 Cathode Ray Oscilloscope (0 20MHz) 1 5 Regulated Power supply (0 30V),1A 1 6 Function Generator (1Hz 1MHz) 1 Theory: a) LPF: A LPF allows frequencies from 0 to higher cut of frequency, f H. At f H the gain is 0.707 A max, and after f H gain decreases at a constant rate with an increase in frequency. The gain decreases 20dB each time the frequency is increased by 10. Hence the rate at which the gain rolls off after f H is 20dB/decade or 6 db/ octave, where octave signifies a two fold increase in frequency. The frequency f=f H is called the cut off frequency because the gain of the filter at this frequency is down by 3 db from 0 Hz. Other equivalent terms for cut-off frequency are -3dB frequency, break frequency, or corner frequency. b) HPF: The frequency at which the magnitude of the gain is 0.707 times the maximum value of gain is called low cut off frequency. Obviously, all frequencies higher than f L are pass band frequencies with the highest frequency determined by the closed loop band width all of the op-amp.
Fig: High pass filter Design: First Order LPF: To design a Low Pass Filter for higher cut off frequency f H = 4 KHz and pass band gain of 2 f H = 1/( 2πRC ) Assuming C=0.01 µf, the value of R is found from R= 1/(2πf HC) Ω =3.97KΩ The pass band gain of LPF is given by A F = 1+ (R F/R 1)= 2 Assuming R 1=10 KΩ, the value of R F is found from R F=( A F-1) R 1=10KΩ First Order HPF: To design a High Pass Filter for lower cut off frequency pass band gain of 2 f L = 1/( 2πRC ) Assuming C=0.01 µf,the value of R is found from R= 1/(2πf LC) Ω =3.97KΩ The pass band gain of HPF is given by A F = 1+ (R F/R 1)= 2 Assuming R 1=10 KΩ, the value of R F is found from R F=( A F-1) R 1=10KΩ Procedure: First Order LPF 1. Connections are made as per the circuit diagram shown in Fig 1. f L = 4 KHz and
2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into saturation. 3. Vary the input frequency and note down the output amplitude at each step as shown in Table (a). 4. Plot the frequency response as shown in Fig 3. First Order HPF 1. Connections are made as per the circuit diagrams shown in Fig 2. 2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into saturation. 3. Vary the input frequency and note down the output amplitude at each step as shown in Table (b). 4. Plot the frequency response as shown in Fig 4
Tabular Form and Sampled Values: a)lpf Input voltage V in = 4V b) HPF O/P Voltage Gain Frequency O/P Voltage Gain Frequency Voltage(V) Gain indb Voltage(V) Gain indb Vo/Vi Vo/Vi 100Hz 100Hz 200Hz 200Hz 300Hz 300Hz 500Hz 500Hz 750Hz 900Hz 700Hz 800Hz 1KHz 1KHz 2KHz 2KHz 3KHz 4KHz 5KHz 6KHz 7KHz 8KHz 9KHz 10KHz 3KHz 4KHz 5KHz 6KHz 7KHz 8KHz 9KHz 10KHz Precautions: Check the connections before giving the power supply. Readings should be taken carefully.
Inferences: By interchanging R and C in a low-pass filter, a high-pass filter can be obtained. Viva Questions: 1. What is meant by frequency scaling? Ans: Change of cut off frequency from one value to the other. 2. How do you convert an original frequency (cut off) f H to a new cut off frequency f H? Ans: By varying either resistor R or capacitor C values 3. What is the effect of order of the filter on frequency response characteristics? Ans: Each increase in order will produce -20 db/decade additional increases in roll off rate. 4. What modifications in circuit diagrams require to change the order of the filter? Ans: Order of the filter is changed by RC network.
Model graphs : Fig (3) Frequency response characteristics of LPF Fig(4) Frequency response characteristics of HPF
Result: First order low-pass filter and high-pass filter are designed and frequency response characteristics are obtained. NAME THEORETICAL PRACTICAL LPF HPF
Circuit diagrams: Fig 1: Wideband pass filter
EXP NO: DATE: Active Filter Applications BPF & Band Reject (Wideband) and Notch Filters Aim: To design and obtain the frequency response of i) Wide Band pass filter ii) Wide Band reject filter iii) Notch filter Apparatus required: S.No Equipment/Component name Specifications/Value Quantity 1 741 IC - 3 2 Resistors Resistors 5.6kΩ 39kΩ 9 2 3 Resistors (20kΩ pot) 2 4 Capacitors Theory: Capacitors 0.01μf 0.1μf Capacitors 0.2μf 1 5 Regulated Power supply (0 30)V,1A 1 6 Function Generator (1Hz 1MHZ) 1 7 Cathode Ray Oscilloscope (0 20MHz) 1 Band pass filter: A band pass filter has a pass band between two cutoff frequencies f H and f L such that f H > f L. Any input frequency outside this pass band is attenuated. There are two types of band-pass filters. Wide band pass and Narrow band pass filters. We can define a filter as wide band pass if its quality factor Q <10. If Q>10, then we call the filter a narrow band pass filter. A wide band pass filter can be formed by simply cascading high-pass and low-pass sections. The order of band pass filter depends on the order of high pass and low pass sections. 2 2
Fig 2: Wideband reject filter
Band Rejection Filter: The band-reject filter is also called a band-stop or band-elimination filter. In this filter, frequencies are attenuated in the stop band while they are passed outside this band. Band reject filters are classified as wide band-reject narrow band-reject. Wide bandreject filter is formed using a low pass filter, a high-pass filter and summing amplifier. To realize a band-reject response, the low cut off frequency fl of high pass filter must be larger than high cut off frequency fh of low pass filter. The pass band gain of both the high pass and low pass sections must be equal. Notch Filter: The narrow band reject filter, often called the notch fitter is commonly used for the rejection of a single frequency. The most commonly used notch filter is the twin-t network.this is a passive filter composed of two T-shaped networks. One T network is made up of two resistors and a capacitor, while the other uses two capacitors and a resistor. There are several ways to make the notch filter. One way is to subtract the band pass filter output from its input.the notch-out frequency is the frequency at which maximum attenuation occurs and is given by fn = 1/( 2πRC )
Fig 3: Notch filter
Design: Band pass filter: To design a band pass filter having fh = 4KHz and fl = 400Hz and pass band gain of 2. As shown in Fig 1,the first section consisting of Op Amp,RF,R1,R and C is the high pass filter and second consisting of low pass filter. The design of low pass and high pass filters. Low Pass Filter Design: Assuming C =0.01μf, the value of R is found from R = 1/(2πfH C ) Ω =3.97KΩ The pass band gain of LPF is given by ALPF = 1+ (R F / R 1 )=2 Assuming R 1=5.6 KΩ, the value of R F is found from R F =( AF-1) R 1=5.6KΩ High Pass Filter Design: Assuming C=0.01μf, the value of R is found from R = 1/(2πfLC) Ω =39.7KΩ The pass band gain of HPF is given by AHPF = 1+ (RF / R1 )=2 Assuming R1=5.6 KΩ, the value of RF is found from RF = ( AF-1) R1=5.6KΩ Band reject filter: To design a band reject filter with fh = 4 KHz, fl = 400Hz and pass band gain of 2 Low Pass Filter Design: Assuming C =0.01μf, the value of R is found from R = 1/(2πfH C ) Ω =3.97KΩ The pass band gain of LPF is given by ALPF = 1+ (R F / R 1 )=2 Assuming R 1=5.6 KΩ, the value of R F is found from R F =( AF-1) R 1=5.6KΩ High Pass Filter Design: Assuming C=0.01μf, the value of R is found from R = 1/ (2πfLC) Ω =39.7KΩ The pass band gain of HPF is given by AHPF = 1+ (RF / R1) =2 Assuming R1=5.6 KΩ, the value of RF is found from RF = (AF-1) R1=5.6KΩ
Observations: a) Band pass filter: b) Band Reject Filter Input voltage (Vi) = 0.5V Frequeny O/P Gain Gain 100Hz 200Hz 300Hz 400Hz 500Hz 750Hz 900Hz 1KHz 1.5KHz 2KHz 2.5KHz 3KHz 4KHz 5KHz 6KHz 7KHz 8KHz 9KHz 10KHz Voltage Vo(V) Vo/Vi indb Frequency 50Hz 70Hz 100Hz 200Hz 300Hz 400Hz 500Hz 700Hz 900Hz 1KHz 2KHz 3KHz 4KHz 5KHz 6KHz 7KHz 8KHz 9KHz 10KHz O/P Voltage(V) Gain Vo/Vi Gain indb
Adder circuit design: Select all resistors equal value such that gain is unity. Assume R2=R3=R4=5.6 KΩ Notch Filter Design: fn = 400Hz Assuming C=0.1μf,the value of R is found from R = 1/ (2πfNC)=39 KΩ Procedure: Wide Band Pass Filter: 1. Connect the circuit as per the circuit diagram shown in Fig1 2. Apply sinusoidal wave of 0.5V amplitude as input such that opamp does not go into saturation (depending on gain). 3. Vary the input frequency from 100 Hz to 100 KHz and note down the output amplitude at each step as shown in Table (a). 4. Plot the frequency response as shown in Fig 4. Wide Band Reject Filter: 1. Connect the circuit as per the circuit diagram shown in Fig 2 2. Apply sinusoidal wave of 0.5V amplitude as input such that opamp does not go into saturation (depending on gain). 3. Vary the input frequency from 100 Hz to 100 KHz and note down the output amplitude at each step as shown in Table( b). 4. Plot the frequency response as shown in Fig 5. Notch Filter: 1. Connect the circuit as per the circuit diagram shown in Fig 3 2. Apply sinusoidal wave of 2Vp-p amplitude as input such that opamp does not go into saturation (depending on gain). 3. Vary the input frequency from 100 Hz to 4 KHz and note down the output amplitude at each step as shown in Table( c). 4. Plot the frequency response as shown in Fig 6
c) Notch filter Input voltage=2vp-p Frequency O/P Vo/Vi Gain in Voltage(V) db 100Hz 200Hz 300Hz 400Hz 500Hz 600Hz 700Hz 800Hz 900Hz 1 KHz 2 KHz 3 KHz 4 KHz
Precautions: Check the connections before giving the power supply. Readings should be taken carefully. Result: i) The frequency response of wide band pass filter is plotted as shown in Fig 4. ii) The frequency response of wide band reject filter is plotted as shown in Fig 5. iii) The frequency response of notch filter is plotted as shown in Fig 6 NAME THEORETICAL PRACTICAL BAND PASS FILTER BAND REJECT FILTER NOTCH FILTER
Model graphs: Fig 4 : Frequency response of Fig 5 : Frequency response wide bandpass filter of wide band reject filter Fig 6: Frequency response of notch filter
Inferences: Cascade connection of HPF and LPF produces wideband pass filter and parallel connection of the above filters gives wideband reject filter. The notch filter is used to reject the single frequency. Viva Questions: 1. What is the relation between f C & f H, f L? Ans: f C f H f L 2. How do you increase the gain of the wideband pass filter? Ans: By increasing the gain of either LPF or HPF 3. What is the application of Notch filter? Ans: The rejection of single frequency such as the 50-Hz power line frequency hum 4. What is the order of the filter (each type)?.what modifications you suggest for the Ans: circuit diagram to increase the order of the filter? Order of the BPF & BRF S are the order of the HPF & LPF..Order of the BPF& BRF s are increased by increasing order of HPF&LPF. 5. What is the gain roll off outside the pass band? Ans: Gain roll off outside the pass band is (20n) db/dec where n indicates the order of the filter. 6. What is the difference between active and passive filters? Ans: Active filters use Op Amp as active element, and resistors and capacitors as the passive elements. 7. What are the advantages of active filters over passive filters? Ans: Gain and frequency adjustment. No loading problem. Low cost
RC Phase shift Oscillator Wein Bridge Oscillator
EXP NO: RC PHASE SHIFT & WEIN BRIDGE OSCILLATORS DATE: AIM: To Design a RC Phase Shift & Wein Bridge Oscillators of output frequency 200 Hz. APPARATUS : NAME OF THE COMPONENT VALUE Qty 1. Resistor 3.3 K 3 2. Resistor 33K 2 3. Resistor 12K 1 4. Variable Resistor 1.2M,50K Each one 5. Capacitor 0.1μf 3 6. Capacitor 0.05 μf 2 7. 741 IC Refer Appendix A 1 8. Bread Board 1 9. Dual Channel Power Supply (0-30V) 1 10. Cathode Ray Oscilloscope (0 20MHz) 1 THEORY: RC Phase shift oscillator: The op-amp is used in inverting mode and so it provides 1800 phase shift. The additional phase 1800deg provided by RC feedback network to obtain total phase shift of 3600.The feedback network consists of three identical RC stages. Each RC stage provides 600phase shift,so that total phase shift provided by feed back network is 1800. Here the gain of the inverting op-amp should be at least 29, or Rf = 29R1.Frequency of oscillation fo = 1/ (2πRC 6) Wien Bridge Oscillator: It is a audio frequency oscillator. Feed back signal in this circuit is connected to non inverting input terminal so that op-amp is working as a non inverting amplifier. So the feed back network need not provide any phase shift. The circuit can be viewed as a Wein-Bride with a series RC network in one arm and parallel RC network in ad joint arm.r1 and Rf are connected in the remaining two arms. Here Rf = 2R1. CALCULATIONS (theoretical): RC Phase shift Oscillator: i. The frequency of oscillation fo is given by fo = 1/(2π )
ii. The gain Av at the above frequency must be at least 29 i.e Rf/R1=29 iii. fo= 200Hz Let C = 0.1μf, Then R= 3.25K (choose 3.3k) To prevent the loading of the amplifier because of RC networks it is necessary that R1 10R Therefore R1=10R=33 k Then Rf= 29 (33 k) = 957 k (choose Rf=1M) Wein Bridge Oscillator: The frequency of oscillation fo is exactly the resonant frequency of the balanced Wein Bridge and is given by fo = 1/(2πRC ) The gain required for sustained oscillations is given by Av= 3. i.e., Rf=2R1 Let C = 0.05uf Then fo = 1/ (2πRC ) => R=3.3K Now let R1=12K, then Rf =2R1=24K Use Rf =50K potentiometer MODEL WAVE FORMS: RC Phase shift Oscillator: 1. The frequency of oscillation = Wein Bridge Oscillator: 2. The frequency of oscillation = PROCEDURE: 1. Construct the circuits as shown in the circuit diagrams. 2. Adjust the potentiometer Rf that an output wave form is obtained.
3. Calculate the output wave form frequency and peak to peak voltage 4. Compare the theoretical and practical values of the output waveform frequency RESULT: 1. The frequency of oscillation of the RC phase shift oscillator = --------Hz 2. The frequency of oscillation of the Wein Bridge oscillator = --------Hz VIVA-VOICE: 1. State the two condition of oscillations 2. Classify the oscillators 3. What is the phase shift in case of the RC phase shift oscillator? 4. In phase shift oscillator what phase shift does the op-amp provide?
Circuit Diagram: Fig1: Function generator
EXP NO: DATE: Function Generator using OPAMPs Aim: To generate square wave and triangular wave form by using OPAMPs. Apparatus required: S.No Equipment/Component name Specifications/Value Quantity 1 741 IC - 2 2 Capacitors 0.01μf,0.001μf Each one 3 Resistors Resistors 86kΩ,68kΩ,680kΩ 100kΩ Each one 2 4 Regulated Power supply (0 30V),1A 1 5 Cathode Ray Oscilloscope (0-20MHz) 1 Theory: Function generator generates waveforms such as sine, triangular, square waves and so on of different frequencies and amplitudes. The circuit shown in Fig1 is a simple circuit which generates square waves and triangular waves simultaneously. Here the first section is a square wave generator and second section is an integrator. When square wave is given as input to integrator it produces triangular wave.
Design: Square wave Generator: T= 2R fc ln (2R 2 +R 1/ R 1) Assume R 1 = 1.16 R 2 Then T= 2R fc Assume C= and find R f = Assume R 1= and find R 2 = Integrator: Take R 3 C f >> T R 3 C f = 10T Assume C f= find R 3 = Take R 3C f = 10T Assume C f = 0.01μf R 3 = 10T/C = 20K
Procedure: 1. Connect the circuit as per the circuit diagram shown above. 2. Obtain square wave at A and Triangular wave at V o2 as shown in Fig 1. 3. Draw the output waveforms as shown in Fig 2(a) and (b).
Model Calculations: For T= 2 m sec T = 2 R f C Assuming C= 0.1μf R f = Sample readings: Square Wave: V p-p = 26 V(p-p) T = 1.8 msec Triangular Wave: V p-p = 1.3 V T= 1.8 msec 2.10-3 / 2.01.10-6 = 10 KΩ Assuming R 1 = 100 K R 2 = 86 KΩ Wave Forms: Output at A Fig 2 (a): (b): Output at V 02
Precautions: Check the connections before giving the power supply. Readings should be taken carefully.. Result: Square wave and triangular wave are generated and the output waveforms are observed. NAME THEORETICAL PRACTICAL SQUAREWAVE TRIANGULARWAVE Inferences: Various waveforms can be generated. Viva Questions: 1. How do you change the frequency of square wave? Ans: By changing resistor and capacitor values 2. What are the applications of function generator? Ans: Function generators are used for Transducer linearization and sine shaping.
Circuit Diagram: Fig1:Monostable Circuit using IC555
EXP NO: DATE: IC 555 Timer-Monostable Operation Circuit Aim: To generate a pulse using Monostable Multivibrator by using IC555 Apparatus required: S.No Equipment/Component Specifications/Value Quantity name 1 555 IC - 1 2 Capacitors 0.1μf,0.01μf Each one 3 Resistor 10kΩ 1 4 Regulated Power supply (0 30V),1A 1 5 Function Generator (1HZ 1MHz) 1 6 Cathode ray oscilloscope (0 20MHz) 1 Theory: A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand by mode the output of the circuit is approximately Zero or at logic-low level. When an external trigger pulse is obtained, the output is forced to go high ( V CC). The time for which the output remains high is determined by the external RC network connected to the timer. At the end of the timing interval, the output automatically reverts back to its logic-low stable state. The output stays low until the trigger pulse is again applied. Then the cycle repeats. The Monostable circuit has only one stable state (output low), hence the name monostable. Normally the output of the Monostable Multivibrator is low.
Design: Consider V CC = 5V, for given t p Output pulse width t p = 1.1 R A C Assume C = in the order of microfarads & Find R A? Typical values: If C=0.1 µf, R A = 10k then t p = 1.1 msec Trigger Voltage =4 V
Procedure: 1. Connect the circuit as shown in the circuit diagram. 2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz. 3. Observe the output waveform and measure the pulse duration. 4. Theoretically calculate the pulse duration as T high=1.1. R AC 5. Compare it with experimental values.
Waveforms: Fig 2 (a): Trigger signal (b): Output Voltage (c): Capacitor Voltage Sample Readings: Input Trigger Output wave Capacitor output
Precautions: Check the connections before giving the power supply. Readings should be taken carefully. Result: The input and output waveforms of 555 timer monostable Multivibrator are observed as shown in Fig 2(a), (b), (c). NAME THEORETICAL PRACTICAL MONOSTABLE MULTIVIBRATOR USING IC555 PULSEWIDTH
Inferences: Output pulse width depends only on external components R A and C connected to IC555. Viva Questions: 1. Is the triggering given is edge type or level type? If it is edge type, trailing or raising edge? Ans: Edge type and it is trailing edge 2. What is the effect of amplitude and frequency of trigger on the output? Ans: Output varies proportionally. 3. How to achieve variation of output pulse width over fine and course ranges? Ans: One can achieve variation of output pulse width over fine and course ranges by varying capacitor and resistor values respectively 4. What is the effect of Vcc on output? Ans: The amplitude of the output signal is directly proportional to Vcc 5. What are the ideal charging and discharging time constants (in terms of R and C) of capacitor voltage? Ans: Charging time constant T=1.1RC Sec Discharging time constant=0 Sec 6. What is the other name of monostable Multivibrator? Why? Ans: i) Gating circuit.it generates rectangular waveform at a definite time and thus could be used in gate parts of the system. ii) One shot circuit. The circuit will remain in the stable state until a trigger pulse is received. The circuit then changes states for a specified period, but then it returns to the original state. 7. What are the applications of monostable Multivibrator? Ans: Missing Pulse Detector, Frequency Divider, PWM, Linear Ramp Generator
Circuit Diagram: Fig.1 555 Astable Circuit
EXP NO: DATE: IC 555 Timer - Astable Operation Circuit Aim: To generate unsymmetrical square and symmetrical square waveforms using IC555. Apparatus required: S.No Equipment/Component name Specifications/Value Quantity 1 IC 555 1 2 Resistors 3.6kΩ,7.2kΩ Each one 3 Capacitors 0.1μf,0.01μf Each one 4 Diode OA79 1 5 Regulated Power supply (0 30V),1A 1 6 Cathode Ray Oscilloscope (0 20MHz) 1 Theory: When the power supply V CC is connected, the external timing capacitor C charges towards V CC with a time constant (R A+R B) C. During this time, pin 3 is high ( V CC) as Reset R=0, Set S=1 and this combination makes Q =0 which has unclamped the timing capacitor C. When the capacitor voltage equals 2/3 V CC, the upper comparator triggers the control flip flop on that Q =1. It makes Q1 ON and capacitor C starts discharging towards ground through R B and transistor Q1 with a time constant R BC. Current also flows into Q1 through R A. Resistors R A and R B must be large enough to limit this current and prevent damage to the discharge transistor Q1. The minimum value of R A is approximately equal to V CC/0.2 where 0.2A is the maximum current through the ON transistor Q1. During the discharge of the timing capacitor C, as it reaches V CC/3, the lower comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0 unclamps the external timing capacitor C. The capacitor C is thus periodically charged and discharged between 2/3 V CC and 1/3 V CC respectively. The length of time that the output remains HIGH is the time for the capacitor to charge from 1/3 V CC to 2/3 V CC. The capacitor voltage for a low pass RC circuit subjected to a step input of V CC volts is given by V C = V CC [1- exp (-t/rc)] Total time period T = 0.69 (R A + 2 R B) C ; f= 1/T = 1.44/ (R A + 2R B) C
Model calculations: Given f=1 KHz. Assuming c=0.1μf and D=0.25 1 KHz = 1.44/ (RA+2R B) x 0.1x10-6 and 0.25 =( R A+R B)/ (R A+2R B) Solving both the above equations, we obtain R A & R B as R A = 7.2K Ω R B = 3.6K Ω Design: Formulae: f= 1/T = 1.44/ (R A+2R B) C Duty cycle (D) = t c/t = R A + R B/(R A+2R B)
Procedure: I) Unsymmetrical Square wave 1. Connect the circuit as per the circuit diagram shown without connecting the diode OA 79. 2. Observe and note down the waveform at pin 6 and across timing capacitor. 3. Measure the frequency of oscillations and duty cycle and then compare with the given values. 4. Sketch both the waveforms to the same time scale. II) Symmetrical square waveform generator: 1. Connect the diode OA79 as shown in Figure to get D=0.5 or 50%. 2. Choose R a=r b = 10KΩ and C=0.1μF 3. Observe the output waveform, measure frequency of oscillations and the duty cycle and then sketch the o/p waveform.
Waveforms: Fig 2(a): Unsymmetrical square wave output (b): Capacitor voltage of Unsymmetrical square wave output (c): Symmetrical square wave output Sample Readings: Parameter Unsymmetrical Symmetrical Voltage V PP Time period T Duty cycle
Precautions: Check the connections before giving the power supply. Readings should be taken carefully. Result: Both unsymmetrical and symmetrical square waveforms are obtained and time period at the output is calculated. NAME THEORETICAL PRACTICAL ASTABLE MULTIVIBRATOR USING IC555 DUTY CYCLE
Inferences: Unsymmetrical square wave of required duty cycle and symmetrical square waveform can be generated. Viva Questions: 1. What is the effect of C on the output? Ans: Time period of the output depends on C 2. How do you vary the duty cycle? Ans: By varying R A or R B. 3. What are the applications of 555 in astable mode? Ans: FSK Generator, Pulse Position Modulator, Square wave generator 4. What is the function of diode in the circuit? Ans: To get symmetrical square wave. 5. On what parameters T c and T d designed? Ans: R A, R B and C 6. What are charging and discharging times Ans: The time during which the capacitor charges from (1/3) Vcc to (2/3) Vcc is equal to the time the output is high is known as charging time and is given by T c=0.69(r A+R B)C The time during which the capacitor discharges from (2/3) Vcc to (1/3) Vcc is equal to the time the output is low is known as discharging time and is given by T d=0.69(r B) C.
Circuit Diagrams: Fig 1: Schmitt trigger circuit using IC 741
EXP NO: DATE: Schmitt Trigger Circuits- using IC 741 & IC 555 Aim: To design the Schmitt trigger circuit using IC 741 and IC 555 Apparatus required: S.No Equipment/Component name Specifications/Value Quantity 1 IC 741-1 2 555IC - 1 3 Cathode Ray Oscilloscope (0 20MHz) 1 4 Multimeter 1 5 Resistors 100 Ω 56 KΩ 2 1 6 Capacitors 0.1 μf, 0.01 μf Each one 7 Regulated power supply (0-30V),1A 1 Theory: The circuit shows an inverting comparator with positive feed back. This circuit converts orbitrary wave forms to a square wave or pulse. The circuit is known as the Schmitt trigger (or) squaring circuit. The input voltage V in changes the state of the output V o every time it exceeds certain voltage levels called the upper threshold voltage V ut and lower threshold voltage V lt. When V o= - V sat, the voltage across R 1 is referred to as lower threshold voltage, V lt. When V o=+v sat, the voltage across R 1 is referred to as upper threshold voltage V ut. The comparator with positive feed back is said to exhibit hysterisis, a dead band condition.
Fig 2: Schmitt trigger circuit using IC 555
Design: V utp = [R 1/(R 1+R 2 )](+V sat) V ltp = [R 1/(R 1+R 2 )](-V sat) V hy = V utp V ltp =[R 1/(R 1+R 2)] [+V sat (-V sat)] Procedure: 1. Connect the circuit as shown in Fig 1 and Fig2. 2. Apply an orbitrary waveform (sine/triangular) of peak voltage greater than UTP to the input of a Schmitt trigger. 3. Observe the output at pin6 of the IC 741 and at pin3 of IC 555 Schmitt trigger circuit by varying the input and note down the readings as shown in Table 1 and Table 2 4. Find the upper and lower threshold voltages (V utp, V Ltp) from the output wave form.
Wave forms: Sample readings: Table 1: Fig 3: (a) Schmitt trigger input wave form (b) Schmitt trigger output wave form Parameter Input Output 741 555 Voltage( V p-p) 3.6 4 Time period(ms) 0.72 1 Table 2: Parameter V utp V ltp Precautions: Check the connections before giving the power supply. Readings should be taken carefully.
Results: UTP and LTP of the Schmitt trigger are obtained by using IC 741 and IC 555 as shown in Table 2. NAME THEORETICAL PRACTICAL SCHMITT TRIGGER USING IC741-UTP,LTP SCHMITTTRIGGER USING IC 555- UTP,LTP Viva Questions: 1. What is the other name for Schmitt trigger circuit? Ans: Regenerative comparator 2. In Schmitt trigger which type of feed back is used? Ans: Positive feedback. 3. What is meant by hysteresis? Ans: The comparator with positive feedback is said to be exhibit hysteresis, a deadband condition. When the input of the comparator is exceeds V utp, its output switches from + V sat to - V sat and reverts back to its original state,+ V sat,when the input goes below V ltp 4. What are effects of input signal amplitude and frequency on output? Ans: The input voltage triggers the output every time it exceeds certain voltage levels (UTP and LTP). Output signal frequency is same as input signal frequency. Inferences: Schmitt trigger produces square waveform from a given signal.