Peak 3A Bus Termination Regulator General Description The regulator is designed to convert voltage supplies ranging from 1.6 to 6 into a desired output voltage which adjusted by two external voltage divider resistors. The regulator is capable of sourcing or sinking up to 3A of peak current while regulating an output voltage to within % (DDR 1) and 3% (DDR ) or less. The, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for DDR SDRAM. Current limits in both sourcing and sinking mode, plus onchip thermal shutdown make the circuit tolerant of the output fault conditions. Ordering Information Features Support Both DDR 1 (1.5 TT ) and DDR (.9 TT ) Requirements SOP-8, TO-5-5 and TO-63-5 Packages Capable of Sourcing and Sinking 3A Peak Current Current-limiting Protection Thermal Protection Integrated Power MOSFETs Generates Termination oltages for SSTL- High Accuracy Output oltage at Full-Load Adjustable OUT by External Resistors Minimum External Components Shutdown for Standby or Suspend Mode Operation with High-impedance Output RoHS Compliant and 1% Lead (Pb)-Free Applications DDR Memory Termination Active Termination Buses Supply Splitter Package Type M5 : TO-63-5 L5 : TO-5-5 S : SOP-8 Operating Temperature Range C : Commercial Standard P : Pb Free with Commercial Standard 3A Sink & Source 1.5A Sink & Source Pin Configurations (TOP IEW) 5 3 1 OUT CNTL (TAB) IN Note : TO-63-5 (RT9173A) RichTek Pb-free products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-. Suitable for use in SnPb or Pb-free soldering processes. 1%matte tin (Sn) plating. 5 3 1 OUT CNTL (TAB) IN TO-5-5 (RT9173A) IN OUT 8 7 3 6 5 CNTL CNTL CNTL CNTL SOP-8 (RT9173) 1
Typical Application Circuit CNTL = 3.3 IN =.5 R TT R 1 IN CNTL C IN C CNTL N7 OUT EN R C SS C OUT R DUMMY R 1 = R = 1kΩ, R TT = 5Ω / 33Ω / 5Ω C OUT(MIN) = 1µF (Ceramic) + 1µF under the worst case testing condition R DUMMY = 1kΩ as for OUT discharge when IN is not present but CNTL is present C SS = 1µF, C IN = 7µF (Low ESR), C CNTL = 7µF Test Circuit.5 3.3 1.5 IN CNTL OUT OUT C OUT I L Figure 1. Output oltage Tolerance, LOAD.5 A 3.3 1.5. IN CNTL OUT R L 1.5 OUT C OUT R L and C OUT Time deleay Figure. Current in Shutdown Mode, I SHDN
.5 3.3 1.5 IN CNTL OUT OUT A C OUT I L Figure 3. Current Limit for High Side, I LIMIT Power Supply with Current Limit 1.5.5 3.3 IN CNTL OUT A I L OUT C OUT Figure. Current Limit for Low Side, I LIMIT.5 3.3 IN CNTL 1.5 OUT OUT. R L C OUT 1.5 OUT OUT would be low if <. OUT would be high if >.8 R L and C OUT Time deleay Figure 5. Pin Shutdown Threshold, TRIGGER 3
Functional Pin Description Pin Name IN CNTL OUT Pin Function Power Input oltage Ground Gate Drive oltage Reference oltage Input and Chip Enable Output oltage Function Block Diagram CNTL IN Current Limiting Sensor CNTL OUT Thermal
Absolute Maximum Ratings Input oltage ------------------------------------------------------------------------------------------------------------ 7 Power Dissipation ----------------------------------------------------------------------------------------------------- Internally Limited ESD Rating ------------------------------------------------------------------------------------------------------------- k Storage Temperature Range ---------------------------------------------------------------------------------------- 65 C to 15 C Lead Temperature (Soldering, 1 sec.) --------------------------------------------------------------------------- 6 C Power Dissipation, P D @ T A = 5 C TO-63-5 ----------------------------------------------------------------------------------------------------------------- 1.93W TO-5-5 ----------------------------------------------------------------------------------------------------------------- 1.71W SOP-8 --------------------------------------------------------------------------------------------------------------------.65W Package Thermal Resistance (Note 3) TO-63-5, θ JC ---------------------------------------------------------------------------------------------------------- 7.7 C/W TO-5-5, θ JC ---------------------------------------------------------------------------------------------------------- 8 C/W SOP-8, θ JC -------------------------------------------------------------------------------------------------------------- 3. C /W TO-63-5,θ JA ------------------------------------------------------------------------------------------------------------ 5 C/W TO-5-5, θ JA ----------------------------------------------------------------------------------------------------------- 68 C/W SOP-8, θ JA -------------------------------------------------------------------------------------------------------------- 16 C/W Electrical Characteristics (IN =.5,, = 1.5, COUT = 1µF (Ceramic), TA = 5 C, unless otherwise specified.) Parameter Symbol Test Conditions Min Typ Max Units Output Offset oltage OS I OUT = A, Figure 1 (Note 1) - m Load Regulation (DDR 1/) LOAD I L : A 1.5A, Figure 1 --.8/1. /3 I L : A -1.5A --.8/1. /3 % Input oltage Range (DDR 1/) (Note ) IN Keep CNTL IN on operation power 1.6.5/1.8 -- CNTL on and power off sequences -- 3.3 6 Operating Current of CNTL I CNTL No Load -- 6.5 1 ma Current In Shutdown Mode I SHDN <., R L = 18Ω, Figure -- 5 9 µa Short Circuit Protection Current limit I LIMIT Figure 3, 3. -- -- A Over Temperature Protection Thermal Shutdown Temperature T SD 3.3 CNTL 5 15 15 -- C Thermal Shutdown Hysteresis Guaranteed by design -- 5 -- C Shutdown Function Shutdown Threshold Trigger TRIGGER Output = High, Figure 5.8 -- -- TRIGGER Output = Low, Figure 5 -- --. Note 1. OS offset is the voltage measurement defined as OUT subtracted from. Note. For safely operate your system, the 3.3 rail MUST be tied to CNTL rather than 5 rail, especially for the new part of RT9173ACL5. Note 3. θ JA is measured in the natural convection at T A = 5 C on a low effective thermal conductivity test board (single Layers, 1S) of JEDEC 51-3 thermal measurement standard. The case point of θ JC is on the on the center of CTRL pins (Lead 6 & 7) for SOP-8 packages, the center of heat sink (tab) for TO-5-5 and TO-63-5 packages. 5
Typical Operating Characteristics 8. 7. Sourcing Current (Peak) vs. Temperature 8. 7. Sinking Current (Peak) vs. Temperature Sourcing Current (A) 6. 5.. 3.. 1. IN =.5 OUT =. - - 6 8 1 1 Temperature ( C) Sinking Current (A) A 6. 5.. 3.. 1. IN =.5 OUT =. - - 6 8 1 1 Temperature ( C) 7 Turn-On Threshold vs. Temperature 7 Turn-On Threshold vs. Temperature Threshold oltage (m) 65 6 55 5 5 IN =.5 - - 6 8 1 1 Temperature ( C) Threshold oltage (m) 65 6 55 5 5 CNTL = 5. IN =.5 - - 6 8 1 1 Temperature ( C) Output Transient oltage (m) Output Current (A) 1 5-5 1-1 - 1.5 TT @ 1.5A Transient Response IN =.5 = Swing Frequency = 1KHz Output Transient oltage (m) Output Current (A) 1 5-5 - - 1.5 TT @ 3A Transient Response IN =.5 = Swing Frequency = 1KHz Time (5us/Div) Time (5us/Div) 6
Output Transient oltage (m) Output Current (A) 1 5-5 1-1 -.9 TT @ 1.5A Transient Response IN = 1.8 =.9 Swing Frequency = 1KHz Output Transient oltage (m) Output Current (A) 1 5-5 - -.9 TT @ 3A Transient Response IN = 1.8 =.9 Swing Frequency = 1KHz Time (5us/Div) Time (5us/Div).31.3 Temperature vs. R DS(ON) IN =.9.3.31 Temperature vs. R DS(ON) IN =.9.9 IN =.85.3 (Ω).8 (Ω).9 IN =.85 RDS(ON).7.6 IN =.8 RDS(ON).8.7 IN =.8.5.6..3 =. 5 35 5 55 65 75 85 95 15 115 15 Temperature ( C).5. CNTL = 5. =.3 5 35 5 55 65 75 85 95 15 115 15 Temperature ( C) Output Short Circuit (A) 1 1 8 6 Sink Output Short-Circuit Protection IN =.5 = Output Short Circuit (A) 1 1 8 6 Output Short-Circuit Protection Source IN =.5 = - - Force the output shorted to - - Force the output shorted to ground Time (5ms/Div) Time (5ms/Div) 7
Application Information Internal Parasitic Diode Avoid forward-bias internal parasitic diode, OUT to CNTL, and OUT to IN, the OUT should not be forced some voltage respect to ground on this pin while the CNTL or IN is disappeared. Consideration while Designs the Resistance of oltage Divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on is below.. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? In notebook application, using RichTek's Patent "Distributed Bus Terminator Topology" with choosing RichTek's product is encouraged. Distributed Bus Terminating Topology Terminator Resistor Thermal Consideration regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed absolute maximum operation junction temperature 15 C. The power dissipation definition in device is: P D = ( IN - OUT ) x I OUT + IN x I Q The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( T J(MAX) -T A ) /θ JA Where T J(MAX) is the maximum operation junction temperature 15 C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance θ JA highly depends on IC package, PCB layout, and the rate of surroundings airflow. θ JA for SOP-8 package is 16 C/W and TO-63-5 package is 5 C/W on standard JEDEC 51-3 (single layer, 1S) thermal test board. The maximum power dissipation at T A = 5 C can be calculated by following formula: R BUS() P D(MAX) = (15 C - 5 C) / (16 C/W)=.65W (SOP-8 R1 BUS(1) package) OUT R BUS() P D(MAX) = (15 C- 5 C) / (5 C/W)= 1.93W (TO- 63- R3 BUS(3) 5 package ) R R5 BUS() BUS(5) Since the multiple CTRL pins of the SOP-8 package are internally fused and connected to lead frame, it is efficient OUT R6 R7 R8 R9 BUS(6) BUS(7) BUS(8) BUS(9) to dissipate the heat by adding cooper area on CTRL footprint. Figure 7 shows the package sectional drawing of SOP-8. Every package has several thermal dissipation paths, as show in Figure 8, the thermal resistance equivalent circuit of SOP-8. The path is the main path of thermal flow due to these materials thermal conductivity. RN RN+1 BUS(N) BUS(N+1) We define the center of multiple CTRL pins are the case point of the path. Figure 6 8
Molding Compound Lead Frame 1 9 θ JA vs. Copper Area Die Case Point 8 Die Pad θja ( C/W) 7 6 Ambient Molding Compound Gold Wire Die Pad Lead Frame 5 3 SOP-8 SP thermal test board 1 3 5 6 7 8 9 1 Copper Area (mm ) Figure 7. The Package Section Drawing of SOP-8 Package The thermal resistance θ JA of IC package is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased efficiently by adding copper under the main path of thermal flow on the package. The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θ JA. For package, the Figure 9 and the Figure 1 show the thermal resistance θ JA vs. copper area of SOP-8 and TO-63-5 packages on single layer (1S) and -layer (SP) thermal test board at T A = 5 C, PCB copper thickness = oz. Thermal Resistance ( C/W) Figure 9. Thermal Resistance θ JA vs. Copper Area of SOP-8 Packages Thermal Resistance vs. Cooper Area 7 6 1S thermal test board 5 SP thermal test board 3 1 TO-63-5 5 1 15 5 3 35 Cooper Area (mm ) Figure 1. Thermal Resistance θ JA vs. Copper Area of TO-63-5 Packages R GOLD-LINE R LEAD FRAME R PCB path 1 Internally Fused For example, as shown in Figure 9, SOP-8 with 1mm x 1mm cooper area on -layers (SP) thermal Junction R DIE R DIE-ATTACH R DIE-PAD path R LEAD FRAME R PCB Ambient test board at T A = 5 C, we can obtain the lower thermal resistance about 5 C/W. The power maximum dissipation can be calculated as: R MOLDING-COMPOUND path 3 Figure 8. Thermal Resistance Equivalent Circuit of SOP-8 Package P D(MAX) = (15 C - 5 C) / (5 C/W) =.W (SOP-8) As shown in Figure 1, TO-63-5 with 15mm x 15mm cooper area on -layers (SP) thermal test board at T A = 5 C, we can obtain the lower thermal resistance about 9 C/W. The power maximum dissipation 9
can be calculated as: P D(MAX) = (15 C - 5 C) / (9 C/W) = 3.5W (TO-63-5) Figure 11 and Figure 1 of power dissipation vs. copper area allow the designer to see the effect of rising ambient temperature on the maximum power allowed. 1 9 Power Dissipation vs. Copper Area SP thermal test board 8 Copper Area (mm ) 7 6 5 3 TA = 65 C TA = 55 C TA = 5 C 1 SOP-8.5 1 1.5.5 3 Power Dissipation (W) Figure 11. Power Dissipation vs. Copper Area of SOP-8 Package Cooper Area (mm ) 35 3 5 15 1 Cooper Area vs. Power Dissipation SP thermal test board TA = 65 C TA = 55 C TA = 5 C 5.5 1 1.5.5 3 3.5.5 Power Dissipation (W) TO-63-5 Figure 1. Power Dissipation vs. Copper Area of TO-63-5 Package 1
Outline Dimension B D C U E L1 L e b b A Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max D 9.65 1.668.38. B 1.13 1.676.5.66 E 8.18 9.65.3.38 A.6.86.16.19 C 1.13 1.397.5.55 U 6.3 Ref..5 Ref. 7.6 Ref..3 Ref. L1 1.65 15.875.575.65 L.86.79.9.11 b.66.91.6.36 b.35.58.1.3 e 1.5 1.89.6.7 5-Lead TO-63 Plastic Surface Mount Package 11
E b3 C R L3 D H T S L b P L A Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A.18.388.86.9 b.381.889.15.35 b3.953 5.61.195.15 C.57.889.18.35 D 5.33 6.3.1.5 E 6.35 6.731.5.65 H 9. 1.1.35.1 L.58 1.78..7 L.58 Ref.. Ref. L3.889.3.35.8 P 1.7 Ref..5 Ref. 5. Ref..5 Ref. R. 1.5.8.59 S.5 3..98.13 T.5.85..33 5-Lead TO-5 Surface Mount Package 1
A H M J B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A.81 5..189.197 B 3.81 3.988.15.157 C 1.36 1.753.53.69 D.33.58.13. M.6 1.7.16.5 F 1.19 1.36.7.53 I.1.5..1 J 5.791 6.198.8. H.178.5.7.1 8-Lead SOP Plastic Package RICHTEK TECHNOLOGY CORP. Headquarter 5F, No., Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)556789 Fax: (8863)556611 RICHTEK TECHNOLOGY CORP. Taipei Office (Marketing) 8F-1, No. 137, Lane 35, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (886)8919166 Fax: (886)8919165 Email: marketing@richtek.com 13