A Bus Termination Regulator General Description The regulator is designed to convert voltage supplies ranging from 1.7 to 6 into a desired output voltage of which adjusted by two external voltage divider resistors. The regulator is capable of sourcing or sinking up to A of current while regulating an output voltage to within 4m. The, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for DDR SDRAM. Current limits in both sourcing and sinking mode, plus onchip thermal shutdown make the circuit tolerant of the output fault conditions. The are available in the popular 5-lead TO-5 and fused SOP-8 (the multiple CNTL pins on the SOP-8 package are internally connected but lowest thermal resistance) surface mount packages. Ordering Information Features Support Both DDR I (1.5 TT ) and DDR II (.9 TT ) Requirements SOP-8 and TO-5-5 Packages Capable of Sourcing and Sinking Current Current-limiting Protection Thermal Protection Integrated Power MOSFETs Generates Termination oltages for SSTL- High Accuracy Output oltage at Full-Load Adjustable by External Resistors Minimum External Components Shutdown for Standby or Suspend Mode Operation with High-impedance Output RoHS Compliant and 1% Lead (Pb)-Free Applications DDR Memory Termination Supply Active Termination Buses Desktop PC/AGP Graphics Set Top Box/IPC Supply Splitter Pin Configurations Package Type S : SOP-8 L5 : TO-5-5 IN (TOP IEW) 8 CNTL Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) REFEN OUT 7 3 6 4 5 CNTL CNTL CNTL Note : SOP-8 RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-. Suitable for use in SnPb or Pb-free soldering processes. 1%matte tin (Sn) plating. 5 OUT 4 REFEN 3 CNTL (TAB) 1 IN TO-5-5 1
Typical Application Circuit CNTL = 3.3 IN =.5 C CNTL R TT N7 R 1 CNTL IN REFEN OUT C IN EN R C OUT RDUMMY Test Circuit R 1 = R = 1kΩ, R TT = 5Ω / 33Ω / 5Ω C OUT(MIN) = 1μF (Ceramic) + 1μF under the worst case testing condition R DUMMY = 1kΩ as for OUT discharge when IN is not present but CNTL is present C IN = 47μF (Low ESR), CCNTL = 47μF 3.3.5 1.5 CNTL IN REFEN OUT C OUT I L Figure 1. Output oltage Tolerance, Δ 3.3 A.5 1.5. CNTL IN REFEN OUT R L 1.5 C OUT R L and C OUT Time deleay Figure. Current in Shutdown Mode, Ι SHDN
3.3.5 1.5 CNTL IN REFEN OUT A C OUT I L Figure 3. Current Limit for High Side, Ι CLHIGH 3.3 Power Supply with Current Limit.5 1.5 CNTL IN REFEN OUT A I L C OUT Figure 4. Current Limit for Low Side, Ι CLLOW 3.3.5 1.5 CNTL IN REFEN OUT REFEN. R L C OUT 1.5 would be low if REFEN <. would be high if REFEN >.6 R L and C OUT Time deleay Figure 5. REFEN Pin Shutdown Threshold, TRIGGER 3
Functional Pin Description Pin Name Pin Function IN CNTL REFEN OUT Power Input Ground Gate Drive oltage Reference oltage Input and Chip Enable Output oltage Function Block Diagram CNTL IN Current Limiting Sensor REFEN CNTL OUT Thermal 4
Absolute Maximum Ratings (Note 1) Input oltage ------------------------------------------------------------------------------------------------------------ 7 Power Dissipation, P D @ T A = 5 C SOP-8 --------------------------------------------------------------------------------------------------------------------.65W TO-5 ------------------------------------------------------------------------------------------------------------------- 1.471W Package Thermal Resistance (Note 5) SOP-8, θ JA -------------------------------------------------------------------------------------------------------------- 16 C/W SOP-8, θ JC -------------------------------------------------------------------------------------------------------------- 3 C/W TO-5, θ JA ------------------------------------------------------------------------------------------------------------- 68 C/W TO-5, θ JC ------------------------------------------------------------------------------------------------------------- 8 C/W Lead Temperature (Soldering, 1 sec.) --------------------------------------------------------------------------- 6 C Junction Temperature ------------------------------------------------------------------------------------------------ 15 C Storage Temperature Range ---------------------------------------------------------------------------------------- 65 C to 15 C ESD Susceptibility (Note ) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ k MM (Machine Mode) -------------------------------------------------------------------------------------------------- Recommended Operating Conditions (Note 3) Junction Temperature Range ---------------------------------------------------------------------------------------- 4 C to 15 C Electrical Characteristics (IN =.5,, REFEN = 1.5, COUT = 1μF (Ceramic), TA = 5 C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units Output Offset oltage OS I OUT = A, Figure 1 (Note 4) m Load Regulation Δ LOAD I L : A A, Figure 1 I L : A -A m Input oltage Range (DDR I/II) IN Keep CNTL IN on operation power 1.7.5/1.8 -- CNTL on and power off sequences 3 3.3/5 6 Operating Current of CNTL I CNTL No Load -- 1.5 ma Current In Shutdown Mode I SHDN REFEN <., R L = 18Ω, Figure -- 5 9 μa Short Circuit Protection Current limit I LIM Figure 3,4..6 -- A Over Temperature Protection Thermal Shutdown Temperature T SD 3.3 CNTL 5 15 17 -- C Thermal Shutdown Hysteresis ΔT SD 3.3 CNTL 5 -- 35 -- C Shutdown Function Shutdown Threshold Trigger Output = High, Figure 5.6 -- -- Output = Low, Figure 5 -- --. 5
Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 1pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. OS offset is the voltage measurement defined as subtracted from REFEN. Note 5. θ JA is measured in the natural convection at T A = 5 C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θ JC is on the center of CTRL pins (Lead 6 & 7) for SOP-8 packages. 6
Typical Operating Characteristics Source Current Limit vs. Temperature Source Current Limit vs. Temperature 3.8 3.8 3.4 IN = 1.8, CNTL = 5 3.4 Source current (A) 3.6 IN =.5, CNTL = 5 Source current (A) 3.6 IN = 1.8, IN =.5,.. 1.8-4 -5-1 5 35 5 65 8 95 11 15 1.8-4 -5-1 5 35 5 65 8 95 11 15 Sink Current Limit vs. Temperature Sink Current Limit vs. Temperature 3.8 3.8 IN = 1.8, CNTL = 5 3.4 3.4 Sink current (A) 3.6 IN =.5, CNTL = 5 Sink current (A) 3.6 IN = 1.8, IN =.5,.. 1.8-4 -5-1 5 35 5 65 8 95 11 15 1.8-4 -5-1 5 35 5 65 8 95 11 15.5 Turn-On Threshold vs. Temperature.5 Turn-Off Threshold vs. Temperature Threshold oltage ().45.4.35 IN =.5, CNTL = 5 IN =.5, Threshold oltage ().45.4.35 IN =.5, CNTL = 5 IN =.5,.3-4 -5-1 5 35 5 65 8 95 11 15.3-4 -5-1 5 35 5 65 8 95 11 15 7
Output oltage vs. Temperature Output oltage vs. Temperature.91 IN = 1.8 1.6 IN =.5 Output oltage ().95.9.895 Output oltage () 1.55 1.5 1.45.89 1.4-4 -5-1 5 35 5 65 8 95 11 15-4 -5-1 5 35 5 65 8 95 11 15 Temperature ( C).9 TT @ A Transient Response.9 TT @ A Transient Response Output Transient oltage (m) 1-1 REFEN =.9 Swing Frequency : 1kHz IN = 1.8 Output Transient oltage (m) 1-1 REFEN =.9 Swing Frequency : 1kHz IN = 1.8 CNTL = 5 Output Current (A) - Output Current (A) - Time (5us/Div) Time (5us/Div) 1.5 TT @ A Transient Response 1.5 TT @ A Transient Response Output Transient oltage (m) 1-1 REFEN = 1.5 Swing Frequency : 1kHz IN =.5 Output Transient oltage (m) 1-1 REFEN= 1.5 Swing Frequency : 1kHz IN =.5 CNTL = 5 Output Current (A) - Output Current (A) - Time (5us/Div) Time (5us/Div) 8
Output Short-Circuit Protection Output Short-Circuit Protection 6 Source IN =.5 1 Sink IN =.5 Output Short Circuit (A) 5 4 3 1 Force the output shorted to ground Output Short Circuit (A) 1 8 6 4 Force the output shorted to DDQ Time (1ms/DI) Time (1ms/DI) 9
Application Information REFEN Internal parasitic diode Avoid forward-bias internal parasitic diode, to CNTL, and to IN, the should not be forced some voltage respect to ground on this pin while the CNTL or IN is disappeared. Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on REFEN is below.. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? In notebook application, using RichTek s Patent Distributed Bus Terminator Topology with choosing RichTek s product is encouraged. REFEN Distributed Bus Terminating Topology Terminator Resistor OUT OUT R R1 R R3 R4 R5 R6 R7 R8 R9 BUS() BUS(1) BUS() BUS(3) BUS(4) BUS(5) BUS(6) BUS(7) BUS(8) BUS(9) RDS(ON) (Ω) R1 R CNTL IN REFEN OUT Make sure that CNTL >= IN in all conditions including power on and off. As other linear regulator, dropout voltage and thermal issue should be specially considered. Figure 6 and 7 show the R DS(ON) over temperature of in SOP-8 and TO-5 packages respectively. The minimum dropout voltage could be obtained by the product of R DS(ON) and output current. For thermal consideration, please refer to the relative sections. R DS(ON) vs. Temperature.45 SOP-8.43.41.39.37.35.33.31.9.7.5.3-5 -5 5 5 75 1 15.48.45.4 TO-5 Figure 6 R DS(ON) vs. Temperature RN BUS(N) R(N+1) BUS(N+1) General Regulator The could also serves as a general linear regulator. The accepts an external reference voltage at REFEN pin and provides output voltage regulated to this reference voltage as shown in Figure 6, where = REF x R1/(R1+R) 1 RDS(ON) (Ω).39.36.33.3.7.4-5 -5 5 5 75 1 15
Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the. A low ESR capacitor larger than 47uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between and the preceding power converter. Thermal Consideration An internal thermal limiting circuitry shuts down the when junction temperature is over 17 C. This protects the device during overload conditions. It is noted that the thermal limiting circuitry is not intended for normal operation. For maximum reliability, the junction temperature should not exceed absolute maximum operation temperature 15 C during normal operation. The power dissipation should be well considered to keep the junction temperature within the specification. The power dissipation in is calculated as: P D = ( IN ) x I OUT + IN x I Q The maximum power dissipation can be calculated by following formula: P D(MAX) = ( T J(MAX) -T A ) /θ JA Where T J(MAX) is the maximum operation junction temperature 15 C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance θ JA highly depends on IC package, PCB layout, the rate of surroundings airflow. θ JA for SOP-8 package is 16 C/W and TO-5 package is 68 C/W on standard JEDEC 51-3 (single layer, 1S) thermal test board. The maximum power dissipation at T A = 5 C can be calculated by following formula: P D(MAX) = (15 5 C) / 16 =.65W (SOP-8) P D(MAX) = (15 5 C) / 68 = 1.471W (TO-5) Since the multiple CTRL pins of the SOP-8 package are internally shorted and connected to lead frame, it is efficient to dissipate the heat by adding cooper area on CTRL footprint. Figure 7 shows the relation about thermal resistance θ JA vs. copper area on a standard JEDEC 51-7 (4 layer, SP) thermal test board at T A = 5 C. The corresponding maximum power dissipation is shown in Figure 8. For example, with 1mm x 1mm cooper area, we can obtain the lower thermal resistance about 45 C/W. The power maximum dissipation can be calculated as: P D(MAX) = (15 5 C) / 45 =.W (SOP-8) θja ( C/W) Copper Area (mm ) ) 1 9 8 7 6 5 4 θ JA vs. Copper Area SOP-8 3 1 3 4 5 6 7 8 9 1 1 9 8 7 6 5 4 3 Copper Area (mm ) Power Dissipation vs. Copper Area TJ = 15 C Figure 7 TA = 65 C TA = 55 C 1 SOP-8.5 1 1.5.5 3 Power Dissipation (W) TA = 5 C Figure 8 11
Outline Information E b3 C R L3 D H T S L b P L A Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A.184.388.86.94 b.381.889.15.35 b3 4.953 5.461.195.15 C.457.889.18.35 D 5.334 6.3.1.45 E 6.35 6.731.5.65 H 9. 1.414.354.41 L.58 1.78..7 L.58 Ref.. Ref. L3.889.3.35.8 P 1.7 Ref..5 Ref. 5. Ref..5 Ref. R. 1.5.8.59 S.5 3.4.98.134 T.5.85..33 5-Lead TO-5 Surface Mount Package 1
A H M J B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 4.81 5.4.189.197 B 3.81 3.988.15.157 C 1.346 1.753.53.69 D.33.58.13. F 1.194 1.346.47.53 H.17.54.7.1 I.5.54..1 J 5.791 6..8.44 M.4 1.7.16.5 8-Lead SOP Plastic Package Richtek Technology Corporation Headquarter 5F, No., Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)556789 Fax: (8863)556611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 35, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (886)89191466 Fax: (886)89191465 Email: marketing@richtek.com 13