CALIFORNIA INSTITUTE OF TECHNOLOGY PHYSICS MATHEMATICS AND ASTRONOMY DIVISION Sophomore Physics Laboratory (PH005/105) Analog Electronics Phase Locked Loop (PLL) Copyright c Virgínio de Oliveira Sannibale, 2003 (Revision October 2012)
Chapter 8 Phase Locked Loop (PLL) A phase locked loop PLL 1 is a circuit with a feedback network that synchronizes an oscillator, the reference oscillator (REF), to another oscillator, the controlled oscillator (CO), so that they will oscillate (be locked together) at the same frequency. The reader should familiarize with the acronyms as soon as possible. v i Input Phase Detector Low Pass Filter Voltage Controlled Oscillator v o Output Phase Locked Loop Figure 8.1: Phase-Locked loop block diagram. To implement a PLL we need a circuit that generates a signal proportional to the phase difference between the REF and the CO. This continuously changing signal is then used to correct the frequency of the CO to be the same of the REF. In fact, if the phase difference is constant or zero the two oscillator must have the same frequency. In other words, keeping the phase differences constant makes the oscillator frequencies the same. 1 It seems that the first phase locked loop was proposed by the French scientist De Belleseize in 1932. 167
168 CHAPTER 8. PHASE LOCKED LOOP (PLL) v 2 v 1 v mix R C Figure 8.2: Mixer Phase-Detector and low-pass filter. The two cascaded circuits produce the error signal to be sent to the VCO. Another way to see this is that the time variation of phase is proportional to the frequency difference between the oscillators, and therefore the phase difference is the signal we need to correct the change of frequency between the two oscillators. LetŽs look the at Figure 8.1 containing the block diagram of a basic PLL. The reference signal from REF is sent to the PLL input, goes into the phase detector, which gives a signal proportional to the phase difference between the CO and the reference. This signal has high frequency noise and in general needs to be low pass filtered and compensated. Then, the filtered signal goes to the voltage controlled oscillator (VCO). The VCO, the core of the PLL, has a circuit to control the frequency by changing its voltage input. This input is therefore driven with a voltage with the proper sign to zero the phase difference between the reference frequency and the CO. 8.1 Phase Detector Phase detectors convert the phase difference between two signals into a signal proportional to the phase difference. Phase detectors can be classified into two types. Type I phase detectors are designed to be driven by analog signals, whereas Type II are driven by digital signal and in particular by the transitions/edges of such signals.
8.2. VOLTAGE CONTROLLED OSCILLATOR (VCO) 169 8.1.1 Type I Phase Detector, Analog Mixer The analog mixer is a device that ideally multiplies two arbitrary signals. If the two signals are simple sinusoids with the same frequency and differnt phase, the output can be decomposed into two components as shown as follows. If the two input signals are v 1 = V 1 sin(ωt), v 2 = V 2 sin(ωt+δφ 0 ), then after some algebra, the multiplied signal v mix (the mixer output) will be v mix = v 1 v 2 = 1 2 V 1V 2 sin(δφ 0 )+ 1 2 V 1V 2 sin(2ωt+δφ 0 ). The output of the mixer is therefore the phase difference of the two sinusoidal signals or their time integrated frequency difference plus a component at twice the frequency of v 1 or v 2. Applying an appropriate low pass filter, we can finally get our wished phase difference detector. 8.1.2 Type I Phase Detector, Logic Gates Another basic type I phase detector, a logic gate with a low-pass filter, is shown in Figure 8.3 together with the plots of the main circuit voltages versus time. As shown in the plots, the logic gate pulses output V xor has a duration of the phase difference between the two input signals V 1 and V 2. Those pulses are then added (integrated) together by the low pass filter producing a voltage which is proportional to the phase difference. 8.2 Voltage Controlled Oscillator (VCO) As we already said before, a voltage controlled oscillator is an oscillator whose frequency can be controlled by changing the voltage input. The following circuit shows how to implement a voltage controlled oscillator using an analog multiplier (or a mixer). Neglecting the effect of the multiplier, we can easily see that the circuit behaves like the RC relaxation oscillator. We will have therefore a square wave at the output of the Schmitt trigger, and at the integrator output, with properly chosen values of R and C, a triangular wave. Considering
170 CHAPTER 8. PHASE LOCKED LOOP (PLL) v 1 v 1 v 2 v xor R v 2 t XOR C v xor t t t Figure 8.3: Phase-Detector and low-pass filter. The two cascaded circuits produce the error signal proportional to the phase difference which is then sent to the VCO. the analog multiplier now, we can see that one can change slope of the triangular wave by changing V c. Changing that slope will increase or reduce the time required for the output to trigger the Schmitt Trigger and as a consequence it will change the square wave time period. The oscillator frequency is therefore controlled by the voltage V C. Let s now predict the oscillation frequency ω 0. The semiperiod is simply T 2 = RC If we consider now the analog multipliter In term of frequency T = 2RC V th V c R + V ss = 2RC R f + R + ν 0 = 2() 8.3 Varactors or Varycap A varactor diode or varycap is a voltage controlled capacitance. It is essentially a reverse biased p-n junction whose capacitance increase if the re- V c
8.4. CMOS 4046 PLL CIRCUIT 171 verse bias decreases. Intuitively, a reverse biased p-n junction is a capacitor with the depletion region acting as an insulator. Increasing the reverse bias the p-n depletion region increases and therefore the capacitance decrease. The major difference between a varactor and a diode is that the varactor is optimized to be a variable capacitance (as much as the technology allows) controlled with a bias. Typical values are from tens to hundreds of picofarads. Because the small variation of capacitance available they cannot be effectively used at low frequency. Varactors commonly available are the Motorola s MVAM115, and the Phillips BB112, BB212, BB204. 8.4 CMOS 4046 PLL Circuit The CMOS 4046 PLL is a integrated circuit which implements a VCO an two PDs ans some extra circuits to simplify the construction of a PLL circuit. The VCO frequency range is set with the components R 1, R 2, and C 1. Resistor R 1 and capacitor C 1 values set the maximum frequency f max of the VCO. Resistor R 2 and Capacitor C 1 set an optional frequency offset f min. The values limitations are: 5kΩ R 1 1MΩ R 2 1MΩ C 1 100pF, 5V V DD < 10V C 1 50pF, 10V V DD < 20V VCO input has a very high input impedance which allows to use a wide range of values for the capacitor C and the resistor R for the low-pass filter circuit.
172 CHAPTER 8. PHASE LOCKED LOOP (PLL) v i 14 16 V DD 8 v o 3 4 XOR PD 2 C R 6 C 1 7 9 v VCO R 1 11 VCO R 2 12 SIMPLIFIED CD4046B Figure 8.4: Simplified circuitry of the CMOS 4046 with components to set the VCO frequency range and the low-pass circuit compensating circuit.
8.5. PRE-LAB PROBLEMS 173 f VCO f max f c f min v min V DD 2 v max V DD v VCO Figure 8.5: VCO characteristic of the CMOS 4046. 8.5 Pre-lab Problems Determine the values of R 1, R 2, and C 1 to set the VCO frequency between 10 khz and 15kHz. Use the CMOS 4046 data-sheet. Sketch the VCO characteristics for the previously selected VCO frequency range and for V DD = 12V. Find the VCO gain K 0. Determine the value of the decoupling capacitor C i for the previously selected VCO frequency range. Determine the value of the low-pass filter components R, C, for a cut-off frequency of 1 khz. 8.6 Procedure Circuit Setup Familiarize wit the PLL CMOS 4046 pin-out looking at its data-sheet. Mount the CMOS 4046 circuit with the value of R 1, R 2, and C 1 calculated in the pre-labs and V DD = 12 V. Verify that the VCO minimum frequency f min is approximately correct. Explain the behavior of VCO output when its input (PIN 9) is floating or grounded.
174 CHAPTER 8. PHASE LOCKED LOOP (PLL) VCO Characteristics Measure f out versus v in VCO characteristics. Note that v in can be varied between 0V to V DD, and determine v min, f min v max, f max f c for v in = V DD /2 the VCO gain K 0, i.e. the slope of the linear range of the VCO characteristics Phase Detector Characteristics Drive the PLL inputs (pin 14 and 3) manually with a varying voltage and and 4046a square wave. Verify that the output varies accordingly to the XOR response VCO Closed Loop Characterization Verify the RC low-pass characteristics with the values of R, and C calculated in the pre-lab problems. Closed the PLL using the low-pass circuit you constructed and verify that the VCO output is phase locked to a function generator with a frequency set approximately to f c. Vary the function generator frequency and verify that the loop is till working. Find the capture range varying the frequency of the function generator