Lecture 02: Logic Families R.J. Harris & D.G. Bailey
Objectives Show how diodes can be used to form logic gates (Diode logic). Explain the need for introducing transistors in the output (DTL and TTL). Explain why Schottky transistors improve the speed of gates. Describe the operating principles of CMOS logic gates. Explain the definitions of noise margin, fanout, propagation delay, rise and fall time. Semester 2-2006 Digital Electronics Slide 2
Review of Previous Lecture You can now: Describe the important differences between analogue and digital signals. Show how to represent more than two levels using digital signals. Manipulate different codes for representing numbers and letters: natural binary, signed binary, twos complement, offset binary, Gray codes, ASCII characters. Show how to convert between binary and base 10. Write down the logic symbols for AND, OR, NOT, NAND and NOR gates. Draw up a truth table to represent relationships between inputs and outputs of a logic circuit. Semester 2-2006 Digital Electronics Slide 3
Presentation Outline Diode Transistor Logic TTL Schottky TTL CMOS Tristate logic outputs Definitions: Noise margin, fanout Timing: rise and fall times, propagation delay Power dissipation Power supply decoupling Semester 2-2006 Digital Electronics Slide 4
Diode Logic AND Gate Recall that a diode behaves like a switch. When the diode is forward biased, the switch is closed, allowing a current to flow through it. When reverse biased, it is like a switch that is turned off - no current flows. First we shall look at an AND gate. If either input A or input B goes low, it will forward bias the corresponding diode. Since the forward biased diode behaves like a switch, it will pull the output M low. The only situation when M is going to be high is when both inputs A and B are high and the input diodes are turned off. Since the output is high only when input A AND input B are high, this circuit is an AND gate. A B M 0 0 0 0 1 0 1 0 0 1 1 1 Semester 2-2006 Digital Electronics Slide 5
Diode Logic OR Gate This time, if both inputs are low, the diodes will be turned off, and the output will be low. If either input A OR input B go high, the corresponding diode will be forward biased, and pull the output M high. The biggest limitation of diode logic is that the circuits cannot be cascaded. If we follow one AND gate with another we start running into problems because the diodes are not ideal switches. If we assume a typical voltage drop across the diode when conducting of 0.6V, then when the input is at 0V, the output of the first gate will be at 0.6V. Since this is used as the input to the next gate, the output of the second gate will be 1.2V. It does not require very many gates in series before it is impossible to distinguish between a high and a low. A B M 0 0 0 0 1 1 1 0 1 1 1 1 Semester 2-2006 Digital Electronics Slide 6
Problems with Diodes If we follow an AND gate with an OR gate in diode logic, the problem is even worse: When one of the AND inputs is low, the output will be low as expected. However, when all of the AND inputs are high, all of the input diodes are turned off. The OR diode is forward biased, and therefore conducts. If the two resistors are equal, the output will be a little less than V/2. This is less than half way for a supposedly high output! We can get around both problems by using a transistor at the output of the AND or OR gate to act as an amplifier. This restores the signal levels, compensating for the voltage drop across the diode, and preventing the problems from cascading AND and OR gates. Semester 2-2006 Digital Electronics Slide 7
Diode Transistor Logic Diode Transistor Logic uses a diode logic gate as input, followed by a transistor amplifier at the output to restore the logic levels: The two diodes and resistor in the middle (in orange) provide biasing for the transistor. When point X is high (ie A, B, and C are all high), the biasing diodes conduct, turning the output transistor on. When the transistor is on, it pulls the output M low. When point X is low (if any of the inputs goes low) the diodes will turn off, and the base of the transistor is pulled low by the bias resistor. This turns the output transistor off, and the output M is pulled high by the output resistor. Overall, this is a NAND gate, since it is an AND followed by a NOT. Semester 2-2006 Digital Electronics Slide 8
Output Stage in Detail The output will be driving a load which has some capacitance from all the other inputs connected plus any stray capacitance. When the transistor turns on, it has a low resistance, like a switch which is closed. The output will go low very quickly. When the transistor turns off (for a high output), the output will change more slowly because of the RC time constant. We can make it faster by reducing the output resistor R, reducing the time constant. However, we shall then have a greater current flowing when the transistor is turned on (0 output). This will increase the power dissipation of the device. There is also a limit as to how much R can be reduced. It has to be significantly greater than the on resistance of the transistor to give a 0 output. The switching time may be improved by replacing the output resistance with another transistor. This is called active pullup. Semester 2-2006 Digital Electronics Slide 9
TTL TTL is the next logical extension on from DTL. It uses an additional transistor on the output to act as a pullup. Looking first at the output stage, we want transistors Q3 and Q4 to be in opposite states: when Q4 is on, Q3 needs to be off, and when Q4 is off, we want to turn Q3 on. This is accomplished by using a driver stage shown in orange. When X is low, this turns Q2 off, turning Q3 off. Since Q2 is off, Y is pulled high by the resistor, turning Q4 on. The output is therefore high. When X is high, this turns Q2 on, and Q3 on (since the base emitter junction of Q2 is just like a diode). Since Q2 is on, it pulls Y low turning off Q4. The output therefore is pulled low by Q3. So, from X to the output we have an inverter with active pullup (Q4) and pulldown (Q3). Looking at the input stage, we can represent the multi-emitter transistor by its simplified diode equivalent. We see that we have the diode AND gate as before. Semester 2-2006 Digital Electronics Slide 10
Schottky TTL - 1 The propagation delay of TTL is ultimately limited by the time spent getting the transistors out of saturation. When a transistor is saturated, VCE is about 0.2V. If we use a clamping diode to limit VCB to 0.3V or greater, we can prevent the transistor from going fully into saturation, allowing it to switch faster. Semester 2-2006 Digital Electronics Slide 11
Schottky TTL - 2 This is done using a Schottky diode which has a forward voltage drop of 0.3V. Such a transistor is called a Schottky transistor, and is given the symbol to the right. Using a combination of Schottky transistors and Darlington pairs (to give extra gain) gives Schottky TTL. The Schottky transistors switch faster, reducing the propagation delay. Alternatively, the resistances may be increased to reduce the power dissipation while giving the same speed as standard TTL. Semester 2-2006 Digital Electronics Slide 12
MOSFET - 1 Looking at the basic inverter first. It uses a complementary pair of MOSFET transistors. When the input is high, it turns the N-channel transistor on, and the P-channel transistor off (left figure), causing the output to go low. When the input goes low, it turns the P-channel transistor on, and the N-channel transistor off. (right figure). When the outputs are changing state, one transistor is turning on while the other off. While changing, the FETs behave like resistors, giving a conductive path between +V and ground. Because of the MOSFET s very high off resistance, static power dissipation is very low. CMOS only dissipates significant power when changing states (when both transistors are conducting). Semester 2-2006 Digital Electronics Slide 13
MOSFET - 2 Making logic gates is a very straight-forward extension of this. For example the NOR gate shown here. The output is connected to +V only when both A and B are low (0). When either A or B is high, the output goes low. Advantages of CMOS: 1. Very simple circuits 2. High input impedance 3. Low power consumption 4. Will work off a wide range of power supply voltages (3-18V) Disadvantages: 1. Slower speed because of high input capacitance 2. Prone to damage by static electricity. Modern devices overcome the slower speed by having smaller devices (smaller capacitance) and reducing the ON resistance of the transistors, allowing them to charge and discharge the capacitive load more quickly. Semester 2-2006 Digital Electronics Slide 14
Tri-state Logic This is not a logic family as such, but is a variation on the other families that allows them to be used in bus applications where several outputs may share a common signal line. Tristate devices have 3 output states: High, Low, and Disabled or high impedance. The output stage consists of 2 transistors which we can think of as switches. Drawing a truth table of our output: A B Output Open Open Disabled High Z Open Closed 0 Closed Open 1 Closed Closed Not Allowed Semester 2-2006 Digital Electronics Slide 15
Some Definitions Let us look at how a digital signal is represented on a line. It will be assumed that we are working with a 5V supply, since that is the most common standard for discrete logic devices. We can represent each state by one of the two conditions of a circuit. However, this "ideal" representation is not possible because of noise, tolerances, component limitations, etc. In practice, we have a range of allowed inputs for each state (shown in blue). The outputs must be well within this range to allow for noise (shown in red). The ranges in between are called noise margins. Semester 2-2006 Digital Electronics Slide 16
Some Example Noise Margins TTL CMOS 5V V OH 2.4V 4.95V V IH 2.0V 3.5V V IL 0.8V 1.5V V OL 0.4V 0.05V Noise Margin 0.4V 1.45V Semester 2-2006 Digital Electronics Slide 17
Fanout Fanout is defined as the number of inputs that an output can drive while remaining within the limits. For TTL this is limited by the output current capability, and the amount of current required by each connected input. For CMOS, fanout is limited more by the desired operating speed. As more inputs are connected to an output, the capacitive load increases, and this takes longer to switch. Semester 2-2006 Digital Electronics Slide 18
Timing 1 Propagation delays are measured from the 50% level to the 50% level. Note that t PHL and t PLH are not necessarily equal. When a single figure is quoted, it is usually the average of these two. Rise and fall times are measured between the 10% and 90% levels. Semester 2-2006 Digital Electronics Slide 19
Timing 2 Typical Power Consumption Propagation Delays Static Dynamic (100 khz) TTL CMOS standard 74xx 10 mw Low power Schottky 74LSxx 10 ns 2 mw 74HCxx 8 ns 0.002 µw 75 µw 4000 series 100 ns 0.1 µw 100 µw Some typical values Semester 2-2006 Digital Electronics Slide 20
Power Supplies TTL requires a stable power supply 5 V ± 5% In contrast, CMOS is able to work off a wide range of supplies 74HC series 2-6 V 4000 series 3-18 V Many modern devices even operate at reduced voltages 3.3V, 2.5V or 1.8V. The advantages are: Lower power consumption (for a given load resistance or capacitance, power dissipated is proportional to voltage squared). Particularly useful for battery operated devices. Lower voltage means devices can be smaller because the dielectric layer can be thinner. Smaller devices mean higher packing densities, and shorter connections between devices (lower internal propagation delay). Semester 2-2006 Digital Electronics Slide 21
Practical Considerations Decoupling When constructing circuits, it is important to have power supply decoupling capacitors placed close to the chip. As the outputs change state, there is usually a surge of current into the chip. A decoupling capacitor is able to provide the needed charge while reducing the noise on the power supply. It should be as close as possible to the chip to minimise the inductance of the interconnection. Unused inputs When considering what to do with unused inputs, you need to consider the logic family, and what the circuit will do if left unconnected. TTL gates require an input current to turn the input transistor on. They therefore behave as though they have an internal pullup resistor, and will behave as a high input if left unconnected. CMOS gates have an extremely high impedance input. They are effectively capacitive inputs. Any nearby signal can be picked up by capacitive coupling (through stray capacitance) and can potentially interfere with the circuits operation. All unused CMOS inputs should therefore be tied to either 0 or 1. In general, it is good practice not to leave unused inputs unconnected, regardless of whether they are TTL or CMOS. Semester 2-2006 Digital Electronics Slide 22