LSN 3 Logic Gates Department of Engineering Technology
LSN 3 Inverter One input and one output Produces a compliment of the input Negation indicator Truth table Active low output In Out 0 1 1 0 Active low input
LSN 3 Inverter Timing diagram Logic expression Compliment (inversion)
LSN 3 AND Gate Two or more inputs and one output Produces a high output when all of its inputs are high Truth table A B Out 0 0 0 0 1 0 1 0 0 1 1 1
LSN 3 AND Gate Timing diagram Logic expression Boolean multiplication
LSN 3 OR Gate Two or more inputs and one output Produces a high output when any of its inputs are high Truth table A B Out 0 0 0 0 1 1 1 0 1 1 1 1
LSN 3 OR Gate Timing diagram Logic expression Boolean addition
LSN 3 NAND Gate Two or more inputs and one output Produces a low output only when all inputs are high Truth table A B Out 0 0 1 0 1 1 1 0 1 1 1 0
LSN 3 NAND Gate Timing diagram Logic expression
LSN 3 NAND Gate NAND as negative-or Inputs are active low Output produces a high when any input is low Used to detect when any input is low
LSN 3 NOR Gate Two or more inputs and one output Produces a low output when any of its inputs are high Truth table A B Out 0 0 1 0 1 0 1 0 0 1 1 0
LSN 3 NOR Gate Timing diagram Logic expression
LSN 3 NOR Gate NOR as negative-and Inputs are active low Output produces a high when all inputs are low
LSN 3 Exclusive-OR / Exclusive-NOR Two inputs and one output Produces a high output when the inputs are at opposite logic levels or same logic level Truth table A B Out 0 0 0 0 1 1 1 0 1 1 1 0 A B Out 0 0 1 0 1 0 1 0 0 1 1 1
LSN 3 Exclusive-OR / Exclusive-NOR Timing diagram Logic expression
LSN 3 Logic Gates Fixed Function Logic CMOS, TTL, ECL CMOS Dominant technology Low power Improved switching speeds 5v or 3.3v operations TTL Original logic technology Less susceptible to static discharge High switching speeds 5v operation only
LSN 3 Logic Gates Logic package identification Series Designator XXX YYY Series designator: Identifier Digits 74 74S 74AS 74LS 74ALS 74F 74HC 74AC 74AHC 74LV 74LVC 74ALVC Standard TTL Schottky TTL Advanced Schottky TTL Low-power Schottky TTL Advanced Low-power Schottky TTL Fast TTL High-speed CMOS Advanced CMOS Advanced High-speed CMOS Low-voltage CMOS Low-voltage CMOS Advanced Low-voltage CMOS
LSN 3 Logic Gates Identifier digits:
LSN 3 Logic Gates Performance metrics Propagation delay: time interval between application of an input pulse and the occurrence of the associated output pulse Power dissipation: Product of the supply voltage and average supply current Speed-Power product Measure of the performance of a logic circuit by looking at propagation delay time and power dissipation Fan-out and loading Fan-out is the maximum number of similar gate inputs that can be connected to an output and still maintain proper output voltage levels Example datasheet
LSN 3 Homework Reading Chapter 3.1 3.7 Problems HW4 Chapter 3, problems 2, 5, 12, 16, 20, 24 Show all work and graph all waveforms on engineering/graph paper for credit References Datasheets http://www.alldatasheet.com/ http://www.chipcatalog.com/ http://focus.ti.com/logic/docs/logicportal.tsp?templateid=5985 (TI) http://focus.ti.com/lit/an/szza036b/szza036b.pdf (how to read them)