Realization of 8x8 MIMO-OFDM design system using FPGA veritex 5

Realization of 8x8 MIMO-OFDM design system using FPGA veritex 5 Bharti Gondhalekar, Rajesh Bansode, Geeta Karande, Devashree Patil Abstract OFDM offers high spectral efficiency and resilience to multipath channel effects. MIMO makes use of multiple antennas to increase throughput without increasing transmitter power or bandwidth. By implementing a MIMO OFDM baseband transceiver on an FPGA with proper selection of one of the four constellations which vary in terms of the convolution coding rate, the parsing method and modulation type (e.g. data rate 90 Mbps using QPSK at the code rate of ½ using Spatial Multiplexing, reduction in PAPR by 5dB using SLM technique and BER achieved up to 10-6 ) thereby the project is expected to fulfill the need for high-speed data transmission for a wireless communication system with cost effective hardware implementation. This architecture utilizes 75% Slice registers, 64% of slice LUT s, 72% of memory on vertex 5 board. Index Terms Field Programmable Gate Array (FPGA), Multiple Input Multiple Outputs (MIMO), Orthogonal Frequency-Division Multiplexing (OFDM), Peak To Average Power Ratio (PAPR), Quality of Service (QoS), Selective level Mapping (SLM), Space Time Block Code (STBC). I. INTRODUCTION One of the major challenges facing modern communications is to satisfy the ever increasing demand of high speed reliable communications with the constraints of extremely limited frequency spectrum and limited power. Wireless communications systems like cellular mobile communications, internet and multimedia services require very high capacity to full fill the demand of high data rates. This necessitates the need for communication systems with increased throughput and capacity. Multiple input multiple outputs and orthogonal frequency division multiplexing (MIMO-OFDM) is one way to meet this need. OFDM offers high spectral efficiency and resilience to multipath channel effects [1]. OFDM is a technique that divides a communication channel into a number of equally spaced frequency bands. Manuscript received Aug, 2014 Bharati Gondhalekar is currently pursuing masters degree program in electronics and telecommunication engineering in Mumbai University, In-dia, PH-+91-9423365470. Mr. Rajesh Bansode is currently Assistant Professor of Thakur College of Engineering and Technology in Mumbai University, India, PH-+91-9820271046. Geeta Karande, Electronics and Telecommunication, Mumbia University/ Thakur college of Engg, Mumbai, India, 9870123474. Devashree Patil Electronics & Telecommunication,Mumbai University Thakur college of Engg, Mumbai, India,, 996743776 Section II depicts details of OFDM transceiver and PAPR reduction technique SLM. Section III gives idea of design methodology, Section IV depicts Simulink model, its subsystems (Transmitter module and receiver module), Section V gives simulation results. A subcarrier carrying a portion of data is transmitted in each frequency band. Each subcarrier is orthogonal (independent of each other) with every other subcarrier, differentiating OFDM from the commonly used FDM. OFDM is sometimes called multi-carrier or discrete multi-tone modulation [2] as shown in Figure 1. MIMO makes use of multiple antennas to increase throughput without increasing transmitter power or bandwidth. Figure 1 OFDM subcarriers showing ortho gonality The Xilinx Integrated Software environment (ISE) is used as the synthesizer in the design flow diagram. Model Sim is used to verify the hardware simulation of the blocks by using test vectors generated by System Generator or HDL test benches [8]-[10]. Finally synthesis and performance results of the blocks are reported using ISE, and bit streams are generated to pro-gram the FPGA board II. TRANSCEIVER OF OFDM Figure 2 shows OFDM Transceiver. The input bits are equiprobable and independent they are grouped into blocks of the size log2m where M is the signal constellation size. The modulation scheme is usually chosen by the system designers or based on the requirements [1]-[3] of the wireless communication systems. Each block of bits is mapped into a modulated symbol, denoted as X[k], using the chosen modulation scheme or based on the signal constellation. The output signal is then converted from serial order to parallel order before IFFT and is converted back to serial order again. 1151

The mathematical representation for the transmitted signal, x (n) as After receiving x(n), the signal is converted into parallel order and processed by FFT. Then it is converted back to serial order. The FFT process is represented as Figure.2 OFDM transceiver block diagram The demodulation process maps the symbols back to bits based on the same mapping that the modulation uses. Assuming there is no noise or distortion imposed on the transmitted signal, the receiver is then able to recover the data perfectly [3]. The basic idea of SLM technique is to generate several OFDM symbols as candidates and then select the one with the lowest PAPR for actual transmission. This technique is a variation of selective mapping (SLM), in which a set of independent sequences are generated by some means from the original signal, and then the sequence with the lowest PAPR is transmitted as shown Figure 3. Figure 4 Field Programmable Gate Arrays FPGA [8] is the best choice for OFDM implementation since it gives flexibility to the program to reconfigure the design besides low cost hardware component compared to others. MATLAB Simulink 2013, Xilinx ISE 14.7 Model Sim 6.3 is the basic requirement as shown in Figure 4. The algorithm of each block using MATLAB Simulink is implemented by use of constructing block diagrams in Simulink. VHDL code is imported into Simulink via the Xilinx System Generator block set, which gives flexibility to design flow. Simulink and Xilinx System Generator create bit-true. The Xilinx Integrated Software environment (ISE) is used as the synthesizer in the design flow diagram. Model Sim is used to verify the hardware simulation of the blocks by using test vectors generated by System Generator or HDL test benches [8], [9]. Finally synthesis and performance results of the blocks are reported using ISE, and bit streams are generated to pro-gram the FPGA board [10]. Develop algorithm & system model Simulink MDL Code Generation (system generator) HDL test Test RTL HDL & Figure 3 Block diagram of SLM III. DESIGN METHODOLOGY Since OFDM is carried out in the digital domain, there are several methods to implement them. ASICs (Application Specific Integrated Circuit), Microprocessor or Micro Controller and FPGA (field-programmable gate arrays) are some of the methods. Hardware Simulation (Model Sim) Xilinx Implementation Bit Download to FPGA (Vertex, etc) Figure 5 Methodology Diagram 1152

IV. SIMULINK MODEL V. SIMULATION RESULTS The Figure 6 represents the complete 8x8 MIMO-OFDM Simulink model. A signal is provided as input by connecting the Gateway_ In to the work-space with the support of a manual switch. The Gateway_ In block is required to convert input which is of Simulink type to Xilinx type. The signal is then connected to the parallel to serial convertor and it is later applied to the Subsystem. Audio input is provided as input to Simulink model whose scope output is shown in Figure 9. A. Output of audio signal Audio signal is given as the input to the Simulink model which is observed in the scope. The received audio signal is magnified in the scope as depicted in Figure 9. ` Figure 6 Simulink Model The transmitter module and the receiver module are depicted in Figure 7 and 8 respectively. Figure 9 Received and Original Audio signal B. JTAG Co simulation model JTAG model shown in Figure 10 is used for hardware co simulation. In this model input image is given which is considered as workspace input. After execution of this model test benches are generated which are shown in Figure 14. Figure 7 Transmitter module The Gateways are used to convert Xilinx type to Simulink type output or vice versa. At the end a scope is connected where the first plot is for output of the model followed by second plot as the input signal applied to the model shown in Figure 9 below. The use of this is to verify the same signal is reproduced at the receiver side. Figure 10 JTAG Co simulation for Image C. Device utilization summary: This architecture utilizes 75% Slice registers, 64% of slice LUT s, 72% of memory as shown in Figure 11. Figure 8 Receiver module Figure11 Design utilization Summary 1153

D. RTL Schematic: In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers and the logical operations performed on those signals. Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design. Figure 14 Test Bench generated for Image Figure 12 RTL Schematic When designing digital integrated circuits with a hardware description language, the designs are usually engineered at a higher level of abstraction than transistor level or logic gate level. In HDLs the designer declares the registers (which roughly correspond to variables in computer programming languages), and describes the combination logic by using constructs that are familiar from programming languages such as if-then-else and arithmetic operations. This level is called register-transfer level. The term refers to the fact that RTL focuses on describing the flow of signals between registers. F PAPR reduction using SLM Whereas in case of a system with SLM there is constant value for some time and gradually decrease at the end. For without SLM system the PAPR probability remains constant till 14 db and deceases abruptly [4]-[7]. For SLM system, the PAPR probability is constant up to 9dB and decreases abruptly later on. A difference of PAPR reduction levels in two techniques is achieved. Figure 15 PAPR reductions with & without SLM Figure 13 RTL Schematic inside mimo8_cw 1 E. Test bench generated for input image: Test bench is generated by configuring FPGA on JTAG co simulation. Figure 14 below depicts the test bench generated for input as image. Table 1 Comparison of PAPR with and without SLM PAPR PAPR PAPR Probability Probability with (db) without SLM SLM 1 0.942 0.842 3 0.94 0.84 5 0.94 0.822 7 0.937 0.765 9 0.937 0.665 11 0.937 0 13 0.933 0 15 0.427 0 1154

VI RESULTS By implementing a MIMO-OFDM baseband transceiver on an FPGA, high-speed data transmission for a wireless communication system with reasonable prices of hardware implementation is achieved. PAPR reduction using SLM technique is achieved a 5dB reduction in comparison to the model using non SLM technique, data rate of 90 Mbps is achieved using QPSK at the code rate of ½ using Spatial Multiplexing. Using XILINX 14.7 software for simulation and then it is tested on VIRTEX 5 XC5VLX50T. The results obtained are stable and reliable. This architecture utilizes 75% Slice registers, 64% of slice LUT s, 72% of memory on vertex 5 board. ACKNOWLEDGMENTS I express my deep and sincere gratitude to my project guide Prof. Rajesh Bansode for his unreserved guidance and support. I am truly thankful to him as he has spent lots of time to review and critique this paper. At the same time, he also gave a lot of valuable construction suggestions which made this paper became more precise and normative. REFERENCES [1] N. Chide, S. Deshmukh, Prof. P.B. Borole, Implementation of OFDM System using IFFT and FFT IJERA, ISSN: 2248-9622 vol. 3, no 1, Feb 2013, pp.2009-2014. [2] A. Ramezani, A Novel Technique for Time Synchronization in OFDM Systems, Journal of telecommunications, vol. 10, no 2, Sept 2011. [4] S.Bhagwatkar, B. P. Patil, and P. Kasliwal, Performance of OFDM system Modified SLM Technique with DQPSK, Journal of telecommunications, vol.11, no 2, Dec 2011. [5] D.Lim, J-Seon A New SLM OFDM Scheme With Low Complexity for PAPR Reduction, IEEE Signal Processing Letters, vol. 12, no 2, 2005. [6] P.Sharma and S.Verma PAPR Reduction of OFDM Signals Using Selective Mapping with Turbo Codes International Journal of Wireless & Mobile Networks (IJWMN) vol. 3, no. 4 Aug 2011. [7] S. Singh,J. Malhotra, M. Singh, A Novel SLM based PAPR Reduction Technique in OFDM-MIMO System International Journal of Computers & Technology, vol. 2, 2008. [8] K. Chang and G. Sobelman FPGA Based Design of a Pulsed-OFDM system, IEEE, APCCAS, pp.1128-1131, 2006. [9] L. J. Cimini Jr, Analysis and simulation of a digital mobile channel using orthogonal frequency division multiplexing, IEEE Transaction Communication, vol. 33, pp. 665 675, Jul 1985. [10] J. Babu, Sri. R. Krishna,.P Reddy, A review on the design of MIMO antennas for upcoming 4G communications, IJAER, DINDIGUL vol 1, no 4, 2011. [3] A. Mhatre, A. Singh, A. Raut Orthogonal Frequency Division Multiplexing for Wireless Networks ISSN: 2278-9057 IJIIT, vol-1, no-3, Paper-09, Jan 2012-2013. 1155