Department o Computer Science and Engineering 2--8 Power ampliiers and the use o pulse modulation Switching ampliiers, somewhat incorrectly named digital ampliiers, have been growing in popularity when it comes to circuits or power ampliication, both or pure ampliication and as drivers or among other things motors. The reasons or this are primarily the simplicity o the circuitry and the low loss which makes it possible to create cheap applications with low power dissipation. We are going to have a look at this group o ampliiers but we will start with an exposé o the commonly used types o ampliication, discuss their merits and limitations and then turn our attention to switching ampliiers. The switching ampliiers need some kind o modulation o the pulse signal driving the ampliier and we will have a look at some schemes or doing this. We will have a look at pulse width modulation (PWM) and pulse density modulation (PDM). Let s start by deining what an ampliier is. Ampliiers An ampliier has the purpose o increasing some aspect o a signal. We can identiy three dierent types. Ampliiers that are designed to increase only the signal voltage (voltage ampliiers), to increase only the current (buers) or to increase both (power amps). We will concentrate on the latter type. Ampliiers typically operate rom a single sided power supply with only a positive or negative power rail and ground or rom a double sided, balanced, power supply with both positive and negative rails. The dierent methods o supplying power results in dierent approaches when it comes to biasing the power element, in most cases one or more transistors. With bias we mean some means o making sure that the transistors works in their active regions. We will not describe all these approaches. A number o dierent principles or power ampliication have evolved and these principles are divided into dierent classes o ampliiers that are identiied using letters rom the alphabet. By now almost all letters are used to name dierent ampliier classes. Some o the classes CHALMERS TEKNISKA HÖGSKOLA Institutionen ör data- och inormationsteknik Sida Avdelningen ör datorteknik Besöksadress: Rännvägen 6 42 96 Göteborg
are very specialized or used only by just one or a ew companies. We will describe the most common classes o ampliication. Ampliier classes In this discussion we will only be discussing dierent types o ampliiers intended or power ampliication, that is we are not only interested in raising the voltage level but also increasing the current through the load. We will only look at transistor ampliiers. The classes will be described using schematic circuits and these schematics are very simpliied and would not work in a real design. Class A In the simplest orm o class A ampliier we use one transistor as the ampliication stage, Figure. This transistor is biased to a quiescent state where hal the available current low through the transistor and the voltage across the load is hal the supply voltage. The input voltage will modulate (change) the base voltage o the transistor and as a result the current through the transistor and the voltage across the load will vary around the quiescent values. Because o the variation around the quiescent state (Q-point), Figure 2, which lies in the active region o the transistor, Figure Class A ampliier this ampliier can be made very linear but at a cost. Since the transistor is conducting even when there is no input signal the power consumption will be large and most o the power will be dissipated as losses, as heat. The eiciency o the class A ampliier will be less that 25 %, that is more than 75 % o the power will be lost in the orm o heath that has to be transported away i the transistor is not to be destroyed. Because o this it is uncommon to use this type o ampliier or powers higher than some tens o Watts. Figure 2 Bias point or class A ampliier Page 2
Class B In the class B ampliier we try to solve the problem o the large power consumption and the low eiciency o the class A ampliier. We have two transistors in a so called push-pull coniguration and we make sure that each o these devices is conducting during separate hal periods o the input signal, Figure 3. When the input signal U IN is zero and the circuit is at rest none o the transistors conduct and there will be no power dissipation. The coniguration has some problems though. A transistor is not linear over the whole span rom very small to large signals, we have an unlinear area or both small and large signal levels. At low levels the transistor will not conduct properly and large signal levels we will get saturation. In this case the unlinearity at small signal levels is the problem. Because o the unlinearity the output signal will be distorted or small positive and negative signals. We will get what is called crossover distortion, Figure 4. Class B ampliiers can theoretically give an eiciency o 78 % but will in reality give a lower eiciency. The crossover distortion makes them unsuited or the ampliication o linear signals such as audio. Class AB Figure 3 Simpliied class B ampliier A class AB ampliier is a combination on the class A and class B theme. We start rom the class B coniguration but we make sure that the two transistors have small bias voltages on their bases even at rest. The bias circuit can in a simpliied orm be described as two diodes, Figure 5. By doing this to make sure that the transistors work in their linear regions. The price we have to pay or placing the transistors in their active regions is that the bias voltages make the transistors conduct even at rest resulting in both voltage over the transistors and current trough them and thereby giving raise to power losses. This type o ampliier will seldom have an eiciency o more than 5 %. Figure 4 Crossover distortion The class AB type o power ampliier is by ar the most requently used ampliier type since it is quit easy to design with a reasonable eiciency. U IN V DD -V DD R LOAD Figure 5 Simpliied class AB ampliier Page 3
Class C The class C ampliier is a bit special and can only be used under special circumstances, Figure 6. The circuit can give large ampliication but it is highly nonlinear meaning that it gives dierent ampliication or dierent requencies in the input signal, Figure 7. The nonlinearity can be o an acceptable level i we use the circuit over a small, narrow requency range which is something we ind in radio transmitters and receivers (transceivers) where the low requency signal is modulated on a high requency carrier wave and thereore just gives a narrow requency band around the carrier wave requency. With the development o modern class AB ampliiers these have gradually started to replace class C ampliiers also in radio applications. Figure 6 Simpliied class C ampliier Class G Figure 7 Class C requency plot A class G ampliier is a variation o the class AB ampliier. In order to decrease the unused voltage over the transistor when the input signal is low we use a lower voltage rom the power supply when the signal amplitude is low. To do this the power supply has a number o rails that supply dierent voltages and the rail that has enough voltage is switched in. Class H In class H we reine the theme o the class G ampliier. Instead o switching in dierent voltage rails rom the power supply we modulate the power supply voltage to make the supply voltage just some volts larger than the output voltage at any given time. The well known power ampliier vendor Labgruppen in Kungsbacka uses this method in many o their devices. Switching ampliier (Class D) We have seen that a problem with the ampliier types mentioned so ar is the power dissipation, the eiciency. Power is proportional to the voltage across the device and the current through it, P ~ U I, that is we could minimize this product by making either o the two properties, or both small and the irst o these options is the idea behind the switching ampliier. We have a number o dierent types o switching ampliiers but the most common type is reerred to as a class D ampliier, Figure 8. Observe that the D Page 4
does not stand or digital but just happens to be the next letter in the alphabet since this type were classiied beore the class G, class H and other types. We still have two transistors in a push-pull coniguration but we switch the transistors between two extreme states, non-conducting and saturated. In the non-conducting state the voltage across the transistor will be high and in the saturated state it will be low. When one o the transistors is non-conducting the other will be satu- Figure 8 Simpliied class D stage rated. Now how does this help us? No current will low through a non-conducting transistor so there will be no power dissipation no matter the size o the voltage across it. When the transistor is saturated the voltage across it will be small (around.2 Volts) and the power dissipation will be, not zero, but small although the current through the transistor might be high. This means that the power dissipation will be low in both cases and the eiciency will be high. This might seem nice but i we think a bit urther we realize that switching the transistors between two states, conducting and non-conducting can only give a aithul representation o the input signal i this is a square wave. Our aim is to ampliy analog signals, that is signals that can take on any voltage within their deinition range. This means that we have to introduce some orm o transormation o the analog signal into pulses that can switch the ampliier. We need some kind o modulator. Dierent types o modulation are used and we will discuss three o these, pulse width modulation (PWM), pulse density modulation (PDM) and sigma-delta modulation (Σ-Δ). Ater the ampliication we need some way to transorm the pulses back to an analog signal. We shall see that we can use a low pass ilter or this purpose. Pulse width modulation (PWM) In pulse width modulation (PWM) we use a modulator to change the duty cycle o the input pulse train into the class D ampliier in accordance with the analog voltage level. The duty cycle describes how large part o a period in the pulse signal that will be high (one) compared to the period time, the value is mostly given in percent. pulse time Duty cycle period time % A duty cycle o zero () percent means that the signal is always low, a duty cycle o 5 percent means that the signal is high during hal the period and low during the other hal, 75 percent duty cycle means that the signal is high during three ourths o the period time and a duty cycle o percent means that the signal is always high, Figure 9. Figure 9 Example o duty cycles Page 5
Now the unction o the PWM modulator is to create this pulse signal with varying duty cycle. The simplest way to directly transorm an analog signal to a PWM-signal is to connect the analog signal and a high requency triangle wave to the two inputs o a comparator, Figure. The requency o the triangle wave will give the requency o the PWM signal. The PWM signal is high when the input signal has a higher value than the level o the reerence triangle wave and low when the input signal has a lower value than the reerence triangle wave. Instead o using a triangle wave the modulator signal could also be generated digitally or come rom an A/D converter. Let s say that we have the latter. We deine the period o the generated pulse signal as a number o clock cycles. The easiest choice is to relate it to the resolution o the A/D converter. Let s say that the A/D converter works with n bits. The number o values we can have with this resolution is N = 2 n and i we set the pulse period to N clock cycles then the reading rom the A/D converter will simply give the number o clock cycles under a period where the signal should be high, that is it will directly give the duty cycle. We will get back to reasons or choosing other period times later. In most PWM-devices we have the option o deciding i the PWM-period should start with a low or a high level. In some devices we can also decide i the signals should be let or center aligned. The dierence could easily be seen i we have two PWM-channels with the same requency but dierent duty cycles. I the signals are let aligned it means that a new period o the signal starts at the same time on both channels. In Figure we have an example o this when the periods start with a high level. The result o the let alignment will be that i the two channels turn on some power hungry devices there will be a sudden current increase on both channels at the same time and this might cause some disturbance and place a big load on the power supply. I the PWM-signal is center aligned it is the center o the period that is at the same instance o time on both channels, Figure 2. Now the devices won t turn on at the same Figure Comparator as PWM-modulator Figure Let aligned PWM-signals Figure 2 Center aligned PWM-signals time as long as the two channels doesn t have the same duty cycle. In the example in our igures the period time o the center aligned signals are twice the period time o the let aligned signals. This is because the symmetrical PWM signal is in our device Page 6
generated by irst counting up a let aligned signal starting with low level and then counting the other way around starting with high level. Pulse density modulation (PDM) We saw earlier that in PWM we varied the duty cycle o our square wave according to the voltage level in our input signal. In pulse density modulation (PDM) we let the pulse signal be either high our low during the whole pulse period but we vary the number o periods that are high and the number o periods that are low in accordance with the level o the input signal, Figure 3. Figure 3 Pulse density modulated signal Beore we discuss our third modulation method, sigma-delta modulation, we will study our output signal or a while. Making the output signal analog I we look back on our goal it was to use the modulated signal to generate an analog output signal but so ar we have not reached this goal. Our output signal is still just a pulse train even i the power has increased. We need to do something about the pulse signal. Let s ocus our discussion on the PWM signal. I we analyze the requency content o the square wave with varying duty cycle (Fourier analysis) we will ind that the signal can be described by the equation T k sin 2 4 2 T k t A A cosk t k 2 T where the signal properties are deined by Figure 4. From the equation we can see that the signal can be separated into a DC level A T and an ininite sum o requency components. The requency components have requencies k where k =, 2,3,, that is we have the undamental requency which is the same as the requency o the pulse train and the other requencies are integer multipliers o this requency. In reality the number o requency components is not Page 7
ininite. This would only happen i the signal transitions rom low to high and rom high to low were ininitely ast and this cannot be done with real components since it would take an ininite bandwidth. The DC level will vary with the duty cycle o the square wave, that is when we vary the duty cycle o the PWM signal this level will vary as the analog output signal that we are looking or. To be precise this is not a DC level but a low requency signal since it will vary with the duty cycle that we are constantly changing. Now all we want to keep is this slowly varying DC level and we want to remove the other requencies, that is the undamental requency and its overtones, rom the signal. These requencies will have higher requencies than the requency o the variation in the DC level and we can use a low pass ilter to remove them. An ideal low pass ilter allows low requencies to pass unaltered while higher requencies are blocked out. In a real implementation o the ilter the higher requencies will not be removed but they will be more or less attenuated. To get a ilter with low losses we will use a LC-ilter, in this case a second order ilter, Figure 5. I we analyze the ilter we will get the transer unction Figure 4 Pulse train U IN L C Figure 5 Output ilter R LOAD U OUT H R j C j L R j C 2 LC j L R 2 j Q 2 j Q where the cut o requency is 2 LC and the Q value Page 8
Q R C L For Q values o.5, and 2 and a normalized cuto requency o Hz we have the requency plots (amplitude) in Figure 6. We can see that when the requency gets above the cut o requency the signal will be more and more attenuated the higher the requency is (or as second order ilter the slope o the attenuation goes towards -2 db/octave or -4 db/decade). To reduce the higher requency components o our PWM signal eiciently we need to make sure that these requencies are well damped by the ilter. To accomplish this these requencies need to be much higher than the requency o the varying DC level that we want to keep. To ensure this the pulse requency o the PWM signal should me much higher than the highest signal requency. We could make a more eicient ilter by increasing the order o the ilter but then the ilter would be more complicated. Since it is easier to design active ilters o higher order than what it is to design passive ilters o the same order one might think that we could replace this passive ilter with an active ilter but we have to remember that the ilter should be placed ater the power ampliier and the operational ampliier in the active ilter cannot handle this kind o power so we have to stay with the passive ilter. Sigma-delta modulation (Σ-Δ) Amplitude (db) I we look pack to our paper on A/D- and D/A-converters we will ind that the output o a D/A converter had to be low pass iltered to remove the staircase shape given by the limited resolution o the DAC. We stated that this error could be described as a noise loor on our signal, Figure 7. In our current case with PWM Figure 7 Noise in DAC signal modulation the noise is even more o a problem since we don t have the staircase o the DAC signal but a signal switching all the way between positive and negative level which means that there are more noise to ilter away. Now getting back to our ADC/DAC paper we can remember that by using a sigmadelta modulator we could shape the noise so that a large part o it moved to higher Page 9-5 - -5-2 -25-3 -35-4 LC ilter db-scale Q=.7 Q= Q=.5-45 - Frequency (Hz) Figure 6 Frequency plot o LC ilter Q, 5, and respectively, Hz 2
requencies, Figure 8. We can take advantage o this in our present application and use a sigma-delta modulator in our switching ampliier. The modulator is placed where we orm the shape o our pulse signal, that is beore the PWM and the power stage. Figure 8 Shaped noise using sigma-delta modulator Resolution and ilter damping When we generate the PWM signal in our processor we set the period o the PWM signal to a number o clock periods and we set the duty cycle by controlling during how many o these clock periods the signal should be a logic one (). The resolution o our PWM signal, that is the number o dierent duty cycles the signal can have, is governed by the period o the signal, that is by the number o clock cycles that orm one period o the PWM signal. I we have n bits o resolution we will get N = 2 n dierent duty cycles or our PWM-signal with the relative lengths ranging rom zero () to N -. This should cover the range rom % to % duty cycle which means that when we generate our PWM-signal using the system clock with a requency s and a period Ts the s period o our PWM-signal becomes (N ) T s and the requency o our PWM-signal becomes s. N Now since the processor clock has a ixed requency the requency o the PWM signal will get lower when we increase the resolution by increasing the number o clock periods in the period time. A lower requency or the PWM signal means that it will get closer to the requencies o the desired signal, the variation in the DC level. This will give a lower damping o the unwanted requency components in the LC ilter i we don t increase the order o the ilter. As a consequence we can see that the quality o the output signal is a tradeo between the resolution o the PWM signal and the damping o the ilter, Figure 9. Amplitude (db) -5 - -5-2 -25-3 -35-4 LC ilter db-scale Q=.7 Q= Q=.5 Low PWM requency High resolution Low damping High PWM requency Low damping High damping -45 - Frequency (Hz) Figure 9 Tradeo between resolution and dampling Page
Other PWM applications Pulse width modulation has or a long time been used or the control o the speed in DC motors. There are several reasons or this. The accuracy o the speed, that is the resolution o the PWM signal is in many cases not that critical. The ability o the motor to react to duty cycle changes in the controlling PWM signal is pretty slow which means that the PWM requency can be low. Actually the motor in itsel acts as a low pass ilter which means that in many cases we can control the motor using the PWM signal directly and do away with the ilter. These things put together give a very simple implementation o the PWM control used or DC motors. Full class D ampliier I we put the parts together we get the ull class D ampliier starting with an analog signal and ending with a power ampliied version o this signal. There are two basic versions o the class D ampliier and they are class D ampliiers with and without eedback. The ampliier without eedback is simpler so we will start with this type. Class D ampliier without eedback The class D ampliier without eedback can be described by Figure 2. Figure 2 Class D ampliier without eedback The analog signal is irst sampled and AD converted to a digital signal with n bits. The sampling requency here is just high enough to avoid aliasing in the sampling that is the sampling requency is just over double the maximal signal requency. This requency is too low to give a good result in the PWM converter and the signal is thereore up sampled (interpolated) to a higher sampling requency. This requency is an integer multiplier o the original sampling requency. A sound signal is oten sampled with the requency 44, khz and with a resolution o 6 bits. We remember rom earlier that to have the ull 6 bits resolution in the PWM we would need a system clock requency o System clock requency 2 6 44, khz 2, 89 GHz This is way too high. Instead we lower the number o bits to three or our by using a delta/sigma converter and this means that the system clock requency would only be 8 or 6 times the sampling requency. Ater the PWM stage the signal is ampliied by the power stage which ollows the principle in Figure 6. Finally the signal is low pass iltered and applied to the load. Page
This is a very simple design but the drawback is that we have no control over i the resulting signal is good since we never check the output signal. To do this we need eedback o the result, o the output signal. We need a class D ampliier with eedback. Class D ampliier with eedback We have a class D ampliier with eedback in Figure 2. Figure 2 Class D ampliier with eedback We can see that the structure is quite similar to the ampliier without eedback but with some extra blocks. We take the output signal either beore or ater the output ilter and eed this back as a control signal. Now this is an analog signal so we have to AD convert it beore it is used. The output signal has ripple especially i we take it beore the output ilter so we have to ilter the signal beore the ADC. There is also a new ilter in the main path, the loop ilter. This ilter attenuates noise rom the ADC and gives requency correction in the passband. In the design o a good class D ampliier with eedback the demands on the ADC in the eedback loop is quite high. Pros and cons with class D ampliiers The big advantage with the class D ampliier is its high eiciency, it can be around 9 % or even more. In many cases it is also an advantage that i we leave out the ADC at the ront end the system is directly compatible with digital systems and practically all o the design, besides the output transistors and the output ilter, can be integrated with the rest o the digital electronics. The drawbacks are that the switching process gives rise to distortion and noise. It is also a problem that since we use the ull voltage swing o the output transistors any noise on the voltage rom the power supply will directly inluence the quality o the output signal. Page 2