Dual Active Bridge Converter

Dual Active Bridge Converter Amit Jain Peregrine Power LLC now with Intel Corporation

Lecture : Operating Principles Sinusoidal Voltages Bi-directional transfer Lagging current V o V 0 P VV sin L jl 0 0 V V High Frequency Square wave (phase-shifted fundamentals) V o V 0 V V Implementation with H-Bridges Lagging current results in ZVS for all switches P m P base V dc S i L S S s 3 S 3s v p L S S 4 N S p : N s s S 4s HB HB v s V dc

P o,min [pu] 0 5 Lecture : Design 0 0.75 0.8 0.85 0.9 0.95.05..5..5 Key parameter is inductance Application based trade-off ZVS range (sw loss) Inductor size Currents (conduction loss) Capacitance size Transformer size Magnetizing inductance for increasing ZVS range decreases with L increases with L increases with L increases with L increases with L Integrated magnetics realization v p Φ p Φ L Φ s v s ZVS Boundary Variation with L, Po = 0kW V dc = V dc,nom controlled to obtain Po.8 0 40 Inductance [ H].6 i p,peak [A] 60 8 i p,rms 80 [A].4 i 00 s,rms [A] 0. 6 Increasing L 4 0.8 40 50 60 70 80 90 00 0 0 Variation with L, Po = 0kW V 0.6 dc = V dc,nom controlled to obtain Po 60 0 0.4 i p,peak Q [A] c [ C] 40 8 i 0. p,rms [A] i s,rms [A] 0 0 6 0.75 0.8 0.85 0.9 0.95.05..5..5 Vdc [pu] 4 0 40 50 60 70 80 90 00 0 0 60 4 Variation Minimum Qwith c [ C] L, CPo = 0kW V dc = V dc,nom controlled to obtain Po reqd [ F] 40 0 3 i p,peak [A] 8 i p,rms [A] 0 i s,rms [A] 6 0 40 50 60 70 80 90 00 0 0 4 4 40 50 60 70 80 90 00 0 0 IMinimum co,rms [A] C reqd [ F] 0 60 3 Q c [ C] 8 40 6 0 4 40 50 60 70 80 90 00 0 0 L [ H] 0 40 50 60 70 80 90 00 0 0 I co,rms [A] 0 3 4

Efficiency [%] Loss [W] Example Prototype: 5kW DC-DC Bi-directional HF Transformer HB Ch: v p (500V/div); Ch: v s (400V/div) Ch3: i p (50A/div) ; Ch4: i s (5A/div) 99 600 98 400 00 HB 97 SiC 000 96 Si IGBT 800 Ctrl Board 95 94 93 0 5 0 5 0 5 Po [kw] 600 400 00 0 4

Lecture 3: Advanced Topics PWM Control: Quasi-square wave operation ZVS to no load; lower rms currents & core loss jl V V V dc p cos 0 V dc cos s f Multiport DAB HB 3-port Transformer HB3 HB P V V V V L VV sin( ) L L L 3 3 V 3 V3 3 H- & Half-Bridge Combination S S 4 S s L S s C V V dc dc S S 3 Full Bridge C Half-Bridge 5

Dual Active Bridge Converter Amit Jain Peregrine Power LLC now with Intel Corporation

Outline Operating Principles Converter Design Advanced Topics: PWM Control, H-Bridge & Half-bridge combination, and Multi-Port DAB 7

Operating Principles 8

Motivations DCDC converter with Soft-switching without auxiliary components Bi-directional power flow Galvanic isolation and/or high conversion ratio 9

Soft Switching in Bridge Converters Bridge output current lags the bridge output voltage Lagging current discharges parasitic capacitance prior to switch turn on ZVS turn-on Lossless snubber capacitors across switches to which current transfers during turn-off ZVS turn-off 0

Power Flow Between Two AC Buses V o V 0 jl V V P VV sin L 0 0 Power flow magnitude and direction controlled by phase angle difference Current is lagging

Topology From AC Power Flow Sinusoidal voltages V o V 0 jl V V High Frequency Square wave (phase-shifted fundamentals) V o V 0 V V Implementation with Bridges V dc S S i S L S s 3 S 3s v p L S 4 N S p : N s s S 4s v s V dc HB HB

V dc S S S 3 S 4 v p i L HB L N p : N s v s S s S s HB Basic Operation S 3s S 4s V dc All switches operate with 50% duty ratio Diagonal switches in each H-bridge turn-on & turn-off together so that output of each bridge is a square wave Bridge outputs are phase shifted Difference of the bridge output voltages appears across the inductor L and determines the instantaneous current i L v p v s S S4 i L Ss S4s i L0 S S3 Ss S3s t t 3

Soft Switching V dc i L S S S 4 S i L 3 v p L N p : N s v s S s S s HB HB v p v s i L0.0KV S 3s S 4s V0V dc t -.0KV.0V 0.5V >> 0V 0A v DS,S v GS,S v GS,S VdsS7 v(g) v(g_bar) i DS,S i D i L i L t 0A i C S S4 Ss S4s S S3 Ss S3s S S4 SEL>> -9A 99.0us 930.00us 93.00us 93.00us i(s8) i(d8) i(c0)-i(c9) i(l) ZVS of i(l) S Time Lagging current of both bridges discharges output capacitance of switches and intra-winding capacitance of transformer Zero Voltage Switching (ZVS) for all devices Lossless capacitive snubbers can be used to minimize turn-off loss 4

Current Expressions Current vertices can be derived assuming steady state il0 m m Ibase il m Ibase Vdc Ibase X s L X L f swl N p V m N V dc dc i L v p v s S S4 i L Ss S4s i L0 S S3 Ss S3s t t 5

P/(mPbase) X L f swl Power Transfer P Power Transfer V P m Pbase Pmax m Pbase at 4 Vdc Pbase X L A A / T Magnitude and direction controlled by phase angle ϕ Similar to power transfer considering only fundamental components of the square waves across inductance L 8 N N p s V dc V f dc sw dc sin 8 L sw m sin P i L base v p v s S S4 0.5 0 i L A Ss S4s i L0 A S S3 Ss S3s -0.5 Exact Fundamental Approx - -00-00 0 00 00 [deg] t t 6

Implementing L Obvious choice is to utilize leakage inductance of transformer. However, in a well designed transformer the leakage inductance is usually not large enough Realize inductance and transformer in one structure to save on losses and size/weight : Magnetic integration v p Φ p Φ L Φ s Note: the type of integrated structure chosen impacts performance v s 7

Summary: Key Features of DAB Active H-bridges: Bi-directional, symmetrical structure No inductive filtering Power transfer controlled by phase shift between bridges (similar to two ac buses) Zero voltage switching (ZVS) Single cycle response in power transfer 8

Converter Design 9

Design Considerations Transformer turns ratio: To maximize ZVS range at nominal conditions choose N N Switching frequency considerations Power/voltage level determine switch type (IGBT/MOSFETs) & Magnetic material. Trade-off is primarily between heat sink and transformer size/weight with the given thermal solution and efficiency target. Switching loss at light load Control bandwidth and implementation Inductance value is the most important design parameter Magnetizing inductance Capacitor size p s V V dc, nom dc, nom 0

Design Equations Max Power Transfer V V dc dc Pmax 4 X L N N p s RMS Currents I I I P, RMS S, RMS i L0 N N p HBswitches, RMS s i I L i P, RMS I i L0 L P, RMS ( ) 3 Transformer magnetizing Volt-Sec Capacitor charge and ripple current

Soft Switching Range If m, below some power level either HB or HB has leading output current & therefore hard switching. Conditions for lagging current in the two bridges are: il0 m m Ibase 0 HB m HB i L m m I base 0 i L.5 v p v s S S4 i L Ss S4s i L0 S S3 ZVS Boundary Ss S3s t t In practice, the total capacitance at the switching node has to be discharged by il0 or il in a maximum allowable dead time []. See Appendix for equations. For low loads, the dead time could be varied in accordance with the current as done in the phase shift modulated full bridge converter. P/P base [pu] 0.5 HB and HB Soft Switching HB Hard SW HB Hard SW 0 0.5.5 m

Inductance Value Considerations The most important design parameter. Lower inductance value leads to higher power transfer capability and therefore smaller range of the phase shift for a given max power. Maximum inductance value that will allow the required maximum power transfer is given by Vdc V dc,min ' Lmax max max f swpo max Minimum value of inductance can be calculated using the minimum phase shift, a specified minimum load, and a specified maximum output voltage. Vdc V dc,max ' Lmin min min f P sw o min Lower inductance reduces size and allows integration with the transformer. Lower inductance leads to smaller capacitance requirement, lower rms capacitor current, and lower rms currents in the transformer and the switches. Higher inductance enables ZVS range to a lower power level Higher inductance increases Vdc/Vdc range for ZVS operation Starting point for optimization: X L = 0.5 0.5 p.u. 3

[A] [kw] [A] P o,min [pu] [A] [kw] [A] Inductance Value Optimization 5 0 5 0.4. 0.8 0.6 0.4 0. min [deg] A numerical trade off is required between the following: [deg] min 40 60 80 00 0 ZVS range (sw loss) Inductor size Currents (conduction loss) Capacitance size Transformer size Increasing L 0 0 0.75 0.8 0.85 0.9 0.95.05..5..5 8 Vdc [pu] 0 50 40 30 0 0 8 6 0 P -i(t o o ) i(t ) decreases with L increases with L increases with L increases with L increases with L 5 0 40 50 60 70 80 90 00 0 0 4 Variation with L, Po = 0kW V dc = V dc,nom controlled to obtain Po 40 50 60 70 80 90 00 0 0 0 0 50 -i(t 0.75 0.8 0.85 0.9 0.95.05..5..5 [deg] o ) 60 40 8 i(t ) Q c [ C] 40 30 6 0 ZVS Boundary 0.8 4 Inductance [ H] 040 50 60 70 80 90 00 0 00 40 50 60 70 80 90 00 0 0.6 40 50 60 70 80 90 00 0 0 0 440 50 60 70 80 90 00 0 0 40 50 60 70 80 90 00 0 0 40 50 60 70 80 90 00 0 0 4 0 I P FETavg I o FETrms 6 4 40 50 60 70 80 90 00 0 0 40 50 60 70 80 90 00 0 0 40 50 60 70 80 90 00 0 0 L [ H] L [ H] 4 I Example of L optimization for a FETrms 0kW 700V-700V DC-DC converter 0 Variation with L, Po = 0kW V dc = V dc,nom controlled to obtain Po [deg] I FETavg 0 8 6 4 3 0 8 6 Variation with L, Po = 0kW V dc = V dc,nom controlled to obtain Po i p,peak [A] i p,rms [A] i s,rms [A] Minimum C reqd [ F] I co,rms [A] 4

Magnetizing Inductance Leakage inductance is not sufficient to ensure soft-switching at light load. Increasing soft-switching range to lighter loads by increasing L increases rms currents. Typically L may be chosen to get soft-switching down to / /3 of the rated load. For lighter loads a finite magnetizing inductance is more effective for ensuring soft-switching. The magnetizing current is higher at small phase shifts (low loads) and lower at higher phase shifts (high loads) and therefore acts in complement with the leakage inductance to extend the ZVS range. [] Reducing magnetizing inductance Lm reduces the maximum power transfer capability of the converter. P o k P base 0.5 k ; This is not a real problem from a design point of view since the rated power is usually less than the maximum power transfer capability. A starting point for the magnetizing inductance is Lm=0xL. Equations including Lm are given in Appendix. k k L L m 5

Transformer and Capacitor Design Transformer design with magnetic integration: Compute worst case rms currents in the windings Compute worst case flux in each path of the magnetic structure Choose core areas starting with an assumption for the operating flux density (e.g., 0.5 Tesla for 3F3 type Ferrite, 0.5 Tesla for nano-crystalline) Compute total loss in windings and magnetic material, considering the flux in each part of the structure Check if loss meets target efficiency and thermal constraints Compute worst case capacitor ripple current for input and output from the inductor current waveforms assuming Lm is very large. Determine capacitance required to meet ripple specification. Simulate to verify efficiency and ripple at different load, input and output voltages 6

Averaged Dynamic Model i HB V dc S S 3 S S 4 HB L S s S s i HB S 3s S 4s HB C i load R V dc i i d v C dt HB load dc V X dc v R L dc ihb i load ~ i HB V X dc L ~ ref vdc _ G C (s) Current Gain i HB _ sc v dc i load R 7

Efficiency [%] Loss [W] 5kW DC-DC Bi-directional Converter Example DC-DC Converter Prototype HF Transformer HB Ch: v p (500V/div); Ch: v s (400V/div) Ch3: i p (50A/div) ; Ch4: i s (5A/div) 99 600 98 400 00 HB 97 SiC 000 96 Si IGBT 800 Ctrl Board 95 94 93 0 5 0 5 0 5 Po [kw] 600 400 00 0 8

Further DAB Topics 9

Extensions PWM Control [8]: If V dc, V dc, or both vary significantly ZVS load range is limited High RMS currents at low load Transformer core loss remains high at low loads Multi-port DAB 30

PWM Control of DAB: Operation HB PWM: m, 0 V dc S S S 3 S 4 v p i L HB L N p : N s v s S s S s HB S 3s S 4s V dc i L v p α p φ v s i L i L0 t i L v p φ α s vs i L i L0 t S S4 Ss S4s -i L t S S4 S4s Ss i L t PWM of bridge output Quasi square wave bridge output 50% duty ratio for each leg Phase shift between legs of the same H-bridge in addition to phase shift between bridge outputs 3

P [p.u.] PWM Control of DAB: Power Transfer 0.5 0.4 Regular DAB (=0) HB PWM( p = (-m) m = 0.5 0.3 Power Transfer: Depends on f and α Maximum P reduced control variable α feed forward variable/disturbance Can approximate by fundamental component 0. 0. 0 0 0 40 60 80 f [deg] jl V V V dc p cos 0 V dc s cos f 3

P [pu] ZVS conditions ( 0) HB leading leg (S, S) HB lagging leg (S3, S4) HB (SsS4s) PWM Control of DAB: ZVS Range HB PWM, m< HB PWM, m> m p f m p ( m) m ( m) p HB lagging leg (S3s, S4s) HB leading leg (Ss, Ss) HB (SS) s m s m m s m f Possible Scheme: Equate volt-seconds across primary and secondary of transformer.5 PWM Control Regular p =(- m) p =0 s = 0 s = (-/ m) 0.5 0 0.5.5 m 33

P [deg] I rms ( f =0) [A] RMS Currents Can optimize α for minimum rms currents with fundamental component approximation (minimize I,rms at constant P) jl P m 8 V V V dc p cos 0 V dc p cos sin f f Computed Results for : V dc 8 6 4 0 50 00 600V, fsw 40kHz, L00H, N ps RMS Current at No Load ( m) p p,min ( m) p p,min p,mini p,opt p,mini p,mini3 50 0 0.5 0.6 0.7 0.8 0.9 m 34

Transformer Size Transformer Size: k [max(volt-sec-product)] x I rms Without PWM ( p 0) p With PWM 0; s ( / m) for m Vdc ( mmax ) Vdc [ VOLT SEC ] p : fsw fsw s For 0.5: variation in m, core area requirement is reduced by 33%. 35

i L S S4 Mode IA: ( ) f p s ; v p α p i i a d α s i b i c S4s Ss p v s s t t Simultaneous Dual PWM Mode IB: p s f ; i L S α p Ss v p α s S4 v s i c =i d i b =i a p S4s v p s Five possible operating modes depending on angles ( p, s, f ) Only Mode III & IV are useful during low load operation. Power transfer can be approximated by the fundamental component v s t t P m Mode II: i L S Ss s p s p s p min f, α p α s v p S4s S4 v s i d i c i b =i a t t 36

Mode IV Operation Current vertices α s v p v s t i L α p i b =i c i d For low load operation -i a t i d ensures: ZVS (lagging current) down to zero load Minimum rms currents Minimum core loss i L S Ss i b =i c -i a S4 S4s 37 t

Composite Scheme Transition from Dual PWM to Single HB PWM and finally to only phase shift control 38

Low Load Efficiency with PWM Control 0kW DAB with Vdc=600V; Vdc=300V (left), 450V (right) 39

Three Port DAB [4] HB 3-port Transformer HB V V V V L HB3 L L 3 3 P VV sin( ) L V 3 V3 3 Choose phase shifts to enable required power transfer while minimizing circulating power 40

Half and Full Bridge Combination S S 3 S s L C V dc V dc S S 4 S s C Full Bridge Half-Bridge Similar to load resonant converters Reduced switch count at expense of capacitors Secondary side cannot produce quasi-square wave 4

References [] R.W. A. A. De Doncker, D. M. Divan, and M. H. Kheraluwala, A threephase soft-switched high-power-density dc/dc converter for high-power applications, IEEE Trans. Ind. Appl., vol. 7, no., pp. 6373, Jan./Feb. 99. [] M. H. Kheraluwala, R. W. Gascoigne, D. M. Divan, and E. D. Baumann, Performance characterization of a high-power dual active bridge dc-to dc converter, IEEE Trans. Ind. Appl., vol. 8, no. 6, pp. 9430,Nov./Dec. 99. [3] R. Steigerwald, R. De Doncker, and M. H. Kheraluwala, A comparison of high power dc to dc soft switched converter topologies, IEEE Trans. Ind. Appl., vol. 3, no. 6, pp. 3945, Sep./Oct. 996. [4] C. Zhao and J. W. Kolar, A novel three-phase three-port ups employing a single highfrequency isolation transformer, in Proc. 35th IEEE Power Electron. Spec. Conf. (PESC004), Aachen, Germany, Jun. 004, vol. 6, pp. 43544. [5] F. Krismer, S. Round, and J. Kolar, Performance optimization of a high current dual active bridge with a wide operating voltage range, in Proc. 37th IEEE Power Electron. Spec. Conf. (PESC006), Jeju, Korea, Jun., pp. 7. [6] D. Aggeler, J. Biela, and J. Kolar, A compact, high voltage 5 kw, 50 khz dc-dc converter based on sic jfets, in Proc. 3rd IEEE Appl. Power Electron. Conf. Expo. (APEC008), Dallas, TX, Feb., pp. 80807. [7] F. Krismer and J. Kolar, Accurate small-signal model for the digital control of an automotive bidirectional dual active bridge, IEEE Trans. Power Electron., vol. 4, no., pp. 756 768, Dec. 009. [8] A.K. Jain and R. Ayyanar, PWM Control of Dual Active Bridge: Comprehensive Analysis and Experimental Verification, IEEE Trans. Power Electron., vol. 6, no. 4, pp. 5-7, April 0. [9] A.K. Jain, D. McIntosh, M. Jones, B. Ratliff, Performance of a 5kW 700V Galvanically Isolated Bidirectional DC-DC Converter Using.kV Silicon Carbide MOSFETs and Schottky Diodes, 0 International Conference on Silicon Carbide and Related Materials (ICSCRM 0), September 6, 0. 4

Appendix 43

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45

Effect of Snubber and Transformer Capacitance 46

Effect of Snubber and Transformer Capacitance i L0 m m I base 0 47