Experiences and Benefits of 16nm and 10nm FinFET Development Jeff Galloway, Paweł Banachowicz, Michael Kroger, Brian Eplett, Andrew Cole, Randy Caplan
Silicon Creations Process Experience Silicon Creations has experience designing in 350nm to 10nm. Relentless process scaling has created challenges and opportunities. This presentation will highlight some of our experiences with FE and BE design from 350nm to 10nm. 2
Products [1] SerDes Proven from 28nm to 180nm and from <100Mbps to 20Gbps Ring Oscillator Based PLLs allow a broad frequency range with random jitter well under 1ps RMS Standards including 10GKR, SATA, PCIe, Display Port, SGMII, XAUI, SATA, V-by-1 HS, FastLVDS, CameraLink, FPDLink, RapidIO, OIF-CEI, JESD204 and semi-custom links SERDES size and power vary with process, application, metal stack, etc. 355fs RMS jitter 3
Products [2] Ring PLLs Used in a huge variety of applications, from mobile AP to networking to consumer display to industrial to automotive. Most SoCs have many, many PLLs! Silicon Creations PLLs in mass production in ~100 chips from 16n to 180n, TO at 10nm In production at the ~1 Billion PLL / year rate Extremely wide frequency range Programmable power-jitter Supplemental RTL IP for Precise SSCG Jitter Cleaner PLLs using same core for Low area Very low jitter High speed Since this IP is so widely used, it will be used for the remainder of the talk to compare process nodes. 4
Transistor Performance (1) Peak ft (transition frequency) is a measure of the analog frequency performance of a transistor. The peak ft continues to rise with scaling. 10nm FinFET has a peak ft in excess of 500GHz! The 28nm node shows a fork in process technology, with the high-k/metal-gate processes showing best ft performance. Some reasons for the process fork at 28nm will be explained a bit later. 5
Transistor Performance (2) The fanout-of-4 delay of an inverter is a measure of the digital speed of a process. The typical FO4 delay in the most advanced processes is <10ps! This enables digital circuits at many, many GHz. The FO4 delay had decreased in every process node until 40nm. However, at 28nm, there is a fork. It seems that 28nm HKMG may be a faster process than the following non-bulk processes, but it comes with tradeoffs. 6
Transistor Performance (3) Just as important as a transistor turning on, is turning off! Typical on/off ratios are >1,000,000:1 for bulk poly-si gate processes. HKMG offers better drive in 28nm, but a worse on/off current ratio. Non-bulk devices offer a way out high drive current and a good on/off current ratio. Change to FinFET 7
Analog Scaling There is some debate over whether analog scales. The plot on the right shows the area for Silicon Creations PLLs with similar frequency & jitter specs from 180nm to 10nm. The size can be seen to decrease 10x, leading to lower cost. Holding noise constant (kt/c), the area should scale with cap area and does! Gate capacitance was scaling through 65nm, metal-metal capacitance is dominant below 40nm and still scaling well. So, analog functions scale, but not as well as digital circuit Digital scaling from 180nm to 10nm is ~300:1 Analog scaling from 180nm to 10nm is ~10:1 8
Process Complexity (1) A simple measure of process complexity is the number of GDSII layers in PLL IP. (The PLLs compared use only up to layer M4.) The number of layers has increased 5x since 180nm, indicating an increase in complexity. But, does the 5x increase reflect process complexity? 9
Process Complexity (2) In the past decade +, process technology has gotten increasingly complex. Another simple (and not very accurate!!!) measure of process complexity is the Design Rule Manual thickness From.35mm to FinFET, the the DRM thickness has increased over an order of magnitude. Does the ~15x increase in DRM thickness indicate the process complexity? 10nm will grow before maturity! 10
Process Complexity (3) From 180nm to 65nm, DRC run times and process complexity were increasing modestly for IP blocks. The 40nm and 28nm nodes saw a large increase in the number of checks and the complexity of the checks and hence DRC run time. FinFET design is a whole order of magnitude more complex: Tighter more complex rules More fill geometries More layers (GDSII layers, derived layers, marker layers, etc) FinFET run times are ~10x the 28nm run times, and ~50x the 65nm run times. Quite complex! Quite expensive! Note: Many very nice EDA optimizations (multi-core, multi-machine, optimized code) have kept the DRC run times to 100x it could be worse! 11
Layout challenges by geometry 40nm Shrunk traditional layout Some exacting space rules and dummy structures Tight fill requirements, density requirements 28nm Gate orientation restrictions Extended dummy structures More exacting space rules Tighter fill requirements, density requirements 16nm Fins on grids! Unit devices Some multi-patterning Limited metal directionality Many more layers! M0, cut layers, etc. 10nm Colored poly, M1, M2, Limited metal directionality, more local (M0) metals More multi-patterning, colored lower metals Extremely exacting pitch/space requirements Extremely tight fill requirements Custom design is very difficult!!! Silicon Creations has developed custom, foundry independent PDKs that enable quick and reliable porting from process to process. Silicon Creations has developed it s own design flows for FinFET BE design. 12
FE design challenges in FinFET Schematics still look like schematics. At a high level, not that much has changed. Yes, analog still lives in 10nm! Statistical variability is increasing as devices shrink Drives circuit topologies more and more Schematic simulation of high speed blocks deviating from reality Parasitics, especially R, mandates much more postlayout verification and work. From 28nm PLL W becomes nfin From 10nm PLL L replaced with stacked fins Many dummies added! 13
Interconnect Challenges (1) Interconnect resistance is climbing quickly! From 40nm to 10nm, the relative wire resistance (Ohms/sq) has risen more than 6 fold. The impact of resistance is leading to multiple challenges: Designs are becoming limited by wire performance Designs are increasingly difficult to verify due to the need for simulation of distributed RC parasitics 14
Interconnect Challenges (2) In advanced processes, the interconnect resistance must be taken into account. The simulation time from a schematic simulation to a cap extracted sim is 2-3x. The simulation time from caponly to RC is another order of magnitude. This simulation time translates to: Longer development cycles Need for more simulation licenses Need for parallel simulation licenses Higher development costs! Simulation of interconnect + devices is expensive! 15
Summary Transistor, gate performance continues to improve 10nm offers record ft with high on/off current ratios. The switch to non-bulk devices such as FinFET provides a boost to performance while keeping leakage low. The added density and dimensionality does pose challenges to verification, as RC simulation is required Density keeps increasing Metal spacing, transistor size, etc. keep shrinking. The gains in density do come with challenges in design and verification. 16