UCXA UC3XA HIGH PEFOMANCE CUENT MODE PWM CONTOLLE FEATUES TIMMED OSCILLATO DISCHAGE CUENT CUENT MODE OPEATION TO 00kHz AUTOMATIC FEED FOWAD COMPENSATION LATCHING PWM FO CYCLEBYCYCLE CUENT LIMITING INTENALLY TIMMED EFEENCE WITH UNDEVOLTAGE LOCKOUT HIGH CUENT TOTEM POLE OUTPUT UNDEVOLTAGE LOCKOUT WITH HYSTEESIS LOW STATUP CUENT (< 0.mA) DOUBLE PULSE SUPPESSION DESCIPTION The UC3xA family of control ICs provides the necessary features to implement offline or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTOL under voltage lockout featuring startup current less than 0.mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving NChannel MOS FETs, is low in the offstate. Figure. Package DIP Table. Order Codes Part Number UCAD; UC3AD; UC3AD; UC33AD; UCAD; UC3AD; UCAD; UC3AD UCAN; UC3AN; UC3AN; UC33AN; UCAN; UC3AN; UCAN; UC3AN NOT FO NEW DESIGN Differences between members of this family are the undervoltage lockout thresholds and maximum duty cycle ranges. The UC3A and UC3A have UVLO thresholds of 6V (on) and 0V (off), ideally suited offline applications The corresponding thresholds for the UC33A and UC3A are. V and.9v. The UC3A and UC33A can operate to duty cycles approaching 00%. A range of the zero to < 0 % is obtained by the UC3A and UC3A by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. Figure. Block Diagram (toggle flip flop used only in UC3A and UC3A) SO Package SO DIP Vi GOUND 3V UVLO S/ V EF VEF V 0mA.0V INTENAL BIAS T/CT OSC VEF GOOD LOGIC T 6 OUTPUT VFB COMP CUENT SENSE 3 EO AMP. S PWM V LATCH CUENT SENSE COMPAATO D9IN33 May 00 EV. /6
UC3XA UCXA Table. Absolute Maximum atings Symbol Parameter Value Unit V i Supply Voltage (low impedance source) 30 V V i Supply Voltage (Ii < 30mA) Self Limiting I O Output Current ± A E O Output Energy (capacitive load) µj Analog Inputs (pins, 3) 0.3 to. V Error Amplifier Output Sink Current 0 ma P tot Power Dissipation at T amb C (DIP). W P tot Power Dissipation at T amb C (SO) 00 mw T stg Storage Temperature ange 6 to 0 C T J Junction Operating Temperature 0 to 0 C T L Lead Temperature (soldering 0s) 300 C * All voltages are with respect to pin, all currents are positive into the specified terminal. Figure 3. DIP/SO Pin Connection (Top view) COMP V EF V FB Vi I SENSE 3 6 OUTPUT T /C T GOUND D9IN33 Table 3. Pin Description N Pin Function COMP This pin is the Error Amplifier output and is made available for loop compensation. V FB This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. 3 I SENSE A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. T /C T The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor T to V ref and cpacitor C T to ground. Operation to 00kHz is possible. GOUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to A are sourced and sunk by this pin. V CC This pin is the positive supply of the control IC. V ref This is the reference output. It provides charging current for capacitor C T through resistor T. /6
UC3XA UCXA Table. Thermal Data Symbol Parameter DIP SO Unit th jamb Thermal esistance Junctionambient Max. 00 0 C/W Table. Electrical Characteristcs ( [note ] Unless otherwise stated, these specifications apply for < T amb < C for UCXA; 0 < T amb < 0 C for UC3XA; V i = V (note ); T = 0K; C T = 3.3nF) Symbol Parameter Test Condition UCXA UC3XA Min. Typ. Max. Min. Typ. Max. Unit EFEENCE SECTION V EF Output Voltage T j = C I o = ma.9.00.0.90.00.0 V V EF Line egulation V V i V 0 0 mv V EF Load egulation I o 0mA 3 3 mv V EF / T Temperature Stability (Note ) 0. 0. mv/ C Total Output Variation Line, Load, Temperature.9... V e N Output Noise Voltage 0Hz f 0KHz T j = C (note ) 0 0 µv Long Term Stability T amb = C, 000Hrs (note ) mv ISC Output Short Circuit 30 00 0 30 00 0 ma OSCILLATO SECTION f OSC Frequency T j = C KHz f OSC / V Frequency Change with Volt. V CC = V to V 0. 0. % V EF / T Frequency Change with Temp. T A = T low to T high % V OSC Oscillator Voltage Swing (peak to peak).6.6 V I dischg Discharge Current (V OSC =V) T J = C..3...3. ma EO AMP SECTION V Input Voltage V PIN =.V..0...0. V I b Input Bias Current V FB = V 0. 0. µa A VOL V V o V 6 90 6 90 db BW Unity Gain Bandwidth T J = C 0. 0. MHz PS Power Supply ejec. atio V V i V 60 0 60 0 db I o Output Sink Current V PIN =.V ma V PIN =.V I o Output Source Current V PIN =.3V V PIN = V 0. 0. ma V OUT High V PIN =.3V; L = KΩ to 6. 6. V Ground V OUT Low V PIN =.V; L = KΩ to Pin 0.. 0.. V CUENT SENSE SECTION G V Gain (note 3 & ). 3 3.. 3 3. V/V V 3 Maximum Input Signal V PIN = V (note 3) 0.9. 0.9. V SV Supply Voltage ejection V i V (note 3) 0 0 db I b Input Bias Current 0 0 µa Delay to Output 0 300 0 300 ns 3/6
UC3XA UCXA Table. Electrical Characteristcs (continued) ( [note ] Unless otherwise stated, these specifications apply for < T amb < C for UCXA; 0 < T amb < 0 C for UC3XA; V i = V (note ); T = 0K; C T = 3.3nF) Symbol Parameter Test Condition UCXA UC3XA Min. Typ. Max. Min. Typ. Max. Unit OUTPUT SECTION V OL Output Low Level I SINK = 0mA 0. 0. 0. 0. V I SINK = 00mA.6..6. V V OH Output High Level I SOUCE = 0mA 3 3. 3 3. V I SOUCE = 00mA 3. 3. V V OLS UVLO Saturation V CC = 6V; I 0.. 0.. V SINK = ma t r ise Time T j = C C L = nf () 0 0 0 0 ns t f Fall Time T j = C C L = nf () 0 0 0 0 ns UNDEVOLTAGE LOCKOUT SECTION Start Threshold XA/A 6. 6. V X3A/A.. 9.0.. 9.0 V Min Operating Voltage XA/A 9 0. 0. V After Turnon PWM SECTION Maximum Duty Cycle XA/3A 9 96 00 9 96 00 % XA/A 0 0 % Minimum Duty Cycle 0 0 % TOTAL STANDBY CUENT I st Startup Current V i = 6.V for UCX3A/ 0.3 0. 0.3 0. ma A V i = V for UCXA/A 0.3 0. 0.3 0. ma I i Operating Supply Current V PIN = V PIN3 = 0V ma V iz Zener Voltage I i = ma 30 36 30 36 V Notes:. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain T j as close to T amb as possible.. These parameters, although guaranteed, are not 00% tested in production. 3. Parameter measured at trip point of latch with V PIN = 0.. Gain defined as : A = V PIN / V PIN3 ; 0 V PIN3 0.V. Adjust V i above the start threshold before setting at V. /6
.nf UC3XA UCXA Figure. Open Loop Test Circuit..KΩ T V EF EO AMP. ADJUST.KΩ N 00KΩ KΩ I SENSE ADJUST KΩ COMP V FB I SENSE T /C T V EF 3 6 0.µF V i OUTPUT GOUND 0.µF A W KΩ V i OUTPUT D9IN33 C T GOUND High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin in a single point ground. The transistor and KΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure. Oscillator Frequency vs Timing esistance Figure. Oscillator Discharge Current vs. Temperature. f o (Hz) M D96IN36 I dischg (ma). V i =V V OSC =V D9IN33 CT=0pF 00K.nF nf.0 0K. K 300 K 3K 0K 30K T(Ω) Figure 6. Maximum Duty Cycle vs Timing esistor.0 0 0 00 T A ( C) Figure. Error Amp OpenLoop Gain and Phase vs. Frequency. f o (Hz) 0 D96IN363 (db) 0 60 Gain D9IN33 V i =V V O =V to V L =00K T A = C φ 30 60 60 0 0 0 Phase 90 0 0 0 0 0 300 K 3K 0K 30K T(Ω) 0 0 0 00 K 0K 00K M f(hz) /6
UC3XA UCXA Figure 9. Current Sense Input Threshold vs. Error Amp Output Voltage. Figure. Output Saturation Voltage vs. Load Current. V th (V).0 0. 0.6 V i =V T A = C T A = C D9IN33 V sat (V) 3 V i Source Saturation (Load to Ground) T A = C V i =V 0µs Pulsed Load 0Hz ate D9IN3 T A =0 C 0. 0. T A =0 C 0.0 0 6 V O (V) 0 T A =0 C Sink Saturation (Load to V i ) T A = C GND 0 00 00 600 I O (ma) Figure 0. eference Voltage Change vs. Source Current.. Figure 3. Supply Current vs. Supply Voltage. 60 V i =V D9IN339 I i (ma) D9IN3 0 0 0 T A =0 C 30 T A = C 0 0 TA= C 0 UCX3/ UCX/ T =0K C T =3.3nF V FB =0V I Sense =0V T A = C 0 0 0 0 60 0 00 I ref (ma) 0 0 0 0 30 V i (V) Figure. eference Short Circuit Current vs. Temperature.. I SC (ma) 00 V i =V L 0.Ω D9IN30 90 0 0 60 0 0 0 00 T A ( C) 6/6
UC3XA UCXA Figure. Output Waveform. Figure. Output Cross Conduction Figure 6. Oscillator and Output Waveforms. V i CT V EG T PWM 6 OUTPUT OUTPUT LAGE T /SMALL C T CLOCK OSCILLATO I D CT C T OUTPUT GND SMALL T /LAGE C T D9IN3 Figure. Error Amp Configuration..V ma Z i V FB COMP Z f D9IN3 /6
UC3XA UCXA Figure. Under Voltage Lockout. V i ON/OFF COMMAND TO EST OF IC I CC UC3A UC3A UC33A UC3A <ma V ON V OFF 6V.V 0V.6V <0.mA V OFF V ON V CC D9IN36mod Figure 9. Current Sense Circuit. EO AMPL. I S COMP 3 V CUENT SENSE COMPAATO S C CUENT SENSE GND D9IN3 Peak current (i s ) is determined by the formula.0v I Smax S A small C filter may be required to suppress switch transients. Figure 0. Slope Compensation Techniques. V EG V EG T T T /C T I S T /C T I S SLOPE CT SLOPE C T S I SENSE 3 GND S I SENSE 3 GND D9IN3 /6
UC3XA UCXA Figure. Isolated MOSFET Drive and Current Transformer Sensing. V CC V in.0v ref ISOLATION BOUNDAY V GS Waveforms 6 Q 0 0 0% DC % DC S Q I pk = V (pin ). 3 S ( ) N S N P COMP/LATCH 3 C S N S N P D9IN39 Figure. Latched Shutdown. OSC BIAS ma EA N 390 N 3903 D9IN30 SC must be selected for a holding current of less than 0.mA at T A(min). The simple two transistor circuit can be used in place of the SC as shown. All resistors are 0K. 9/6
UC3XA UCXA Figure 3. Error Amplifier Compensation From V O.V ma i d C f f EA Error Amp compensation circuit for stabilizing any currentmode topology except for boost and flyback converters operating with continuous inductor current. From V O.V ma P C P i d C f f EA D9IN3 Error Amp compensation circuit for stabilizing currentmode boost and flyback topologies operating with continuous inductor current. Figure. External Clock Synchronization. V EF BIAS T OSC C T EXTENAL SYNC INPUT 0.0µF Ω EA The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of C T to go more than 300mV below ground D9IN3 0/6
UC3XA UCXA Figure. External Duty Cycle Clamp and Multi Unit Synchronization. V EF A B K BIAS 6 3 OSC K Q C K S NE EA. f = ( A B )C D max = B A B TO ADDITIONAL UCXXAs D9IN33 Figure 6. SoftStart Circuit V ref BIAS OSC MΩ EA ma V S Q C D9IN3 /6
UC3XA UCXA Figure. SoftStart and Error Amplifier Output Duty Cycle Clamp. V ref V CC V in BIAS OSC 6 Q EA ma V Clamp V S Q Comp/Latch C BC09 S V CLAMP = where 0 <V CLAMP <V I pk(max) = V CLAMP S D9IN3 /6
UC3XA UCXA Figure. SO Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A.3. 0.03 0.069 OUTLINE AND MECHANICAL DATA A 0.0 0. 0.00 0.00 A.0.6 0.03 0.06 B 0.33 0. 0.03 0.00 C 0.9 0. 0.00 0.00 D ().0.00 0.9 0.9 E 3.0.00 0. 0. e. 0.00 H.0 6.0 0. 0. h 0. 0.0 0.00 0.00 L 0.0. 0.06 0.00 k 0 (min.), (max.) ddd 0.0 0.00 Note: () Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.mm (.006inch) in total (both side). SO 00603 C 3/6
UC3XA UCXA Figure 9. DIP Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 3.3 0.3 OUTLINE AND MECHANICAL DATA a 0. 0.00 B..6 0.0 0.06 b 0.36 0. 0.0 0.0 b 0.0 0.30 0.00 0.0 D 0.9 0.30 E.9 9. 0.33 0.3 e. 0.00 e3.6 0.300 e.6 0.300 F 6.6 0.60 I.0 0.00 L 3. 3. 0. 0.0 Z. 0.060 DIP /6
UC3XA UCXA Table 6. evision History Date evision Description of Changes March 999 First Issue in EDOCS May 00 NOT FO NEW DESIGN /6
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