Lecture 390 Oversampling ADCs Part I (3/29/0) Page 390 LECTURE 390 OVERSAMPLING ADCS PART I LECTURE ORGANIZATION Outline Introduction Deltasigma modulators Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 698705 Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3902 INTRODUCTION What is an oversampling converter? An oversampling converter uses a noiseshaping modulator to reduce the inband quantization noise to achieve a high degree of resolution. What is the range of oversampling? The oversampling ratio, called M, is a ratio of the clock frequency to the Nyquist frequency of the input signal. This oversampling ratio can vary from 8 to 256. The resolution of the oversampled converter is proportional to the oversampled ratio. The bandwidth of the input signal is inversely proportional to the oversampled ratio. What are the advantages of oversampling converters? Very compatible with VLSI technology because most of the converter is digital High resolution Singlebit quantizers use a onebit DAC which has no INL or DNL errors Provide an excellent means of trading precision for speed (68 bits at 50ksps to 80 bits at sampling rates of 50Msps). What are the disadvantages of oversampling converters? Difficult to model and simulate Limited in bandwidth to the clock frequency divided by the oversampling ratio
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3903 Nyquist Versus Oversampled ADCs Conventional Nyquist ADC Block Diagram: x(t) Digital Processor y(kt N ) Filtering Sampling Quantization Digital Coding Fig.0.90 Oversampled ADC Block Diagram: x(t) Modulator Decimation Filter y(kt N ) Filtering Sampling Quantization Digital Coding Fig.0.902 Components: Filter Prevents possible aliasing of the following sampling step. Sampling Necessary for any analogtodigital conversion. Quantization Decides the nearest analog voltage to the sampled voltage (determines the resolution). Digital Coding Converts the quantizer information into a digital output signal. Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3904 Frequency Spectrum of Nyquist and Oversampled Converters Definitions: f B = analog signal bandwidth f N = Nyquist frequency (two times f B ) f S = sampling or clock frequency M = f S f N = f S 2f B = oversampling ratio Frequency prespective: Conventional ADC with f B 0.5f N =0.5f S. Transition band Amplitude Signal Bandwidth ;;; 0 0 f B Antialiasing filter 0.5f N = 0.5f S f S =f N f Oversampled ADC with f B 0.5f N <<f S. Amplitude ; Signal Bandwidth Antialiasing filter Transition band 0 f 0 f B = f N 0.5f S f S =Mf N 0.5f N Fig.0.903
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3905 Quantization Noise of a Conventional (Nyquist) ADC Multilevel Quantizer: Output, y 5 Δ 3 Ideal curve 6 4 2 Input, x 2 4 6 3 The quantized signal y can be represented as, y = Gx e Δ where G = gain of the ADC, normally e = quantization error The mean square value of the quantization error is erms 2 = S Q = /2 e(x) 2 dx = 2 2 /2 5 Quantization error, e Input, x Fig.0.904 Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3906 Quantization Noise of a Conventional (Nyquist) ADC Continued Spectral density of the sampled noise: When a quantized signal is sampled at f S (= /), then all of its noise power folds into the frequency band from 0 to 0.5f S. Assuming that the noise power is white, the spectral density of the sampled noise is, 2 E(f) = e rms f = e rms 2 S where = /f S and f S = sampling frequency The inband noise energy no is f B n o 2 = E 2 (f)df = erms 2 (2f B ) = e 2 rms 2f B erms 2 fs = M 0 n e rms o = M What does all this mean? One way to increase the resolution of an ADC is to make the bandwidth of the signal, f B, less than the clock frequency, f S. In otherwords, give up bandwidth for precision. However, it is seen from the above that a doubling of the oversampling ratio M, only gives a decrease of the inband noise, n o, of / 2 which corresponds to 3dB decrease or an increase of resolution of 0.5 bits As a result, increasing the oversampling ratio of a Nyquist analogdigital converter is not a very good method of increasing the resolution.
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3907 Oversampled AnalogDigital Converters Classification of oversampled ADCs:.) Straightoversampling The quantization noise is assumed to be equally distributed over the entire frequency range of dc to 0.5f S. This type of converter is represented by the Nyquist ADC. 2.) Predictive oversampling Uses noise shaping plus oversampling to reduce the inband noise to a much greater extent than the straightoversampling ADC. Both the signal and noise quantization spectrums are shaped. 3.) Noiseshaping oversampling Similar to the predictive oversampling except that only the noise quantization spectrum is shaped while the signal spectrum is preserved. The noiseshaping oversampling ADCs are also known as deltasigma ADCs. We will only consider the deltasigma type oversampling ADCs. Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3908 DELTASIGMA MODULATORS General block diagram of an oversampled ADC f S fd <f S Analog Input x(t) f B ΔΣ Modulator (Analog) Decimator (Digital) Lowpass Filter (Digital) 2f B Digital PCM Fig.0.907 Components of the Oversampled ADC:.) Modulator Also called the noise shaper because it can shape the quantization noise and push the majority of the inband noise to higher frequencies. It modulates the analog input signal to a simple digital code, normally a onebit serial stream using a sampling rate much higher than the Nyquist rate. 2.) Decimator Also called the downsampler because it down samples the high frequency modulator output into a low frequency output and does some prefiltering on the quantization noise. 3.) Digital Lowpass Filter Used to remove the high frequency quantization noise and to preserve the input signal. Note: Only the modulator is analog, the rest of the circuitry is digital.
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3909 FirstOrder, DeltaSigma Modulator Block diagram of a firstorder, deltasigma modulator: Components: Integrator (continuous or discrete time) Coarse quantizer (typically two levels) A/D which is a comparator for two levels D/A which is a switch for two levels Firstorder modulator output for a sinusoidal input:.5 x u Fig.0.908 Integrator v f S A/D D/A Quantizer y 0.5 Volts 0 0.5.5 0 50 00 50 200 250 Tme (Units of T, clock period) Fig.0.909 Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3900 SampledData Model of a FirstOrder Modulator q[nt s ] Writing the following relationships, y[nt s ] = q[nt s ] v[nt s ] v[nt s ] = w[(n)t s ] v[(n)t s ] y[nt s ] = q[nt s ]w[(n)t s ]v[(n)t s ] = q[nt s ]{x[(n)t s ]y[(n)t s ]}v[(n)t s ] But the first equation can be written as y[(n)t s ] = q[(n)t s ] v[(n)t s ] q[(n)t s ] = y[(n)t s ]} v[(n)t s ] Substituting this relationship into the above gives, y[nt s ] = x[(n)t s ] q[nt s ] q[(n)t s ] Converting this expression to the zdomain gives, Y(z) = zx(z) (z)q(z) Definitions: Signal Transfer Function = STF = Y(z) X(x) = z Noise Transfer Function = NT F= Y(z) Q(x) = z x[nt s ] w[nt s ] Integrator Delay v[nt s ] Quantizer y[nt s ] Fig. 0.90
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 390 HigherOrder Modulators A secondorder, modulator: q[nt s ] x[nt s ] Integrator Delay Integrator 2 Delay Quantizer y[nt s ] 070970 It can be shown that the zdomain output is, Y(z) = zx(z) (z)2q(z) The general, Lth order modulator has the following form, Y(z) = zkx(z) (z)lq(z) Note that noise transfer function, NTF, has Lzeros at the origin resulting in a highpass transfer function. K depends on the architecture where KL. This highpass characteristic reduces the noise at low frequencies which is the key to extending the dynamic range within the bandwidth of the converter. Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3902 Noise Transfer Function The noise transfer function can be written as, NTF Q (z) = (z )L Evaluate (z ) by replacing z by ejt s to get (z )= ejts 2j e jf/fs 2j ejf/fs = ejf/fsejf/fs 2j 2j ejf/fs = sin(ft s ) 2j ejf/fs z = (2sinfT s ) NTF Q (f) = (2sinfT s )L Magnitude of the noise transfer function, Note: Singleloop modulators having noise shaping characteristics of the form (z )L are unstable for L>2 unless an Lbit quantizer is used. Magnitude of noise shaping function 0 8 6 4 L = 3 L = 2 L = 2 LPF ;; 0 0 f b f Frequency s /2 Fig.0.92
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3903 InBand Rms Noise of SingleLoop Modulator Assuming noise power is white, the power spectral density of the modulator, S E (f), is S E (f) = NTF Q (f) 2 S Q(f) f s Next, integrate S E (f) over the signal band to get the inband noise power using S Q = 2 2 f b S B = f s (2sinfT s )2L 2 2 df 2L 2L M2L 2 2 where sinft s ft s for M>>. f b Therefore, the inband, rms noise is given as n 0 = S B = L 2L ML0.5 2 = L 2L ML0.5 e rms Note that as the is a much more efficient way of achieving resolution by increasing M. e rms n 0 ML0.5 Doubling of M leads to a 2L0.5 decrease of inband noise resulting in an extra L0.5 bits of resolution! The increase of the oversampling ratio is an excellent method of increasing the resolution of a oversampling analogdigital converter. Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3904 Illustration of RMS Noise Versus Oversampling Ratio for Single Loop Modulators Plotting n 0 /e rms gives, n 0 e = rms L 2L ML0.5
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3905 Dynamic Range of AnalogDigital Converters Oversampled Converter: The dynamic range, DR, for a bitquantizer with level spacing =V REF, is DR 2 = Maximumsignalpower S B (f) = 2 2 2 2L 2L M2L 2 2 = 3 2 2L 2L M 2L Nyquist Converter: The dynamic range of a Nbit Nyquist rate ADC is (now becomes V REF for large N), DR 2 = Maximumsignalpower S Q = (V REF/2 2)2 2/2 = 3 2 2 2N DR =.5 2N Expressing DR in terms of db (DR db ) and solving for N, gives N = DR db.7609 6.0206 or DR db = (6.0206N.7609) db Example: A 6bit ADC requires about 98dB of dynamic range. For a secondorder modulator, M must be 53 or 256 since we must use powers of 2. Therefore, if the bandwidth is 20kHz, then the clock frequency must be 0.24MHz. Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3906 Multibit Quantizers A singlebit quantizer: = V REF Advantage is that the DAC is inherently linear. v u y v<0 v>0 Multibit quantizer: Consists of an ADC and DAC of Bbits. = V REF 2B Disadvantage is that the DAC is no longer perfectly linear. To get large V resolution deltasigma REF ADCs requires highly precise DACs. Dynamic range of a multibit ADC: DR2 = 3 2L 2 2L M 2L 2B 2 Δ Fig. 0.935 Fig. 0.93 v u V REF 2 f S A/D D/A Quantizer Fig. 0.94 V REF 2 y
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3907 Example 390 Tradeoff Between Signal Bandwidth and Accuracy of ADCs Find the minimum oversampling ratio, M, for a 6bit oversampled ADC which uses (a.) a bit quantizer and thirdorder loop, (b.) a 2bit quantizer and thirdorder loop, and (c.) a 3bit quantizer and secondorder loop. For each case, find the bandwidth of the ADC if the clock frequency is 0MHz. Solution We see that 6bit ADC corresponds to a dynamic range of approximately 98dB. (a.) Solving for M gives M = 2 3 DR 2 2L 2L (2 B ) 2 /(2L) Converting the dynamic range to 79,433 and substituting into the above equation gives a minimum oversampling ratio of M = 48.03 which would correspond to an oversampling rate of 64. Using the definition of M as f c /2f B gives f B as 0MHz/2 64 = 78kHz. (b.) and (c.) For part (b.) and (c.) we obtain a minimum oversampling rates of M = 32.53 and 96.48, respectively. These values correspond to oversampling rates of 32 and 28, respectively. The bandwidth of the converters is 32kHz for (b.) and 78kHz for (c.). Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3908 ZDomain Equivalent Circuits The modulator structures are much easier to analyze and interpret in the zdomain. q[nt s ] x[nt Integrator s ] w[nt s ] v[nt s ] Delay Quantizer Q(z) y[nt s ] X(z) W(z) Integrator z V(z) Quantizer Y(z) X(z) z z Fig.0.96 Y(z) = Q(z) z z [X(z) Y(z)] Y(z) z = Q(z) z z X(z) Y(z) = (z)q(z) zx(z) NTF Q (z) = (z) for L = Q(z) Y(z)
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3909 Cascaded, SecondOrder Modulator Since the singleloop architecture with order higher than 2 are unstable, it is necessary to find alternative architectures that allow stable higher order modulators. A cascaded, secondorder structure: X 2 (z) z z Y 2 (z) Q (z) Y (z) = (z)q (z) zx(z) X(z) z Y (z) Y(z) z z X 2 (z) = z z z (X(z) Y (z) Fig.0.97 = z z X(z) z z [(z )Q (z) zx(z)] Y 2 (z) = (z)q 2 (z) zx 2 (z) = (z)q 2 (z) z2 z X(z) z 2Q (z) z2 z X(z) = (z)q 2 (z) z2q (z) Y(z) = Y 2 (z) zy 2 (z) z2y (z) = (z)y 2 (z) z2y (z) = (z)2q 2 (z) (z)z2q (z) (z)z2q (z) z3x(z) = (z)2q 2 (z) z3x(z) Y(z) = (z)2q 2 (z) z3x(z) Q 2 (z) Lecture 390 Oversampling ADCs Part I (3/29/0) Page 39020 ThirdOrder, MASH Modulator It can be shown that Y(z) = X(z) (z)3q 3 (z) This results in a 3 rd order noise shaping and no delay between the input and output. Q (z) X(z) Y(z) z Y (z) z Q (z) Q 2 (z) z z Y 2 (z) z Q 2 (z) z Q 3 (z) z z Comments: The above structures that eliminate the noise of all quantizers except the last are called MASH or multistage architectures. Digital error cancellation logic is used to remove the quantization noise of all stages, except that of the last one. z Y 3 (z) Fig. 0.97A
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 3902 A FourthOrder, MASHtype Modulator using Scaling of Error Signals X in (z) z z z z a /C b a 2 b 2 Q (z) Q 2 (z) z z D 2 (z) z z D (z) z z 062070 The various transfer functions are (a =, a 2 =2, b =, b 2 =2, l =2 and C = 4) : λ z The signal is divided by /C as it passes from the first 2 nd order modulator to the second 2 nd order modulator. The digital output of the second 2 nd order modulator is then multiplied by the inverse factor of C. U.S. Patent 5,06,928, Oct. 29, 99. z D (z) = X in (z) (z ) 2 Q (z) D 2 (z) = (/C)(Q (z)) (z ) 2 Q 2 (z) D out (z) = X in (z) (z ) 4 Q 2 (z) C D out (z) Lecture 390 Oversampling ADCs Part I (3/29/0) Page 39022 Distributed Feedback Modulator FourthOrder X a z Y a 2 z Y 2 a 3 z Y 3 a 4 z Y 4 bit z z z z A/D Q Y Amplitude of integrator outputs: bit D/A Fig.0.920 amplitude of integrator output / VREF.50.25.00 0.75 0.50 0.25 fourth order distributed feedback modulator a=0., a2=0., a3=0.4, a4=0.4 y y2 y3 y4 0.00.00 0.60 0.20 0.20 0.60.00 input signal amplitude / VREF
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 39023 Distributed Feedback Modulator FourthOrder Continued X a z Y a 2 z Y 2 a 3 z Y 3 a 4 z Y 4 bit z z z z A/D.50 bit A/D fourth order feedforward modulator a=0.5, a2=0.4, a3=0., a4=0. Q Y Fig.0.920 Amplitude of integrator outputs (Integrator constants have been optimized to minimize the integrator outputs): amplitude of integrator outputs.25.00 0.75 0.50 0.25 0.00.00 y y2 y3 y4 0.60 0.20 0.20 0.60.00 input signal amplitude / VREF Lecture 390 Oversampling ADCs Part I (3/29/0) Page 39024 Cascaded of a SecondOrder Modulator with a FirstOrder Modulator q X a z a 2 z z z Fig.0.92 β α q 2 a 3 z z Digital error cancellation circuit Comments: The stability is guaranteed for cascaded structures The maximum input range is almost equal to the reference voltage level for the cascaded structures All structures are sensitive to the circuit imperfection of the first stages The output of cascaded structures is multibit requiring a more complex digital decimator Y
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 39025 Integrator Circuits for Modulators Fundamental block of the modulator: V i (z) FullyDifferential, Switched Capacitor Implementation: a z V o (z) V i (z) az V o (z) z Fig.0.922 It can be shown (Chapter 9 of the text) that, V out (z) V in (z) = C s z C i z Vout(e o jt ) Vin(e o jt ) = C e jt/2 T C 2 j2sin(t/2) T = C jtc 2 T/2 sin(t/2) e jt/2 Vout(e o jt ) Vin(e o jt ) = (Ideal)x(Magnitude error)x(phase error) where I = C TC 2 v in φ φ φ 2 C s φ C s 2 φ φ φ2 φ 2 C i C i v out Fig.0.923 Ideal = I j Lecture 390 Oversampling ADCs Part I (3/29/0) Page 39026 Power Dissipation versus Supply Voltage and Oversampling Ratio The following is based on the above switchedcapacitor integrator:.) Dynamic range: The noise in the band [f s,f s ] is kt/c while the noise in the band [f s /2M,f s /2M] is kt/mc. We must multiply this noise by 4; x2 for the sampling and integrating phases and x2 for differential operation. DR = V DD 2 /2 4kT/MC s = V DDMC 2 s 8kT C 2.) Lower bound on the sampling capacitor, C s : s = 8kT DR VDDM 2 3.) Static power dissipation of the integrator: P int = I b V DD 4.) Settling time for a step input of V o,max : I b = C i V o,max T = C i settle C s T settle C V i DD = C sv DD T = C settle s V DD (2f s ) = 2Mf N C s V DD P int = 2Mf N C s V DD 2 = 6kT DR f N Because of additional feedback to the first integrator, the maximum voltage can be 2V DD. P stint = 32kT DR f N
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 39027 SUMMARY Oversampled ADCs allow signal bandwidth to be efficiently traded for resolution Noise shaping oversampled ADCs preserve the signal spectrum and shape the noise quantization spectrum The modulator shapes the noise quantization spectrum with a high pass filter The quantizer can be single or multiple bit Single bit quantizers do not require linear DACs because a bit DAC cannot be nonlinear Multiple bit quantizers require ultra linear DACs Modulators consist of combined integrators with the goal of highpass shaping of the noise spectrum and cancellation of all quantizer noise but the last quantizer