Data Sheet Optical Modulator Driver with Internal Attenuator and Power Detector FEATURES 32.0 Gbps maximum data rate 13 ps typical output rise time and fall time 28 GHz bandwidth Self biased, no power sequencing required Adjustable gain Integrated output peak detector Low power consumption 0.5 W with 3.3 V positive/negative external supply voltage 0.44 W with 2.5 V positive/negative external supply voltage Use with compact bias tee: 1 inch 0402 + 1 inch 0603, SMT only 16-terminal, 2.9 mm 2.9 mm, leadless chip carrier (LCC) package Differential balanced outputs APPLICATIONS Communication infrastructure: 400 G 16 QAM, 100 G DP-QPSK pluggable optical modules in CFP/CFP2 Broadband gain stage and pre-amplifiers Broadband test and measurement equipment INP INN V DD FUNCTIONAL BLOCK DIAGRAM ATTENUATOR CONTROL GND (VCTL) PEAK DETECTOR (VDET, VREF) AMPLITUDE CONTROL (VC) Figure 1. V DD_EXTP OUTP OUTN V DD_EXTN BIAS TEE BIAS TEE 16229-001 GENERAL DESCRIPTION The is a differential input and differential output, broadband linear amplifier, capable of driving a differential indium phosphate (InP) Mach-Zehnder (MZ) modulator for data center interconnect fiber optics or silicon photonics, or driving a single-ended, electroabsorption modulated laser (EML) modulator for short reach or metro applications. The supports data rates up to 32.0 Gbps with a gain flatness of up to 20 GHz. The integrated peak detector at the output enables system designers to maintain constant output by adjusting the gain of the amplifier via the VCTL pin through an external automatic gain control (AGC) circuit. The IC provides module designers with scalable supplies for optimizing power dissipation vs. required linearity. The IC is in a 2.9 mm 2.9 mm leadless chip carrier (LCC) package and requires an external bias tee. The differential input and differential are externally ac-coupled. No power supply sequencing is required. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 General Description... 1 Revision History... 2 Specifications... 3 Timing Specifications... 4 Absolute Maximum Ratings... 5 Thermal Resistance... 5 ESD Caution... 5 Pin Configuration and Function Descriptions... 6 Data Sheet Typical Performance Characteristics...7 Frequency Domain Properties...8 Theory of Operation... 10 Applications Information... 11 Reflow Solder Profile... 11 Evaluation Board... 12 Evaluation Board Schematic... 12 Evaluation PCB Outline... 13 Outline Dimensions... 14 Ordering Guide... 14 REVISION HISTORY 2/2018 Revision 0: Initial Version Rev. 0 Page 2 of 14
Data Sheet SPECIFICATIONS All specifications with positive supply voltage (VDD) = 3.3 V, positive and negative external supply voltage (VDD_EXTP/VDD_EXTN) = 2.5 V or 3.3 V, TMIN to TMAX, typical values are specified at TA = 25 C at maximum data rate, unless otherwise stated. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments MAXIMUM DATA RATE 28.3 32.0 Gbps Nonreturn to zero (NRZ), pseudorandom binary sequence (PRBS31) = 2 31 1 BANDWIDTH High 28 GHz Low Cutoff 1 MHz VOLTAGE RANGE Differential Input 0.2 1.0 V With adjusted control voltage (VCTL); for differential input voltage levels higher than 550 mv p-p, adjust VCTL to keep the driver in linear operation Output 4.4 V Measured with PRBS31 and differential input of 600 mv p-p and VCTL = 1.5 V Single-Ended 2.2 V Measured with PRBS31 and differential input of 600 mv p-p and VCTL = 1.5 V SMALL SIGNAL GAIN Differential to Differential 4 17 18 db Adjustable through VCTL control voltage, 1 MHz to 28 GHz, maximum gain: VCTL = 1.5 V, minimum gain: VCTL = 0 V Differential to Single-Ended 2 11 12 db 1 MHz to 28 GHz GAIN FLATNESS ±1 db 1 MHz to 20 GHz, 1.5 V < VCTL < 0 V RETURN LOSS Input Differential 15 db 100 MHz to 20 GHz, VCTL = 1.15 V 10 db VCTL = 1.5 V Single-Ended 15 db 100 MHz to 10 GHz, VCTL = 1.15 V 10 db VCTL = 1.5 V Single-Ended Output 15 db 100 MHz to 10 GHz 10 db 10 GHz to 30 GHz SIGNAL-TO-NOISE RATIO (SNR) 22 db Input voltage (VIN) = 560 mv p-p, VCTL = 1.5 V TOTAL POWER CONSUMPTION VDD = 3.3 V 0.44 W VDD_EXTP, VDD_EXTN = 2.5 V 0.5 W VDD_EXTP, VDD_EXTN = 3.3 V TOTAL HARMONIC DISTORTION (THD) At 1 GHz 2 % At 3 V p-p 3 % At 4 V p-p VC PIN VOLTAGE VVC 0 0.5 1.5 V VCTL PIN VOLTAGE VVCTL 1.5 0 V CONTROL SOURCE CURRENT IVC 2 ma IVCTL 1 ma COMMON-MODE REJECTION RATIO 25 db SUPPLY VOLTAGE TOLERANCE 8 +5 % VDD = 3.3 V 8 +5 % VDD_EXTP/VDD_EXTN = 3.3 V 5 +5 % VDD_EXTP/VDD_EXTN = 2.5 V Rev. 0 Page 3 of 14
Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments RESISTANCE Input Differential 100 Ω Single-Ended 50 Ω Output Differential 100 Ω Single-Ended 50 Ω TIMING SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments GROUP DELAY VARIATION ±7.5 ps 1 GHz to 30 GHz OUTPUT Rise Time 13 ps 20% to ~ 80% Fall Time 13 ps 20% to ~ 80% Jitter VCTL = 1.5 V Additive RMS 350 fs VDD_EXTP, VDD_EXTN = 2.5 V 400 fs VDD_EXTP, VDD_EXTN = 3.3 V Deterministic 3 ps VDD_EXTP, VDD_EXTN = 3.3 V and 2.5 V Rev. 0 Page 4 of 14
Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Positive VDD Supply to GND 12 V INN and INP to GND 2 V OUTP to GND 12 V VC to GND 2.5 V VCTL to GND 2.5 V to +0.5 V Electrostatic Discharge (ESD) Protection Human Body Model (HBM) Class 1A, 250 VRF, 500 VDC Charged Device Mode (CDM) 1500 V Maximum Reflow Temperature Moisture Sensitivity Level 3 (MSL3) 260 C Operating Temperature Range 40 C to +130 C Maximum Junction Temperature (TJ) 175 C Storage Temperature Range 65 C to +150 C Lead Temperature (Soldering, 60 sec) 300 C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 4. Thermal Resistance Package Type 1 θja 2 θjc 3 Unit E-16-1 53 51 C/W 1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with nine thermal vias. 2 θja is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. 3 θjc is the junction to case thermal resistance. ESD CAUTION Rev. 0 Page 5 of 14
Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD VDET NIC VREF 16 15 14 13 GND 1 INN 2 INP 3 GND 4 TOP VIEW (Not to Scale) 12 GND 11 OUTN 10 OUTP 9 GND 5 6 7 8 NIC VCTL NIC VC NOTES 1. NIC = NOT INTERNALLY CONNECTED. THIS PIN IS NOT CONNECTED INTERNALLY. 2. EXPOSED PAD. THE LCC PACKAGE HAS AN EXPOSED PAD THAT MUST BE CONNECTED TO SUPPLY GND. Figure 2. Pin Configuration 16229-002 Table 5. Pin Function and Descriptions Pin No. Mnemonic Description 1, 4, 9, 12 GND Supply GND. 2 INN Data Negative Differential Input. 3 INP Data Positive Differential Input. 5, 7, 14 NIC Not Internally Connected. This pin is not connected internally. 6 VCTL Analog Attenuator Control Voltage. 8 VC Amplitude Control Voltage. 10 OUTP Positive Differential Output. 11 OUTN Negative Differential Output. 13 VREF Reference Voltage for Detector. 15 VDET Detector Voltage Output. 16 VDD Supply Voltage. EPAD Exposed Pad. The LCC package has an exposed pad that must be connected to supply GND. Rev. 0 Page 6 of 14
Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Time domain properties, typical 32 Gbps NRZ output eye diagram, measured with PRBS31 pattern and 600 mv p-p differential input. 1 OPEN 950mV 1 OPEN 950mV 0 OPEN 920mV 0 OPEN 920mV BIT RATE 31.780GBPS FALL TIME 13.130ps DCD(%) 2% RISE TIME 13.200ps EYE AMPL 2.317V CROSSING % 51.2% SNR 15.52 EYE HEIGHT (AMPL) 1.869V JITTER (p-p) JITTER (rms) 4.6545ps 767.5fs 16229-003 CURRENT MINIMUM MAXIMUM TOTAL MEAS JITTER RMS 686fs 674fs 699fs 28 RISE TIME 13.11ps 13.11ps 13.33ps 28 EYE SNR 8.28 8.28 8.37 28 EYE AMP 3.19V 3.19V 3.19V 28 16229-006 Figure 3. Single-Ended Output, 2.3 V p-p Swing Figure 6. Differential Output, VCTL = 1 V 1 LEVEL 2.26V 1 LEVEL 2.26V 0 LEVEL 2.28V 0 LEVEL 2.28V BIT RATE 32.060GBPS FALL TIME 13.545ps DCD(%) 0% RISE TIME 13.685ps EYE AMPL 4.536V CROSSING % 49.6% SNR 16.59 EYE HEIGHT (AMPL) 3.716V JITTER (p-p) JITTER (rms) 5.4185ps 905.5fs Figure 4. Differential Output, 4.5 V p-p Swing 16229-004 CURRENT MINIMUM MAXIMUM TOTAL MEAS JITTER RMS 1.058ps 1.045ps 1.089ps 29 RISE TIME 14.44ps 14.44ps 12.67ps 29 EYE SNR 15.46 15.33 15.46 29 EYE AMP 4.76V 4.75V 4.76V 29 Figure 7. Differential Output, VCTL = 1.5 V 16229-007 CURRENT MINIMUM MAXIMUM TOTAL MEAS JITTER RMS 969fs 933fs 980fs 29 RISE TIME 14.22ps 13.56ps 14.22ps 29 EYE SNR 7.25 7.24 7.30 29 EYE AMP 1.95V 1.94V 1.95V 29 Figure 5. Differential Output, VCTL = 0 V 16229-005 Rev. 0 Page 7 of 14
FREQUENCY DOMAIN PROPERTIES DIFFERENTIAL TO SINGLE-ENDED GAIN (db) 16 14 12 10 8 6 4 2 0 VCTL = 0.8V VCTL = 0.9V VCTL = 1.0V VCTL = 1.1V VCTL = 1.2V VCTL = 1.3V VCTL = 1.4V VCTL = 1.5V VCTL = 0V VCTL = 0.1V VCTL = 0.2V VCTL = 0.3V 2 0.01 4.79 9.57 14.35 19.13 23.91 28.69 FREQUENCY (GHz) VCTL = 0.4V VCTL = 0.5V VCTL = 0.6V VCTL = 0.7V Figure 8. Differential to Single-Ended Gain (S21) vs. Frequency with Respect to the VCTL Pin, Measurement Taken with EV1LC3 Evaluation Board (Fixture Not De-Embedded) DIFFERENTIAL TO DIFFERENTIAL GAIN (db) 0 5 10 15 20 25 30 35 40 45 50 55 VCTL = 1V VCTL = 1.3V 60 VCTL = 1.1V VCTL = 1.2V VCTL = 1.4V VCTL = 1.5V 65 0.01 4.79 9.57 14.35 19.13 23.91 28.69 FREQUENCY (GHz) Figure 9. Differential to Differential Gain (S11) vs. Frequency with Respect to the VCTL Pin, Measurement Taken with EV1LC3 Evaluation Board (Fixture De-Embedded) 16229-008 16229-009 DIFFERENTIAL OUTPUT (V p-p) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 +130 C +25 C 40 C Data Sheet 1.0 200 300 400 500 600 700 800 DIFFERENTIAL INPUT (mv p-p) Figure 11. Differential Output vs. Differential Input, Measured at 1 GHz Sine Wave V PEAK (V) = V DET V REF 0.12 0.10 0.08 0.06 0.04 0.02 0 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 ANALOG ATTENUATION (V) Figure 12. Peak Voltage (VPEAK) = Detector Output Voltage (VDET) Reference Voltage (VREF) vs. Analog Attenuation 16229-011 16229-012 0 300 DIFFERENTIAL TO DIFFERENTIAL GAIN (db) 5 10 15 20 25 30 35 40 45 50 55 60 +130 C, S11 (db) +25 C, S22 (db) 65 +130 C, S22 (db) 40 C, S11 (db) 70 +25 C, S11 (db) 40 C, S22 (db) 0.01 4.79 9.57 14.35 19.13 23.91 28.69 FREQUENCY (GHz) 16229-010 V PEAK (V) = V DET V REF 250 200 150 100 50 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 DIFFERENTIAL OUTPUT (V) 16229-013 Figure 10. Differential to Differential Gain (S11, S22) vs. Frequency, VCTL Pin = 1.5 V, Zoomed for Gain Flatness (Fixture De-Embedded) Figure 13. VPEAK = VDET VREF vs. Differential Output Rev. 0 Page 8 of 14
Data Sheet 9 5.5 TOTAL HARMONIC DISTORTION (%) 8 7 6 5 4 3 2 1 +130 C +25 C 40 C DIFFERENTIAL OUTPUT (V p-p) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 900mV p-p 700mV p-p 500mV p-p 300mV p-p 0 200 300 400 500 600 700 800 DIFFERENTIAL INPUT (mv p-p) Figure 14. Total Harmonic Distortion (THD) vs. Differential Input 16229-014 0 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 V CTL (V) Figure 16. Differential Output vs. VCTL, Voltage Measured at Various Differential Input Voltages, 32 Gbps PRBS31 Data at the Input 16229-016 TOTAL HARMONIC DISTORTION (%) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 V CTL (V) 800mV p-p 600mV p-p 400mV p-p 200mV p-p 16229-015 Figure 15. Total Harmonic Distortion vs. VCTL, Voltage Measured at Various Differential Input Voltages Rev. 0 Page 9 of 14
THEORY OF OPERATION The is a broadband linear amplifier with a differential input and output. The device supports a maximum data rate of 32.0 Gbps with a typical bandwidth of 28 GHz. The is self biased and does not requires any bias sequencing or current adjustment circuitry. The device has two external supply voltages: VDD = 3.3 V supply at the supply pin and VDD_EXTP/VDD_EXTN. The VDD_EXTP/VDD_EXTN supply has two options: 2.5 V, which achieves better jitter performance, and 3.3 V, which achieves higher output voltage swings. Data Sheet The includes an integrated analog that allows a gain adjustment of at least 6 db. When VCTL is 1.5 V, the gain is maximum, and when VCTL is 0 V, the gain is minimum. The contains a peak detector that behaves linearly with respect to the output swing. The peak detector has two outputs, VDET and VREF. Use the difference of these voltages to read the output voltage swing. To implement an external automatic gain control, use an analog attenuator and the features of the peak detector. Rev. 0 Page 10 of 14
Data Sheet APPLICATIONS INFORMATION The can drive Mach-Zehnder modulators in differential or single-ended operation. To keep the output swing constant at a desired value, build an analog or digital gain control loop. To build a gain control loop, use the voltage difference of the VREF and VDET pins (VPEAK) as an input to an analog or digital gain control mechanism to drive the VCTL pin (see Figure 17). The requires an external bias from the output side; however, the modulator bias can be provided after a dc blocking capacitance. INP OUTP V DD_EXTP MODULAR POSITIVE BIAS MACH-ZEHNDER MODULATOR REFLOW SOLDER PROFILE Figure 18 shows the typical, Pb-free reflow solder profile. TEMPERATURE ( C) RAMP UP 3 C/SECOND MAX 217 C 60 TO 180 SECONDS 480 SECONDS MAX 60 TO 150 SECONDS 260 5 C/260 + 0 C 150 C TO 200 C RAMP DOWN 6 C/SECOND MAX TIME (Second) 20 TO 40 SECONDS Figure 18. Typical Pb-Free Reflow Solder Profile 16229-026 INN OUTN VCTL ANALOG OR DIGITAL GAIN CONTROL VDET VREF V DD_EXTN MODULAR NEGATIVE BIAS Figure 17. Analog or Digital Gain Control Loop 16229-027 Rev. 0 Page 11 of 14
Data Sheet EVALUATION BOARD EVALUATION BOARD SCHEMATIC Figure 19 shows the schematic for the EV1LC3 evaluation board. Table 6 lists the bill of materials. TP2 VDET TP3 VREF C13 C19 C18 C21 C20 C16 TP1 VDD C10 4.7µF C17 C15 100pF 16 15 14 13 U1 LC3 FB4 470Ω C22 100nF FB3 470Ω OUTN J4 1492-04A-5 J1 INN 1492-04A-5 J2 INP 1492-04A-5 C4 100nF C5 100nF 1 GND 2 INN 3 INP 4 GND VDD VDET NIC VREF NIC VCTL NIC VC 5 6 7 8 12 GND 11 OUTN 10 OUTP 9 GND L8 10µH C32 100pF C33 R4 475Ω V DD_EXTN C34 1µF C1 100nF TP9 L6 10µH C35 100pF C36 R3 475Ω V BIAS_EML_N C37 1µF OUTP TP11 J3 TP4 TP5 TP6 VCTL NIC VC C7 C8 C9 FB2 470Ω L4 10µH C29 100pF C30 R2 475Ω V DD_EXTP C31 1µF TP7 FB1 470Ω L2 10µH C38 100pF C39 R1 475Ω V BIAS_EML_P C40 1µF 1492-04A-5 TP10 GND TP8 J5 C25 C27 J7 J6 C26 C28 J8 16229-017 Figure 19. Evaluation Board Schematic Table 6. Bill of Materials Qty. Reference Designator Description Manufacturer/Part Number 1 EV1LC3 Evaluation board Analog Devices, Inc./EV1LC3 4 C1, C4, C5, C22 100 nf, 16 V, tin, ultra broadband capacitor American Technical Ceramics/ATC550L101KT16T 5 C7, C9, C17, C19, C20, C30, 1 nf, 50 V, X7R, 0402, ceramic capacitor Murata/GRM15555C1H101J C33, C36, C39 9 C8, C13, C16, C18, C21, C25 to Do not populate Not applicable C28 1 C10 4.7 μf, 25 V, 10%, X7R, 0603, gold terminal ceramic capacitors Capax Technologies, Inc./0603X475K250GW 5 C15, C29, C32, C35, C38 100 pf, 50 V, 5%, C0G, 0402, ceramic capacitors Murata/GRM155R71H102KA01D 4 C31, C34, C37, C40 1 μf, 16 V, 10%, X5R, 0402, ceramic capacitors Taiyo Yuden/EMK105BJ105KV-F 4 FB1 to FB4 Ferrite chips, 470 Ω, 200 ma, 0402 Murata/BLM15GG471SN1D 4 J1 to J4 Connectors, K connector SRI Connector Gage Co./25-146-1000-92 3 J5 to J8 Do not populate 4 L2, L4, L6, L8 Inductors, 10 μh, 0603, 5%, 0.18 A Coilcraft/0603LS-103XJLB 4 R1 to R4 475 Ω, 1/10 W, 1%, 0402, resistors, SMD Panasonic/ERJ-2RKF470X Rev. 0 Page 12 of 14
Data Sheet Qty. Reference Designator Description Manufacturer/Part Number 8 TP1 to TP4, TP6 to TP9 Test point, PC compact, 0.063 inch, red Keystone Electronics/5005 1 TP5 Do not populate 1 TP10 Test point, PC, compact, 0.063 inch, black Keystone Electronics/5006 1 U1 Optical modulator driver with internal attenuator and power detector Analog Devices/LC3 EVALUATION PCB OUTLINE THRU CAL 600-01085-00-2 GND VDD VDET VREFV_EX_N TP10 TP1 TP2 TP3 TP9 C10 J4 J1 J2 INN INP C4 C5 C20 OUTN C17 C34 C19 C33 C32 C35 L8 R4 FB3 L6 C36 FB4C22R3 U1 C37 FB2C1 R1 C40 L2 C39 L4 R2 FB1 C38 C29 C30 C31 C15 C7 C9 OUTP VCTL VC V_EX_P J3 VB_E TP8 SEE NOTE 4 4 TP4 TP6 TP7 1 PCB NOTES 1. SOLDER QUALITY TO IPC-A-610 CLASS 2. 2. MANUALLY DISPENSE SOLDER (ITEM 5) FOR ALL COMPONENTS. 3. J1 TO J4, ATTACH TO PCB WITH CENTER PIN ON TOP SIDE TRACE. MANUALLY DISPENSE SOLDER (ITEM 5) TO CENTER PIN AND GROUND LEADS, TOP AND BOTTOM. AFTER REFLOW, SOLDER MUST JOIN CONNECTOR AND PCB EDGE. 4. TRIM EDGE PLATING WITH ITEM 6 (106356). Figure 20. Evaluation Board PCB 16229-028 Rev. 0 Page 13 of 14
Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 3.05 2.90 SQ 2.75 0.08 BSC 13 0.36 0.30 0.24 16 PIN 1 0.50 BSC 12 EXPOSED PAD 1 1.60 1.50 SQ 1.40 9 4 PKG-004838 0.90 0.80 0.70 SEATING PLANE TOP VIEW SIDE VIEW 0.32 BSC 8 5 BOTTOM VIEW 1.50 REF 2.10 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-24-2017-C Figure 21. 16-Terminal Leadless Ceramic Chip Package [LCC] (E-16-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 Temperature Range Package Description Lead Finish Package Option LC3 40 C to +130 C 16-Terminal Leadless Ceramic Chip Carrier [LCC] Nickel/gold (NiAu) E-16-1 LC3TR 40 C to +130 C 16-Terminal Leadless Ceramic Chip Carrier [LCC] NiAu E-16-1 EV1LC3 Evaluation Board with Bias Tee and AC-Coupled Input/Output Capacitors 1 The LC3 and the LC3TR models are RoHS Compliant Parts. 2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16229-0-2/18(0) Rev. 0 Page 14 of 14