State of Demonstrated HV GaN Reliability and Further Requirements

State of Demonstrated HV GaN Reliability and Further Requirements APEC 2015 Charlotte, NC Tim McDonald Steffen Sack, Deepak Veereddy, Yang Pan, Hyeongnam Kim, Hari Kannan, Mohamed Imam

Agenda What Composes a High Voltage Device? How to ensure GaN devices meet lifetime requirements of a given application? JEDEC qualification insufficient! Application stability? DC stability? Multiple aspects/components required Multi dimensional approach is proposed Data for each dimension for HV devices provided Further work 2

Sample Silicon Test Plan Accelerated Environment Stress Tests REQUIRED RELIABILITY TESTS Parameter Part Type Test Conditions Duration measurements @ Quantity Part no X TC -55 C/150 C 1000 cy 0/168/500/1000 3 x 77 H 3 TRB 85 C/85%RH/100V 1000 hrs 0/168/500/1000 3 x 77 HTRB 150 C/960V /480V 1000 hrs 0/168/500/1000 3 x 77 HTGB 150 C/20V 1000 hrs 0/168/500/1000 3 x 77 IOL delta Tj = 100 C 5,000 cy 0/2500/5000 3 x 77 AC 121 C/15psig 96 hrs 0/96 3 x 77 On what basis can one assume that the test conditions typically used in Si Device qualification, if applied to qualify GaN Devices, will assure a given useful life in application? 3

Ingredients to Drive a Test Plan QRP Quality Requirement Profile Rel. Investigation at Development Phase Application Profile Degradation Models Released Product 4

Ingredients to Drive a Test Plan QRP Quality Requirement Profile Rel. Investigation at Development Phase Application Profile Degradation Models Released Product 5

Application Profile - The Application Profile displays the technical details of the different target applications in respect to the expected use conditions at the customer side. - Within the Application Profile the following information are given: - Application Lifetime - Operating hours, duty cycles - Switching frequencies - Currents, voltages, temperatures at different load conditions - Use times of different load profiles - Amount/Time of abnormal use conditions within lifetime (e.g. AC line cycle drop out) - Currents/Voltages at peak and spikes during switching - Description of peak/spike forms and durations In a single phrase: The Application Profile displays the typical use conditions in the target applications 6

DC 100V 200V 300V 400V 480V 480V 480V 480V 480V 480V 480V75C 480V75C 480V75C 480V75C 480V75C 480V150C 480V150C 480V150C 480V150C 480V150C d-rdson (Ohm) HV GaN HEMT dynamic Rds(on): Today 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 25 to 150C, 100V to 480V, f sw = 100 Hz, DC = 1% After bias RDSon is stable with voltage At 75C and 150C : Rds(on) is stable after bias (increase is due to expected change with temperature). 1us 5us Bias (each point separated in time by 1 min) Negligible dynamic Rds(on) effect over drain voltages (up to 480V) and temperatures is observed.

Tcase ( o C) Device Ruggedness: Long-Term PFC (Boost) Application Testing 120 100 80 225 W, 120V:500V DC to DC conversion at 100 khz Measured package Temperature is a proxy for power dissipated: Δ T = R TH x P loss, which correlates to Efficiency. Devices are shown stable in efficiency for >1200 hours 60 Stable efficiency (case temperature) to >1200 hours 40 200 400 600 800 1000 1200 Time (Hours) 600V Cascode GaN switches demonstrate stable operation over 1200 hours of continuous PFC application testing

Ingredients to Drive a Test Plan QRP Quality Requirement Profile Rel. Investigation at Development Phase Application Profile Degradation Models Released Product 9

QRP - Quality Requirement Profile - The QRP displays the development targets of a new technology/product in respect to it s reliability performance and the target applications - Within the QRP following information are given: - General definition of target applications (Technical details in application profile) - Maximum operation voltages and currents - Operation temperature range - ESD classification - MSL-class definition - Lifetime targets/failure rates for device, dielectrics and metallization - Definition of parameter drift limits (e.g. Vth, Ids,leakage, Ron,...) and time to failure for dielectric breakdowns or migration effects In a single phrase: The QRP displays the reliability target of a development project 10

Example Element of Quality Requirement Temp. Profile Conversion The different temperatures are corresponding to varying levels of output power and ambient temperatures over the application lifetime. The electrical biased tests has to consider this thermal profile. Using acceleration models the application profile can be converted to useful stress conditions. Temp. Profile of Application Time /h Temp. / C 3504 30 28032 50 35040 70 3504 105 S = 70080 (~8a) Profile conversion with temp. accel. model to equivalent temp. profile Converted Temp. Profile to Mean Temp. over Lifetime Time /h Temp. / C 70080 67.5 Time /h Mean Temp. over Lifetime Converted to Accelerated Stress Condition Temp. / C This example assumes Silicon device with Activation Energy of 0.5 ev 1181 175 11

Ingredients to Drive a Test Plan QRP Quality Requirement Profile Rel. Investigation at Development Phase Application Profile Degradation Models Released Product 12

Reliability Investigation at Development Phase - Check reliability capabilities starting with first full design wafers - Perform DoE s (Design of Experiment) during learning cycles and assess reliability to find optimal process flow and define process windows - Confirm a sufficient quality before starting the final qualification phase - Learn about the typical failure modes and create degradation/lifetime models - Adaption or creation of test methods to address new failure mechanisms and modes - Based on derived lifetime models screening procedures can be implemented if needed In a single phrase: During development phase reliability investigations are driven to assess and improve technology reliability and learn about failure mechanisms and generate models on them 13

Reliability of 600V devices in HTRB (150C, 480V) Early Reliability data for 3 lots, 77 pcs each Rdson stable through 1000 hours Interval Lot number

Reliability of 600V GaN Devices up to 5,000 hours of HTRB 600V GaN devices are inherently reliable Source-drain resistance Rdson of 600 V rated cascode switch for a population of representative cascoded GaN-on-Si based HEMT devices with Wg = 120 mm, under a drain bias of 480 V and 0 gate bias for 5000 hrs at 150 C. 15

Ingredients to Drive a Test Plan QRP Quality Requirement Profile Rel. Investigation at Development Phase Application Profile Degradation Models Released Product 16

MTTF (hrs) FIT rate (FIT) MTTF and FIT Rate for HV Gate Dielectric Material 10 15 MTTF at RT 10 13 MTTF at 85C MTTF at 110C 10 11 MTTF at 150C 10 9 10 7 10 5 MTTF & FIT Rate vs Stress voltage 10 10 10 8 10 6 10 4 10 2 10 0 Preliminary predictions: MTTF > 10 8 hrs; FIT~1 @ application conditions 10 3 10 1 10-1 FIT rate at RT FIT rate at 85C FIT rate at 110 C FIT rate at 150 C 5 6 7 8 9 10 11 12 13 14 15 16 17 18 V GSS (V) 10-2 10-4 10-6 Degradation models required for component structures of the GaN HEMT: Gate dielectric AlGaN/GaN material Passivation materials Metallization (electromigration) 17 17

Time Dependent Dielectric Breakdown Related Reliability Ceramic Capacitors : Accelerated Stress Conditions Prokopowicz and Vaskas Equation Michael S. Randall et al (KEMET), Proceedings of CARTS 2003 pp. 1-7

MTTF [Hrs] Preliminary Reverse Bias Lifetime Estimate for early HV GaN Devices 25C 1E+11 1E+10 1E+9 1E+8 1E+7 1E+6 1E+5 1E+4 1E+3 1E+2 1E+1 1E+0 1E-1 Based on Testing to failure at 825V, 800V and 775V: Projected meantime to failure at 480V bias (25C) is 2E7 hours or >2200 years. 300 350 400 450 500 550 600 650 700 750 800 850 900 Stress Voltage [V] Engineering Evaluation of Early Samples

MTTF [Hrs] Preliminary Reverse Bias Lifetime Estimate for early HV GaN Devices 25C 1E+11 1E+10 1E+9 1E+8 1E+7 1E+6 1E+5 1E+4 1E+3 1E+2 1E+1 1E+0 1E-1 -Use accelerated data to set test conditions for 1,000 hr testing (ie: to generate a meaningful Test Plan) -Use statistics to calculate FIT rate at required lifetime and use conditions 300 350 400 450 500 550 600 650 700 750 800 850 900 Stress Voltage [V] Engineering Evaluation of Early Samples

Ingredients to Drive a Test Plan QRP Quality Requirement Profile Rel. Investigation at Development Phase Application Profile Degradation Models Released Product 21

Test Plan The testplan includes: - Definition of sample size in respect to internal and common standards like JEDEC, Q101, etc. - All tests and test parameters to address all known degradation modes. - All tests with critical reliability impact seen during the development phase testing where the test parameters reflect the outcome of the degradation and acceleration models. - All tests and test conditions required in the international norms - The results of the tests will be judged and as pass or fail label displayed in the list. Criterias are given within the QRP and data sheet limits In a single phrase: The qualification test plan summarizes all relevant reliability tests to assure that the required lifetime and failure rate limits are fulfilled. 22

Sample Silicon Test Plan Accelerated Environment Stress Tests REQUIRED RELIABILITY TESTS Parameter Part Type Test Conditions Duration measurements @ Quantity Part no X TC -55 C/150 C 1000 cy 0/168/500/1000 3 x 77 H 3 TRB 85 C/85%RH/100V 1000 hrs 0/168/500/1000 3 x 77 HTRB 150 C/960V /480V 1000 hrs 0/168/500/1000 3 x 77 HTGB 150 C/20V 1000 hrs 0/168/500/1000 3 x 77 IOL delta Tj = 100 C 5,000 cy 0/2500/5000 3 x 77 AC 121 C/15psig 96 hrs 0/96 3 x 77 With knowledge of Failure mechanisms and appropriate modeling and with detailed application and qualification requirements profiles the test conditions of the qualification can be chosen to assure required useful life is met. 23

Ingredients to Drive a Test Plan QRP Quality Requirement Profile Rel. Investigation at Development Phase Application Profile Degradation Models Released Product 24

Summary -To qualify GaN on Si devices it is insufficient to follow standard Silicon qualification matrix -5 required elements to a qualification are described: the qual matrix is only 1 component -Establishing GaN device performance to all 5 elements will assure reliable operation to a specified application -Preliminary GaN device reliability data is provided to illustrate the elements -A full qualification will include fully addressing all 5 dimensions In a single phrase: To qualify GaN on Silicon it is not sufficient to follow the existing JEDEC Std Matrix; a comprehensive 5 element methodology is proposed that will assure reliable operation to a given application profile 25

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