Field Effect Transistors (FET s) University of Connecticut 136
Field Effect Transistors (FET s) FET s are classified three ways: by conduction type n-channel - conduction by electrons p-channel - conduction by holes by zero-gate-bias state Enhancement Type - normally off Depletion Type - normally on by gate structure MOSFET - metal oxide semiconductor FET JFET - junction FET MESFET - metal semiconductor FET University of Connecticut 137
Field Effect Transistors (FET s) MOSFET displacing other devices as dimensions shrink basis of Intel, Cyrix, AMD, Motorola microprocessors, and the 1 Gb DAM currently being developed JFET normally off devices are very difficult to fabricate not presently used in digital IC s MESFET same problems as JFET high-speed logic gates can be realized with GaAs DCFL (50 ps propagation delays) basis of Cray Y-MP and some top-end microprocessors University of Connecticut 138
Enhancement-type n-mosfet thin gate oxide <100 Angstroms source contact n+ p substrate n+ polysilicon gate metal drain contact thick field oxide (5000 Angstroms) CUTOFF. With V GS = 0, there are two back-to-back pn junctions. No drain current flows. LINEA OPEATION. (a.k.a. triode or ohmic operation) A positive gate voltage is applied (V GS > V T ) attracting electrons to the channel region. The MOSFET acts like a voltage-controlled resistance. SATUATION. V DS is sufficiently large to pinch off the chanel at the drain end. The MOSFET acts like a voltage-controlled current source. University of Connecticut 139
MOSFET Threshold Voltage V T With zero body-source bias, the threshold voltage is V QB QOX = φ 2φ C C TO MS F φ MS = metal-semiconductor work function difference 2φ F = voltage across the semiconductor neccesary for inversion Q B = charge in the semiconductor under inversion Q OX = charge in oxide Q II = charge of ion-implanted impurities in the semiconductor If a body-source bias is present, this modifies the threshold voltage: V ( OX OX = V + γ V + 2φ 2φ Q C T TO SB F F II OX ) where the body effect coefficient is γ ε = 2q N A C /A OX University of Connecticut 140
MOSFET Linear Operation The MOSFET acts like a voltage-controlled resistance: 2 VDS I D = K ( VGS VT ) VDS 2 2 2I VDS = ( VGS VT ) ( VGS VT ) K LINEA OPEATION where K is the device transconductance parameter, given by n K = k W = L µ ε ' t OX OX k is the process transconductance parameter. Typically, µ n = 580 cm 2 /Vs. ε OX = 3.45 x 10-13 F/cm. W L D University of Connecticut 141
MOSFET Saturation Operation The MOSFET acts like a voltage-controlled current source: I K = V 2 ( V ) D GS T 2 SATUATION OPEATION where K is the device transconductance parameter, as before. If we include the channel length modulation effect, then I K = V V + V 2 2 ( ) ( 1 λ ) D GS T DS where the channel length modulation parameter λ is typically between 0.01 V -1 and 0.1 V -1. University of Connecticut 142
MOSFET Characteristic Curves I D (ma) 0.16 0.12 0.08 0.04 0.00 0.00 K = 0.05 ma/v 2 V T = 0.6 V 0.40 0.80 1.20 1.60 V DS (V) V GS =3.0V 2.5 2.0 1.5 1.0 2.00 2.40 2.80 CUTOFF MODE. V GS I D V = 0 LINEA MODE. V GS V SATUATION T T I KV V D = DS ( VGS VT ) 2 V V V + V I T GS DS T K = V V + V 2 DS 2 ( ) ( 1 λ ) D GS T DS University of Connecticut 143
SPICE MOSFET Model D VT = VTO + GAMMA( PHI + VSB PHI) C GD D C BD I KP width = 2 length ( 1+ LAMBDAVDS ) ( V V ) 2 D GS T (saturation) G DS I D B 2 width VDS I D = KP ( VGS VT ) VDS length 2 (linear operation) ( 1+ LAMBDAVDS ) C GS S S C BS CGS = width CGSO C GB University of Connecticut 144
NMOS Logic Gates University of Connecticut 145
NMOS Inverter w/ esistive Load: Basic Operation 3.00 2.00 V DD 1.00 0.00 0.00 1.00 2.00 3.00 For < V T, N 0 is cut off and = V DD. For V T < < +V T, N 0 is saturated For > +V T, N 0 is linear and is low University of Connecticut 146
NMOS Inverter w/ esistive Load: Load Line Analysis I D (ma) 0.20 0.16 0.12 LOAD LINE ANALYSIS =3.3V 2.8V V DD = 3.3V 50kΩ K = 50µ A/ V 2 V T = 0.6V 0.08 0.04 0.00 0.00 1.00 2.00 3.00 V DS (V) 2.3V 1.8V 1.3V 0.8V The equation of the load line is I D = Simultaneous solution of the load line and the transistor equations yields the voltage transfer characteristic. University of Connecticut 147
NMOS Inverter w/ esistive Load: VTC Calculation K=50µA/V 2 V T =0.6V V DD =3.3V 50kΩ N O With the MOSFET linear, I D = This is a quadratic in V OL. Thus, With < V T, N O is cut off and therefore V OH = The calculation of V OL is more complicated because the MOSFET is in the linear mode. If V OL is small, then V OL University of Connecticut 148
NMOS Inverter w/ esistive Load: VTC Calculation K = 50µ A/ V 2 V T = 0.6V V DD =3.3V 50kΩ With the MOSFET linear, I D = N O Actually, we can determine V OL by just using the voltage divider rule! This is because a linear-operated MOSFET behaves like a voltage-controlled resistance. Thus, I V D = DS VDS= 0 Using the voltage divider rule, V OL University of Connecticut 149
NMOS Inverter w/ esistive Load: VTC Calculation K = 50µ A/ V 2 V T = 0.6V V DD =3.3V 50kΩ With the MOSFET saturated, = N O For the calculation of V IL, we know that the MOSFET is operated in the saturation region. Thus, dv dv OUT IN V = V IN solving for V IL, V IL = IL = University of Connecticut 150
NMOS Inverter w/ esistive Load: VTC Calculation K = 50µ A/ V 2 V T = 0.6V V DD =3.3V 50kΩ Solving for, = N O For the calculation of V IH, we know that the MOSFET is operated in the linear region. = Solving for V IH, dv dv IN OUT V IN = V IH = V IH = University of Connecticut 151
NMOS Inverter w/ esistive Load: VTC Calculation K = 50µ A/ V 2 V T = 0.6V V DD =3.3V 50kΩ N O Thus, This is a quadratic in V M : The midpoint is defined by VOUT = VIN = VM For the example shown here, Here, the MOSFET is saturated. University of Connecticut 152
NMOS Inverter w/ esistive Load: DC Dissipation K = 50µ A/ V 2 V T = 0.6V V DD =3.3V 50kΩ N O P L = With a high output, no current flows because the load gates draw negligible current. Hence P H = P = University of Connecticut 153
NMOS Inverter w/ esistive Load: Total Dissipation K = 50µ A/ V 2 V T = 0.6V V DD =3.3V 50kΩ N O We just calculated the DC dissipation of this NMOS inverter as 96 µ W. The total dissipation also includes a dynamic component. P = P + P = DC AC Now suppose that the present gate is switched at a rate of 1 MHz with a 1 pf load. Then the dynamic dissipation is P AC = University of Connecticut 154
NMOS Inverter w/ esistive Load: MOSFET Design Suppose that µ n = 550 cm 2 / Vs and t ox = 500 Angstroms. Then the process transconductance parameter is µ nε ox k'= = t ox To obtain a device transconductance parameter equal to 50 µ A/ V 2, we require an aspect ratio equal to W L = University of Connecticut 155
NMOS Inverter w/ esistive Load: esistor Design Integrated circuit resistors are made using diffused or ion-implanted regions of semiconductor which are junction-isolated from other devices. t L = ρ t W = S L W W L where S is the sheet resistance. Typically, the resistor is made using a p-type diffusion with S = 100 Ω / square. Then if we minimize W at 1 µm, then for a 50 kω resistor we require L = University of Connecticut 156