Figure 1. The energy band model of the most important two intrinsic semiconductors, silicon and germanium

Analog Integrated ircuits Fundamental Building Blocks 1. The pn junction The pn junctions are realized by metallurgical connection of two semiconductor materials, one with acceptor or p type doping (excess holes) and another with donor or n type doping (excess electrons). When the p and the n type semiconductors are in each other s vicinity, their behavior changes significantly compared to the behavior of the isolated materials. In order to analyze the operation of the pn junction, one must consider the energy band model of solids, applied to doped semiconductors. The energy band model, drawn for so called intrinsic or pure semiconductors, is shown in Figure 1. Figure 1. The energy band model of the most important two intrinsic semiconductors, silicon and germanium onduction occurs by drift within the crystal lattice when electrons from the valence band acquire sufficient energy for moving into the conduction band. Through this jump between the valence and the conduction band the electrons must overcome the effect of the potential barrier equal to the typical band gap voltage of the material. The probability of the transition for the electrons is given by the Fermi-irac statistical distribution. f ( E) 1 F EE F kt 1 e, (1) where E is a given energy level, E F is the Fermi energy level, k is Boltzmann s constant and T is the absolute temperature. The distribution function gives the probability for an electron to have the E energy level in a crystal at a given temperature T. It also states that at a temperature equal to 0K no electron can be in energy states above the Fermi level. This means that at 0K no conduction occurs in a pure semiconductor where the Fermi level is halfway between the valence and the conduction bands. At higher temperatures a finite number of electrons can acquire sufficient energy for moving into the conduction band and contributing to a small drift current. For doped semiconductors the situation in the energy band model is dramatically changed by the presence of donor and acceptor impurities in the semiconductor crystal lattice. These atoms exhibit free electrons or holes that can be easily pushed into the conduction or valence bands. As a consequence, the Fermi level moves closer to the conduction band for the n type material and closer to the valence band for the p type material. This is shown in Figure. Figure. hanges of the Fermi level caused by acceptor and donor impurities 1

Analog Integrated ircuits Fundamental Building Blocks A pn junction can be obtained by joining together two crystals with complementary doping. At temperatures larger than 0K both materials will feature free carriers in the conduction band (donor electrons) or in the valence band (acceptor holes). harged atoms, essentially ions, will create an internal electric field that drives the free electrons close to the contact surface of the junction to drift and diffuse into the p type material where a hole-electron recombination occurs. The recombination causes a drift current through the surface of the junction. Assuming that the atom is electrically neutral, excess electrons cause the formation of negative ions. Similarly, the lack of electrons left behind in the n type crystal cause the formation of positive ions. The diffusion of the electron through the junction surface happens until the current due to the electric field created by the forming positive and negative ions cancels the drift current induced by the diffusion. When the junction reaches equilibrium, the Fermi energies of the two materials are identical and the diffusion ceases. The junction structure and energy band model in equilibrium are presented in Figure 3. Figure 3. The structure and energy band model of a pn junction in equilibrium When the junction reaches equilibrium, further diffusion is inhibited by the oulomb force between the newly created negative ions and the electrons. Therefore, the region around the junction will contain no free carriers and is considered depleted. The positive and negative ions located in the depletion region create an internal potential difference across the junction, between p and n type materials. This voltage is not accessible from the outside and can not be directly measured. Its presence is associated with the intrinsic concentration of carriers and with the initial difference between the Fermi energies of the two doped semiconductors. The intrinsic potential difference, as a function of the doping concentrations, can be derived from the Fermi-irac distribution. Its expression can be written as follows: N N, () A 0 T ln ni where T =kt/q is the thermal voltage, N and N A are the concentrations of the doping donor and acceptor atoms, while n i is the intrinsic carrier concentration of silicon, equal to 1.45 10 10 cm 3 at 300K. The sustained conduction current through the junction depends on the external biasing voltage applied across the terminals. There are two possible biasing conditions, depending on the sign for this voltage. When it is negative, the junction is reverse biased, when it is positive the junction is forward biased. Reverse biasing By reverse biasing the external voltage emphasizes the intrinsic potential of the junction as illustrated in Figure 4. onsequently, the width of the depletion region increases together with the repelling oulomb force. From energetic point of view this means that the electron must overcome a much larger potential barrier in order to reach the conduction band. At normal temperatures the probability of electrons crossing the larger potential barrier is very small and a conduction does not occur. Forward biasing By forward biasing the applied external voltage decreases or, if sufficiently large, totally overcomes the effect of the intrinsic potential. As a consequence, the width of the depletion region and the potential barrier are also decreased. The acceleration, induced by the ϕ 0 voltage difference, causes a drift and diffusion of the electrons into the p type material. Furthermore, attracted by the positive terminal of the external source, the electrons will not remain steady after a recombination but will jump from hole to hole inducing a

Analog Integrated ircuits Fundamental Building Blocks sustained conduction current. In order not to deplete the n type material of electrons, these are replaced by the negative terminal of the external source. This mechanism closes the circuit and maintains a constant current flow. The conduction through the forward biased pn junction and its energy band model are shown in Figure 5. Figure 4. The structure and energy band model of a reverse biased pn junction Figure 5. The structure and energy band model of a forward biased pn junction A quantitative evaluation of the pn junction behavior is done through an electrostatic analysis. The analysis starts from Poisson s equation, simplified for the full depletion model in order to allow an analytical solution. The full depletion model is based on the assumption that there are no free carriers in the materials around the junction in the depletion region and the concentration of the carriers outside the depletion region is approximately equal to the doping density. This approximation is justified by the exponential variation of the concentration with the Fermi energy according to the Fermi-irac distribution. This means that a small increase of the Fermi energy or the band gap will lead to a significant decrease in the carrier concentration and very few carriers will be able to overcome the potential barrier. The pn junctions approximated with the full depletion model are also called abrupt junction due to the instantaneous transition between the depletion region and the rest of the crystals. The charge density profile allows the derivation of the electric field and the potential across the junction. The obtained curves are shown in Figure 6. The charge carrier concentration is constant both regions according to the full depletion model. The total charge crossing the junction can be written by multiplying the electronic charge q with the total number of carriers. The total number of carriers is equal to N A on the p side and N on the n side of the junction. The coordinates x p and x n represent the limits of the depletion region. The origin is considered to be at the junction boundary. The electric field is found according to Gauss s law written for a single direction perpendicular to the junction boundary. This law states that the gradient of the electric field is equal to the ratio of the charge density ρ to the dielectric constant of the material ε Si. E x q N N Si Si A (3) After integration along the x axis the electric field results: qn qn (4) A E x x Si Si 3

Analog Integrated ircuits Fundamental Building Blocks Figure 6. The charge concentration, the electric field and the potential variation along the pn junction It can be seen that the electric field varies linearly along the x axis. If the boundary condition imposes a zero electric field outside the depletion region, then, for electrical neutrality reasons, the total positive charge is equal to the total negative charge, according to the charge conservation theorem. The electric field reaches its maximum exactly at the junction surface. This value can be obtained by simple geometric calculations which yield E 0 qn x n A p (5) Si qn x Si The calculation of the potential is done by integrating the electric field with respect to the variable x. qn qn E x x x Si A Si (6) This expression shows a parabolic variation of the potential along the x axis. The total potential difference across the depletion region is equal to the difference between the intrinsic potential and the externally applied voltage. qnx qn Ax n p 0 (7) Another useful parameter, determined from the electro statical analysis, is the capacitance associated with the junction, or simply the junction capacitance. For the calculations, the junction is assumed to act as a simple parallel plate capacitor. In this case, the capacitance is simply defined as the ratio of the semiconductor permittivity ε Si to the width of the depletion region w. Si Si j w Si (8) The full depletion approximation allows the determination of the width by calculating the coordinates x p and x n as 4

Analog Integrated ircuits Fundamental Building Blocks x x The width of the depletion region is then p n N Si A 0 N qn N N A Si 0 qn N N A (9) 1 1 w x x Si p n 0 q N A N (10) The resulting junction capacitance is j q SiN AN 1 j 0 N N 1 1 0 A j 0 0 0 (11) where j0 is the capacitance of the unbiased junction ( =0). The variation of the capacitance with the external voltage is given in Figure 7. Figure 7. ariation of the junction capacitance with the bias voltage An important aspect concerning the functionality of the pn junction is the connection between the conduction current and the externally applied bias voltage. The current I can be derived from the carrier concentrations and the diffusion equation. The resulting expression is I I S e nt 1, (1) where I S is the saturation current. The saturation current depends on the diffusion constants of the holes and the electrons, on the carrier concentrations and on the area of the junction surface. More important is the fact that the saturation current is proportional to T 3 /e 1/T. Therefore, I S is a strong function of temperature. The typical order of magnitude for the saturation current is 1fA.. The bipolar junction transistor (BJT) Bipolar transistors are obtained by connecting two pn junctions back to back. They are three terminal devices (four terminal if substrate is also considered), typically controlled by a current. The terminals that connect the three distinct regions of the device to the outside world are called emitter, base and collector. If the thin middle layer, associated with the base terminal and built of either p or n type doped semiconductor, is common to both junctions, the structure will exhibit an interesting behavior that allows the transistors to be used as amplifiers or switches. 5

Analog Integrated ircuits Fundamental Building Blocks.1. Principles of operation For a functional analysis of the bipolar transistor one can resume to the npn case. The operation of the pnp device is identical, but all voltages and currents will be negative. The structure and the energy band model of an unbiased npn transistor are given in Figure 8. Figure 8. The structure and the energy band model of an unbiased npn bipolar transistor From the figure it can be seen that the depletion region is formed around both junctions. At equilibrium the Fermi energy is equal to all the three layers. Now consider that the base collector (B) junction is reverse biased. The minority carriers in the base region, electrons in this case, originating from the emitter by recombination, are forced to jump from hole to hole attracted by the positive potential applied to the collector. Meanwhile, the reverse bias of the junction raises the B potential barrier and prevents the majority electrons from the collector to diffuse into the base. The result is a sustained migration of the electrons from the base toward the collector. The intensity of the induced current depends only on the electron concentration in the base. This leads to the idea that the current can be increased by lowering the potential barrier between the base and the emitter with a positive bias voltage. The structure and the energy band model of a correctly biased npn transistor is illustrated in Figure 9. Figure 9. The structure and the energy band model of a correctly biased npn bipolar transistor It can be seen that the width of the depletion region between the base and the emitter has become small, while the depletion region around the B junction has been significantly increased. The forward bias of the BE junction facilitates a high concentration of electrons in the base that can contribute to a significant current flow between the emitter and the collector. Practical values of the BE voltage for silicon transistors vary between 0.5 and 1, depending on the doping concentrations and on the parameters of the fabrication process. An effect observed in bipolar transistors is that not all the electrons from the base reach the collector. Some of the minority carriers are attracted by the positive base terminal voltage, causing a current flow in the base. Usually the number of electrons lost in the base is around 1% of all the electrons reaching the collector. Figure 10 shows the conduction mechanisms of the bipolar transistor, considering the migration of the electrons between the emitter, base and collector. Note that the arrows mark the movement of the electrons while dashed arrows show the currents flowing through the device. Since current flow is associated with the movement of holes, electron migration and currents have opposite senses. This aspect is very important in circuit design for establishing proper biasing conditions. Usually it is easier to consider the transistor with the classical signing convention, used for passive circuit analysis. This convention states that the sense of the current through a circuit branch is always opposite to the movement of the electrons. 6

Analog Integrated ircuits Fundamental Building Blocks Figure 10. urrent conduction in a npn bipolar transistor Another information is that the B voltage does not affect the current flowing through the transistor, unless it is large enough to produce the punch through of the B junction. The break down voltage of the junction is usually in the range of tens of (except some cases like in Zener diodes). In practical circuits the biasing conditions are set by the BE and E voltages as shown in Figure 11. Figure 11. Bipolar transistor biasing npn and pnp cases The equations that describe the connection between the currents and voltages are I E I B I I IB E BE B, (13) where β is the current gain of the transistor. The typical value of β is around 100, corresponding to the estimated 1% electron loss in the base terminal. The equations above are valid, regardless of the transistor type (npn or pnp)... BJT fabrication - a simplified description Real processes for integrated circuit fabrication are much too complex to be described here in detail. This section only discusses the most important structural aspects of physical bipolar transistors, that define the principles of operation. Similarly, the presentation is resumed to more commonly used vertical npn transistors. In modern MOS or BiMOS processes lateral pnp transistors may be available but their performance is inferior to their vertical npn counterparts. In the description of the fabrication steps the sign marks a lightly doped material (low impurity concentration) while the + sign marks high doping concentrations. The starting point of the fabrication process is the substrate. The substrate is in many cases a lightly doped p type material. The next step implies the realization of a collector implant made of heavily doped n + type material and the growth of an epitaxial n layer. This way the n + implant will be buried between the substrate and the epitaxial layer. These steps are shown in Figure 1. The figure shows the section view and the top layout view of the device. The n epitaxial deposition is followed by the p + implantation. This includes the base region and the trench isolation between two adjacent transistors. Alternatively, in some processes the trench can be etched into the substrate and filled with isolator in order to separate adjacent devices. The isolation can be seen as a three dimensional ring around the transistor. Figure 13 shows the cross section and the layout view of the device after the p + implantation. 7

Analog Integrated ircuits Fundamental Building Blocks Figure 1. Realization of the n + buried implant and the n epitaxial layer on the p substrate Figure 13. Realization of the p + implants of the base and the trench isolation Next the n + implant is repeated for the realization of the collector contact and the emitter as shown in Figure 14. The final steps imply the realization of the metal (alternatively low resistivity silicide or salicide) contacts for the terminals and the deposition of a SiO surface isolation of the transistor that separates the device from possible metal wirings on the integrated circuit. The finished transistor is presented in Figure 15. Figure 14. Realization of the n + collector contact and emitter region.3. The large signal model of the bipolar transistor The large signal model gives the equations that describe the operation of the transistor and the dependence between the currents and voltages in the two pn junctions. The analysis is based on the carrier concentration in the different regions of the transistor. The analysis also assumes that the transistor has been correctly biased. Figure 16 gives the minority carrier concentration in the base. 8

Analog Integrated ircuits Fundamental Building Blocks Figure 15. The finished transistor with contacts and surface isolation Figure 16. The carrier concentrations in the base of the npn transistor The minority carrier concentration in the base on the emitter side, n p (0), depends on the junction crossing probability of the majority electrons from the emitter. This probability is a function of the mobile carrier concentration in the emitter and is proportional with the exponential of the base-emitter biasing voltage. p p0 BE T n (0) n e, (14) where n p0 is the concentration of the electrons in the emitter with n type doping. The carrier concentration on the collector side may be written assuming that no majority electron from the collector can cross the junction into the base due to the potential barrier of the reverse biased junction. Therefore, at the limit of the depletion region only acceptor atoms exist in the base and the electron concentration is n p (W B )=0. If the recombination rate in the base is low, the minority electron concentration changes linearly along the base width. BE x T np ( x) np0e 1 WB (15) The conservation of charges requires the number of remaining acceptor atoms in the base after recombination, N A, to be constant and equal to the difference between the number of holes p p (x) and the number of recombining electrons n p (x). N p ( x) n ( x) (16) A p p The collector current is produced by the minority electrons diffusing in the direction of the collector along the concentration gradient. The current density due to diffusion is obtained by multiplying the electronic charge q with the concentration gradient and the diffusion constant n of the electrons in silicon. 9

Analog Integrated ircuits Fundamental Building Blocks J n dn ( ) p x qn (17) dx The derivative can be easily found as the slope of the linear concentration function n p (x). dnp ( x) np (0) (18) dx W The expression of the collector current is found by multiplying the current density with the cross sectional area of the emitter A. B By convention, if p qann p0 T BE n (0) I A J n qan e W W (19) B B I S qa n n p0, (0) W B then the collector current becomes S BE T I I e (1) The corresponding large signal model is shown in Figure 17. Figure 17. The large signal model of a bipolar transistor It can be seen that the forward biased base-emitter junction is modeled with a diode. The base-collector junction is modeled as a current controlled current source. The output current of this source depends on the base current through the current gain β. The Early effect The large signal model is not very often used for design purposes but it is important for the explanation of the transistor operation. It is correct in this form only if the effective width of the base is considered constant and independent on the transistor bias. In this case it is true that the collector current is independent of the collector-emitter voltage. In reality the collector-emitter voltage modulates the width of the depletion region around the base-collector junction. Therefore, also the effective width of the base is varied. Increasing the E voltage leads to an increase of the potential barrier and the widening of the B depletion region. In the mean time, the slope of the carrier concentration function n p (x) increases together with the collector current due to the zero concentration boundary condition on the collector side of the base. This phenomenon, called Early effect (or base width modulation), is shown in Figure 18. The derivation of the correction term for the current, that also considers the base width modulation, is done under the assumption that the base width is a function of the E voltage. Typically, the effective width of the base will decrease width the larger collector emitter voltage, as the depletion region around the basecollector junction widens. Therefore, a Δ E variation of the voltage will produce a ΔW B variation of the effective base width and implicitly a ΔI change of the collector current. 10

Analog Integrated ircuits Fundamental Building Blocks Figure 18. The effect of the E voltage on the charge concentration in the base The ideal collector current is written: I B BE n p0 T qa n e W () E The differentiation of the collector current with respect to the E voltage leads to BE qann p0 W T B I WB e E B E E B E I W W, (3) where the term E WB WB EA (4) is the Early voltage. The error term of the collector current caused by the E voltage is then I I I E E E EA (5) The collector current results: BE BE BE * T T E T S S S EA I I I I e I e I e 1 E EA (6) It can be seen that, if the base-emitter voltage is fixed, the variation of the collector current with the collector-emitter voltage is linear. The dependence of the collector current on the bias voltages is valid only if E is sufficiently large and the transistor is biased in the forward active region. In these conditions the device behaves as a current controlled current source and can be efficiently used for amplification. The bipolar transistor in saturation In saturation both junctions are forward biased. As a consequence, the base region receives electrons from both the emitter and the collector. The carrier concentration for the saturated operation is shown in Figure 19. ue to the charge injection occurring through both, base-emitter and base-collector junctions, the collector current is no longer βi B. Since the carrier concentration in the base is much larger in saturation than in the forward active region, the saturation condition is written: I I B (7) 11

Analog Integrated ircuits Fundamental Building Blocks Figure 19. arrier concentrations in a saturated bipolar transistor In practice, if the unconditional operation of the transistor in the forward active region (as an amplifier) is desired, the saturation must be avoided by keeping the collector-emitter voltage higher than BE. If BE > E, according to the equation (13) the difference between these voltages will forward bias the basecollector diode. onsequently, the potential barrier around the base-collector junction is lowered and conduction may occur from the collector toward the base. The higher the difference, the larger the conduction current. Practically both the collector and the emitter inject mobile carriers into the base. These carriers will be extracted through the positive terminal of the BE voltage source. It results that, the current flowing into the base will be larger than a fraction of the collector current, which explains the saturation condition. In saturation the impedance levels looking into both the collector and the emitter are low, recommending the use of the transistor as a switch. The junction voltages become independent on each other. BE is the voltage across the base-emitter diode, changing in the range between 0.5 and 1, while E is approximately constant and held at around 0...4. The small signal model of the bipolar transistor The small signal model can be derived from the large signal model by considering infinitely small variations of the currents and voltages around the operating point of the transistor. Therefore, the base-emitter diode is transformed into a resistance, while the current controlled current source is replaced by a voltage controlled current source and an equivalent parallel resistance. The small signal low frequency model and the typical parameters are presented in Figure 0. Figure 0. The small signal low frequency model of the bipolar transistor The derivation of the small signal base-emitter resistance r BE, collector-emitter resistance r E and the transconductance g m is done by considering the dependence of the collector current on the biasing voltages. This dependence has been defined in the equation (6) and is repeated here for convenience: BE T I IS e 1 E EA (8) The collector-emitter resistance (r E ) is defined as the variation of the E voltage caused by an infinitely small variation of the collector current. Its expression can is obtained as follows: r E E 1 1 BE I I I I S T e E EA EA (9) 1

Analog Integrated ircuits Fundamental Building Blocks Typical values of the r E resistance are in the range of hundreds of kω. The small signal transconductance (g m ) is defined as the variation of the base-emitter voltage caused by an infinitely small variation of the collector current. Typical values of g m are in the range of ms. BE I 1 I T gm IS 1 e E BE EA T T (30) The base-emitter resistance (r BE or r π ) is calculated as the derivative of the base emitter voltage with respect to the base current. r BE BE 1 1 I I B 1 I B BE BE g m (31) The output characteristic of the transistor describes the dependence of the collector current I on the collector emitter voltage. This characteristic can be regarded as a family of curves corresponding to different base-emitter voltages. With the increase of BE each collector-emitter voltage will produce a larger current through the transistor. The output characteristic family is shown in Figure 1. The slope of the curves in the forward active region (FAR), calculated around the operating point of the transistor, is equal to the small signal r E resistance. Figure 1. The output characteristics of the bipolar transistor The transfer characteristic gives the dependence of the collector current on the base-emitter voltage, according to the relatively steep exponential function of equation (8), as illustrated in Figure. Figure. The transfer characteristics of the bipolar transistor The small signal transconductance g m of the device is given by the slope of the curve calculated for an infinitely small segment around the operating point..5. The small signal and high frequency model of the bipolar transistor The small signal and high frequency model, given in Figure 3, describes the frequency dependence of the parameters. Therefore, it includes sheet resistances of the materials and parasitic capacitances. 13

Analog Integrated ircuits Fundamental Building Blocks Figure 3. The small signal and high frequency model of the bipolar transistor The elements of the model are as follows: r B, r E and r are the equivalent sheet resistances of the base, emitter and collector; the capacitance S is the collector-substrate capacitance formed due to the depletion region at the boundary between the n type collector and the p type substrate. This capacitance is a junction capacitance whose expression has been defined in the equation (11). S S 0 1 S S 0, (3) where S0 depends on the carrier concentration (doping density) of the substrate and the collector S 0 q SiN AN N N A S 0 (33) the capacitance B is a depletion capacitance associated with the base-collector junction. Its expression is: B B 0 1 B B 0 (34) the capacitance BE can be considered as a sum of two separate components. One is the effect of the base-emitter junction depletion region, while the other is caused by the charge carrier diffusion in the base as a result of the changing BE voltage. (35) BE BEdep BEdiff The diffusion component of the base-emitter capacitance may be written as Q Q I g B B BEdiff F m BE I BE (36) The transit time of the base, τ F, is defined as a function of the base width W B and the diffusion coefficient of the electrons n : The final expression of the base-emitter diffusion capacitance is then WB F (37) n 14

Analog Integrated ircuits Fundamental Building Blocks gmwb (38) BE diff An important parameter, that is specified by the semiconductor foundry, is the cutoff frequency of the transistor. The cutoff frequency is defined at the intercept of the current gain β(s) with the frequency axis. Its value is calculated from the small signal and high frequency model of the transistor, whose emitter is grounded. In this case the transfer function of the transistor is defined as follows: n i ( s) (39) i In the calculations the sheet resistances and the collector-substrate capacitance are ignored. The high frequency model from Figure 3 is transformed as follows: B Figure 4. The simplified small signal and high frequency model of the bipolar transistor The current gain is calculated for a shorted collector-emitter junction. In this case the r E resistance acts as an interruption and it can be ignored together with the Early effect. The base-collector capacitance is transformed into a capacitance to the ground connected in parallel with BE. The small signal model can be redrawn: Figure 5. The small signal and high frequency model of the bipolar transistor used in the cutoff frequency calculation The network can be solved for β(s) by writing the following set of equations: i gmvbe 1 1 vbe ib r BE sbe sb (40) The transfer function results: gmrbe 0 ( s) 1 s r 1 s r BE BE B BE BE B (41) The cutoff frequency is then f T gm BE B (4) 15

Analog Integrated ircuits Fundamental Building Blocks The corresponding magnitude response of the transistor is given in Figure 6. Figure 6. The frequency dependence of the current gain β It is of importance that the cutoff frequency indirectly depends on the collector current and on temperature through the transconductance. The cutoff frequency of the transistors should be maximized depending on the frequency range of the circuit where the device is used. The optimization is done by adjusting the collector current and subsequently the operating point of the transistor. Table 1 gives a summary of the bipolar transistor parameters and their expression often used in practical designs. Parameter Expression collector current I BE T I ISe 1 small signal transconductance g m I gm current gain β rbe gm base-emitter resistance r BE rbe g collector-emitter resistance r E base-emitter capacitance BE base-collector capacitance B cut-off frequency f T BE f T B r E I T m EA E EA BE0 m B 1 BE BE0 g W B 0 1 B B 0 gm Table 1. Summary of the bipolar transistor parameters and their expressions 3. Enhancement MOS transistors Metal-oxide-semiconductor (MOS) transistors are becoming the predominant components in modern semiconductor technologies. The fabrication steps are based on the same procedures as in the case of bipolar transistors, namely oxidation, diffusion, ion implantation, epitaxial deposition and etching. Although the steps of fabrication are similar, the technologies differentiate according to the type of material used as a substrate. The structures of a p-channel and an n-channel transistor are shown in Figure 7. Notice the geometrical parameters (W is the channel width and L is the channel length) of the devices. BE B n 16

Analog Integrated ircuits Fundamental Building Blocks Figure 7. The structure of a PMOS and of an NMOS transistor built in n-well technology on a p- substrate The p-channel transistor is separated from the p- substrate by an n-type material called n-well. The PMOS transistor, that resides in the well, tends to have inferior characteristics compared to the NMOS transistor positioned on the native substrate. A p-well technology, where the n-channel transistors is separated from the substrate by a p type material, is preferred in the cases when PMOS and NMOS transistors need to have more balanced characteristics. Balanced characteristics means that threshold voltages, the current gain, the switching time and the frequency behavior of PMOS and NMOS devices are similar. Usually a p-well process offers higher quality PMOS transistors than an equivalent n-well process. There are more balanced processes that are meant to eliminate the imbalance of the characteristics. Typical examples in this sense are twin-well (independent optimization of threshold voltages, body effect and gain for PMOS and NMOS devices) and silicon on insulator (SOI) processes. 3.1. Fabrication of MOS transistors The described fabrication process is meant to give an overview on the realization of the most important structures that define the functionality of the transistor. A real process includes many additional steps, but these are omitted here for simplicity. The process starts from a lightly doped p substrate, similar with the case of bipolar transistors. The next step is to define the trench isolation between adjacent devices. This procedure implies insulator (SiO ) depositions on the desired areas of the substrate as shown in Figure 8 Figure 8. eposition of the isolator in the separation regions of adjacent transistors Next the gate oxidation is performed. A 100A to 300A thin oxide layer is deposited evenly on the entire surface of the wafer. The oxide is then etched in the regions where the substrate is prepared for implanting the drain and the source diffusions. The poly-silicon gate contact is defined in a consequent maskingpatterning process, similar to the one used to create the trench isolation. The resulting cross section is presented in Figure 9. In the following step the uncovered substrate is heavily doped with donor (n + ) impurities. The depth of the implant is in the μm range. The gate poly silicon is separated from the future metal contacts by a short circuit protection layer, called oxide-spacer, that completely covers the gate area. The final step of the fabrication process is the definition of the metal contacts that give external access to the drain and the source terminals of the transistor. The cross section of the NMOS transistor is shown in Figure 30. 17

Analog Integrated ircuits Fundamental Building Blocks Figure 9. eposition of the gate oxide, of the gate poly-silicon and the preparation of the drain-source regions for implantation Figure 30. Implantation of the drain and of the source and the metal contacts The bulk (substrate) contact of the n-channel devices are realized by implanting acceptor (p + ) impurities into the substrate prior to the definition of the metal contacts. The bulk connection becomes important when parasitic effects (latch-up) are considered. 3.. Operation of a physical MOSFET The functionality of the physical MOSFET is based on the characteristics of the pn junction. When the terminals of the transistor are not biased, a depletion layer is formed at the boundaries between the heavily doped drain-source regions and the substrate or well. Figure 31 shows the functional structure of an unbiased NMOS transistor and the depletion regions around the substrate-drain and substrate-source pn junctions. At this stage neither of the equivalent diodes are biased and there is no current flowing through the device. Figure 31. The structure of an unbiased NMOS transistor When the gate is biased with a positive voltage, the minority electrons from the p substrate are attracted by the gate. If the bias voltage applied to the gate is smaller than a threshold voltage, the depletion region is extended under the gate due to the recombination of the minority electrons with the holes in the substrate. This is shown in Figure 3. If the gate voltage is increased above the threshold voltage, the p substrate region under the gate accumulates a sufficiently large number of electrons and an inversion layer, called channel, is formed between the drain and the source. The material in the inversion layer is of type n due to the excess electrons. The electrons are majority carriers compared to the bipolar NPN transistors where the conduction has been insured by minority electrons. The structure of the transistor with an induced channel is shown in Figure 33. Once the channel has been created, a drain-source voltage is needed to accelerate the electrons along the inversion layer from the source toward the drain. The current is maintained through injecting electrons 18

Analog Integrated ircuits Fundamental Building Blocks into the channel on the source side and extracting them at the drain terminal. It is important to notice that a positive drain-source voltage causes the drain-substrate (bulk) junction to be reversely biased. As a consequence, the depletion region is widened around the drain diffusion. It results that the channel will be asymmetrical, its depth decreasing at the drain side proportionally with the applied S voltage. The asymmetrical channel is shown in Figure 34. Figure 3. The extension of the depletion region under the gate due to recombination Figure 33. The structure of the NMOS transistor with an induced channel Figure 34. The channel asymmetry caused by the drain-source voltage If the increasing drain-source voltage equals a saturation threshold, Ssat, a pinch-off point appears at the drain diffusion, as shown in Figure 35. Figure 35. The channel asymmetry caused by the drain-source voltage The pinch-off region increases proportionally with the applied drain-source voltage and the effective length of the channel is reduced. The electrons arriving from the source are accelerated by the strong electric field and are eventually eliminated from the device through the drain terminal. 19

Analog Integrated ircuits Fundamental Building Blocks The form of the channel defines the operating region of the transistor. As long as GS < Th, no channel is created and the transistor works in the cut-off region where no conduction occurs. When GS > Th the inversion layer is created. If the condition 0< S < Ssat is fulfilled, the device can be regarded as a simple ohmic contact between the drain and the source, whose resistance is modulated by the gate-source voltage. In this case the transistors is biased in the linear or triode region. When the S voltage is greater or equal to Ssat, the pinch-off appears and the device is saturated. The operating regions are summarized in the following table depending on the bias voltages. Operating region GS S hannel cut-off < Th does not matter unless breakdown no triode (linear) > Th 0< S < sat yes, no pinch-off saturation > Th S > sat yes, pinch-off Table. MOS transistor operating region summary 3.3. The large signal linear model in the triode region The linear region assumes a biasing condition with a small drain-source voltage. As shown in the previous paragraph, the MOS transistor can be approximated with a voltage controlled resistor, whose resistance is modulated by the gate-source voltage. According to the definition, the drain current of the transistor can be expressed as the ratio of the total charge in the inversion layer and the time required by the carriers to drift from the source to the drain. It results: I Q A Q W L t t u u, (43) tr tr where Q u is the charge per unit area, A=W L is the total area of the channel and t tr is the transit time of the space between the drain and the source. The drift velocity can be expressed as a function of the carrier mobility µ n and the accelerating electric field E. v drift E (44) n Generally, the electric field is equal to the ratio of the voltage that creates the field to the distance between the points where the voltage is applied. In the case of the MOS transistor, the drain-source voltage creates the electric field, while the distance between the two terminals is the channel length. It follows that S E (45) L By replacing the equations (44) and (45) in (43) the expression of the current becomes W I QuW ne Qu ns (46) L Finally, the charge per unit area can be written as a function of the capacitance per unit area and the overdrive voltage of the transistor u ox od ox GS Th Q, (47) where the overdrive voltage is the amount with which the gate-source voltage, GS exceeds the threshold voltage, Th. The expression of the current becomes 0

Analog Integrated ircuits Fundamental Building Blocks W I L S GS Th n ox GS Th S (48) Note that the expression of the current is only valid if the drain-source voltage is much smaller than the overdrive voltage. This condition insures an approximately even charge distribution along the channel (ohmic contact through the inversion layer) and a constant drift velocity of the carriers. 3.4. The large signal quadratic model in the triode region The quadratic large signal model is derived similarly as the previously discussed linear model, but it considers that the charge distribution along the channel is not even due to the increased depletion region around the drain and to the channel asymmetry. The current is again confined to the boundary layer of the inverted substrate under the gate. In calculations it is considered that the charge density varies along the x axes as a consequence of the widened depletion region. Figure 36. ariation of the charge density along the x axes (along the channel) due to the depletion region asymmetry The potential difference between the source terminal (taken as reference) and a particular section of the channel will vary with respect to the distance from the source diffusion. This assumption introduces another variable into the expression of the charge per unit area. ( ) Qu x ox od x ox GS Th x (49) The voltage drop along the channel introduced by the charge density gradient is d I dr (50) The variation of the channel resistance can be written as a function of the sheet resistivity, ρ s. dx dr s, (51) W where The voltage drop on the dx section of the channel is then 1 s Q ( x) (5) n u 1 dx d I Q ( x) W (53) n u 1

Analog Integrated ircuits Fundamental Building Blocks By rearranging the terms it results: n u I dx WQ x d (54) The expression of the current can be determined by integrating the equation (54) along the channel: L S n u 0 0 (55) I dx WQ x d After replacing the expression of Q u (x) as given in equation (49), the expression of the drain current becomes: noxw S I GS Th S L S GS Th (56) 3.5. The large signal model in saturation The large signal model in saturation still assumes that the charge distribution along the channel is not even, but varies instead with the distance from the source. Therefore, the quadratic equation (56), derived for the triode region still applies. From this equation it can be noticed that, once the channel has been established by a constant GS voltage, the current will exhibit a parabolic variation with the drain-source voltage as illustrated in Figure 37. The variation is presented as a family of curves (output characteristics) due to the influence of the gate-source voltage on the channel characteristics. Figure 37. ariation of the drain current with the S and GS voltages It is of importance that the current decreases for high S values. The inflection point of the drain current function, corresponding to a given gate-source voltage, can be found by derivation as follows: I S W L 0 n ox GS Th S (57) The maximum current is achieved for a drain source voltage S = GS Th. If the condition S GS Th Sat (58) is fulfilled, the charge in the inversion layer at the drain side is zero due to the pinch-off so the current can not further obey equation (56). At this stage the inversion layer at the drain side has been reverted to its original p characteristics. The reversely biased drain-substrate diode does not allow the current to flow through the junction. This way the carriers in the drain-substrate junction cannot contribute to the conduction current

Analog Integrated ircuits Fundamental Building Blocks through the device. In this case, the current through the transistor is only modulated by the charge density on the source side. For a given GS voltage this charge density is approximately constant and independent on the potential difference between the drain and the source. Furthermore, its value will stay constant at whatever value has been achieved at the moment when S has equaled GS Th. It results that the expression of the current for the saturation region becomes noxw I GS Th (59) L An important aspect regarding the expression of the drain current in saturation is that the length of the channel has been considered constant and equal to the drawn length, L (the current remains constant once the pinch-off point has been created). However, in reality this assumption is not true since the drain-substrate depletion region increases for larger S voltages. This means that the effective channel length will decrease proportionally with the same voltage. As a consequence, the drawn channel length in the equation (59) must be replaced with the effective length. noxw I GS Th (60) L eff Notice that there is an intrinsic dependence of the current on the drain-source voltage through L eff. In order to describe this dependence the effective length is written as the difference between the drawn length and the size of the pinch-off region: eff pinch S The variation of the current with the S voltage is then L L X (61) I I X I X X L pinch pinch S pinch S eff S I, (6) where X L eff pinch S (63) is the channel length modulation parameter. The corrected expression of the current can be written: I W I I I I 1 * n ox S S GS Th S S L (64) Additionally, the drain current also depends on the substrate-source voltage by means of the threshold voltage. The variation of the threshold voltage with BS can be characterized through an empirically developed equation: 0, (65) Th BS Th F BS F where BS is the bulk-source voltage, Th0 is the threshold voltage for BS =0, γ is the bulk threshold parameter measured in -0.5 and ϕ F is the strong inversion surface potential. The equations developed in this paragraph for the NMOS transistor are equally valid for the PMOS transistor, with the observation that the negative signs of different voltages must be considered for the appropriate biasing. 3

Analog Integrated ircuits Fundamental Building Blocks 3.6. Short channel effects in MOS transistors The operation of the MOS transistor, as described above, is only valid in this form when the channel is considered relatively long. As the distance between the drain and the source decreases, the reduction of the effective channel length becomes increasingly important. In these cases the performances of the transistor suffer due to the so called short channel effects. Among the most important phenomena observed in short channel transistors are the drain induced barrier lowering, the surface scattering, the velocity saturation, the impact ionization and the hot electron effect. The quantitative analysis of these effects is rather complex and will not be discussed here in detail. rain induced barrier lowering The mobile carriers in the channel must overcome a potential barrier that inhibits their flow. The potential barrier is determined by the electric fields generated by both the GS and the S voltages. If the drainsource voltage is increased, the carriers are accelerated and the potential barrier is decreased. This effect is called drain induced barrier lowering. The consequence of the potential barrier decrease is that a current may flow between the source and the drain when the transistor is biased in the cut-off region ( GS < Th ). This results in a subthreshold or weak inversion operation. If the channel is not formed, the structure of the MOS transistor resembles a bipolar transistor. Therefore, the subthreshold current will exhibit an exponential dependence on the gate-source voltage. When the S voltage is heavily increased the depletion region formed around the drain may reach the source. This effect is emphasized by the small channel length and can lead to a virtual short circuit between the drain and the source (also called punch through). The risks of the punch through can be lowered by increasing the capacitance per unit area ( ox ) and the substrate doping concentration. Surface scattering The scattering of the carriers on the surface of the gate occurs when the three-dimensional geometry of the transistor increases the component of the electric field that is perpendicular to the carrier movement. This is illustrated in Figure 38. Figure 38. The components of the electric field in the three-dimensional MOS transistor structure The component E x accelerates the carriers along the channel, while E y causes a drift toward the gate. A collision with the surface of the gate reduces the carrier mobility and consequently the transconductance of the transistor. elocity saturation It has been previously stated that the drift velocity of the carriers, v drift, linearly depends on the mobility and on the accelerating electric field. In reality, this is true only for relatively low electric field values (below approximately 104/cm). If the field increases above this limit, the drift velocity tends to stabilize at a critical saturation value approximately equal to 107cm/s. Similarly as the surface scattering, the velocity saturation increases the drift time and causes mobility degradation. Impact ionization High longitudinal electric fields in the channel may be able to accelerate electrons sufficiently for an ionization of the atoms at impact with the silicon lattice. Since most of the electrons are attracted by the drain, electron-hole pairs are created in the depletion region around the drain diffusion. The holes, origina- 4

Analog Integrated ircuits Fundamental Building Blocks ting from the places previously disclosed by the electrons, are propagated in the channel by the electric field. The substrate between the drain and the source can act as the base of a bipolar transistor while the collector and the emitter is replaced by the drain and the source. If the hole current induced by the impact ionization creates a voltage drop of around 0.6 on the source-substrate diode, the pn junction enters into conduction state and injects an electron current from the source into the substrate. These electrons may be accelerated toward the drain, further increasing the electron-hole pair recombination at the impact with the lattice. The situation worsens when the electrons escape from the field created by the drain and are attracted by other devices residing on the same substrate. This creates leakage and facilitates latch-up. Hot electron effects Hot electron effects occur when highly accelerated electrons trespass the boundary into the gate isolation oxide. They can be trapped there causing an oxide charge accumulation. The oxide charge is accumulated in time and degrades the performances of the transistor similarly as impact ionization. The degradation is permanent due to the damaged gate oxide. 3.7. Substrate biasing and latch-up In the previous paragraphs only the biasing of the gate, source and drain terminals has been discussed, in connection with the functionality of the physical device. The biasing requirements of the fourth, substratebulk (B) terminal can be determined from the necessity to avoid the latch-up phenomenon that is typically associated with MOS circuits. In order to understand how latch-up occurs, let us consider a complementary PMOS-NMOS transistor pair, situated in each other s vicinity on the substrate and created in a common n- well fabrication process. The two parasitic bipolar transistors, together with the sheet resistances of the substrate and of the n- well implant, form an equivalent positive feedback circuit called thyristor or silicon controlled rectifier (SR). If one of the transistors is forced into conduction by an current or voltage change at its base, the positive feedback quickly drives the circuit to become a virtual short circuit between the terminals S p and S n. The SR can be fired up by either of the two bulk terminals. Once conduction has occurred, it is maintained by the positive feedback mechanism, regardless of the further bulk voltage variations. This phenomenon is called latch-up. The only way to bring the structure out of the latch-up mode is to sufficiently decrease the S p S n voltage. Figure 39. Parasitic components of a complementary PMOS-NMOS pair sitting on the same substrate in a n-well process Figure 40. The equivalent parasitic SR formed by the pn junctions and the sheet resistances of the materials The latch-up effect can be very serious in MOS circuits where S p is usually connected to or to a near- voltage, while S n is connected to lower voltages or the ground. A latch-up may create a virtual short circuit between the positive and the negative supply rails. 5

Analog Integrated ircuits Fundamental Building Blocks For the prevention of an eventual latch-up, the voltages at the bulk connections, responsible for the conduction of the parasitic transistors, must be precisely controlled. Practically, the sheet resistances must be shorted in order to avoid a voltage drop that could bring the transistors into conduction. This means that the bulk terminals are always tied either to the lowest possible potential (the negative rail) in the case of the NMOS transistors and the highest possible potential (positive rail) for the PMOS transistors. These connections must be done regardless of the potential at the source terminals. 3.8. The small signal MOS transistor model in saturation The small signal model of a MOS transistor in saturation is similar to the small signal model of the bipolar transistor biased in the forward active region. There are two main differences compared to the bipolar transistor. The first difference is the infinitely large gate-source resistance that replaces r BE. The second is the contribution of the substrate-source junction to the conduction process. The effect of the bulk-source voltage on the drain current is modeled by an additional voltage controlled current source, whose transfer ratio is the bulk transconductance g mb. Usually the bulk transconductance is much smaller that the transconductance of the transistor and in many cases can be neglected in hand calculations. The small signal low frequency model in saturation is shown in Figure 41. Figure 41. The small signal low frequency model of a MOS transistor biased in saturation The parameters of the small signal model can be determined in a similar manner as for the bipolar transistor. The small signal transconductance is defined as the variation of the drain current caused by an infinitely small change of the gate-source voltage around the chosen operating point. I oxw I gm GS Th 1 S L GS GS Th (66) Another often used approximation of the transconductance is: g m LI (67) W ox Typical values of the transconductance are in the range of hundreds of µs. The bulk or substrate transconductance is defined as the variation of the drain current caused by an infinitely small variation of the bulk-source voltage. The drain current indirectly depends on the bulk-source voltage through the threshold voltage whose expression has been given in the equation (65). The bulk transconductance results: g mb I I Th Th gm gm BS Th BS BS BS F (68) All the parameters in this equation have been previously defined in the expression of the threshold voltage as a function of BS. The multiplication factor of the small signal transconductance is typically an order of magnitude smaller than unity. onsequently, the substrate transconductance value is typically a fraction of the small signal transconductance The drain source resistance is defined as the variation of the drain-source voltage caused by an infinitely small variation of the drain current around the bias point. Its expression may be written 6

Analog Integrated ircuits Fundamental Building Blocks r S S 1 1 S 1 I I sat I I S sat (69) Similarly as for the bipolar transistor, the drain-source resistance will have values in the range of tenshundreds of kω, but it tends to be smaller than the collector-emitter resistance for the same bias current. 3.9. Parasitic capacitances in MOS transistors A representation of all the capacitances introduced by the physical structure is given in Figure 4 Figure 4. Parasitic capacitances of a MOS transistor introduced by the physical structure The capacitances emphasized on the figure have the following significance: OLS and OL are the source and drain overlap capacitances created by the overlapping of the gate with the source and drain diffusions; jbs, jb and jbch are the bulk-source, bulk-drain and bulk-channel junction capacitances; ch is the channel capacitance. All these capacitances contribute to the parasitics to some extent, depending on the operating region of the transistor. Junction capacitances jbs BS 0 B0 jb 1 BS BS 0 ; 1 B B0 (70) In these equations BS0 and B0 depend on the doping concentration, while ϕ BS0 and ϕ B0 are the intrinsic surface potentials of the junctions. The bulk-channel depletion capacitance depends on BS similarly as jbs and jb do on BS and B. Overlap capacitances The overlap capacitances are approximated with the expression of a planar capacitor whose value is calculated by multiplying the capacitance per unit are with the total area of the plates. Therefore, OLS OL W LOLox, (71) where L OL is the overlap length. In the expression of the overlap capacitances it has been assumed that the diffusions and the overlap regions are equal on the source and on the drain sides of the transistor. The channel capacitance The expression of the channel capacitance depends on the operating region due to the dependence of the channel charge on the drain current and the bias voltages. onsequently, the channel capacitance must be individually determined for each of the biasing conditions. 7

Analog Integrated ircuits Fundamental Building Blocks 3.10. The small signal and high frequency model in saturation The small signal and high frequency model in saturation is illustrated in Figure 43. Figure 43. The small signal and high frequency model of a MOS transistor in saturation The capacitances associated with the high frequency model in saturation are: W L BS jbs jbch B jb GS OLS ch G OL OL ox (7) The channel capacitance can be determined by considering the charge distribution along the channel in the saturation region. It has been stated that the unit charge in the channel may be written as a function of the distance x from the source diffusion. Q ( x) ( x) (73) unit ox GS Th The current at a distance x from the source is onsidering that I dx WQ ( x) d (74) unit oxw I GS Th I GS Th (75) L W L and rearranging the expression (74) leads to the following relation: GS L Th ox dx ( x) d (76) The potential at a distance x from the source diffusion along the channel can be found by integrating the equation (76) with the limits 0 and x. GS Th x ( x) GS Th dx GS Th ( x) d (77) L 0 0 The result of the integration is a second order equation with the variable (x) written as 8