XR-2211 FSK Demodulator/ Tone Decoder

...the analog plus company TM XR- FSK Demodulator/ Tone Decoder FEATURES APPLICATIONS June 997-3 Wide Frequency Range, 0.0Hz to 300kHz Wide Supply Voltage Range, 4.5V to 0V HCMOS/TTL/Logic Compatibility FSK Demodulation, with Carrier ion Wide Dynamic Range, 0mV to 3V rms Adjustable Tracking Range, +% to 80% Excellent Temp. Stability, +50ppm/ C, max. Caller Identification Delivery FSK Demodulation Data Synchronization Tone Decoding FM ion Carrier ion GENERAL DESCRIPTION The XR- is a monolithic phase-locked loop (PLL) system especially designed for data communications applications. It is particularly suited for FSK modem applications. It operates over a wide supply voltage range of 4.5 to 0V and a wide frequency range of 0.0Hz to 300kHz. It can accommodate analog signals between 0mV and 3V, and can interface with conventional DTL, TTL, and ECL logic families. The circuit consists of a basic PLL for tracking an input signal within the pass band, a quadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation. External components are used to independently set center frequency, bandwidth, and output delay. An internal voltage reference proportional to the power supply is provided at an output pin. The XR- is available in 4 pin packages specified for military and industrial temperature ranges. ORDERING INFORMATION Operating Part No. Package Temperature Range XR-M 4 Pin CDIP (0.300 ) -55 C to +5 C XR-N 4 Pin CDIP (0.300 ) -40 C to +85 C XR-P 4 Pin PDIP (0.300 ) -40 C to +85 C XR-ID 4 Lead SOIC (Jedec, 0.50 ) -40 C to +85 C 99 EXAR Corporation, 4870 Kato Road, Fremont, CA 94538 (50) 668-7000 FAX (50) 668-707

BLOCK DIAGRAM V CC GND 4 NC 9 INP Pre Amplifier Loop -Det LDO 3 LDF TIM C 4 VCO Lock Comparator 6 LDOQ TIM C TIM R 3 Internal Quad -Det 5 LDOQN V REF COMP I 0 8 V REF Reference FSK Comp 7 DO Figure. XR- Block Diagram

PIN CONFIGURATION V CC INP LDF GND LDOQN LDOQ DO 3 4 5 6 7 4 3 0 9 8 TIM C TIM C TIM R LDO V REF NC COMP I V CC INP LDF GND LDOQN LDOQ DO 3 4 5 6 7 4 3 0 9 8 TIM C TIM C TIM R LDO V REF NC COMP I 4 Lead CDIP, PDIP (0.300 ) 4 Lead SOIC (Jedec, 0.50 ) PIN DESCRIPTION Pin # Symbol Type Description V CC Positive Power Supply. INP I Receive Analog Input. 3 LDF O Lock Filter. 4 GND Ground Pin. 5 LDOQN O Lock Output Not. This output will be low if the VCO is in the capture range. 6 LDOQ O Lock Output. This output will be high if the VCO is in the capture range. 7 DO O Data Output. Decoded FSK output. 8 COMP I I FSK Comparator Input. 9 NC Not Connected. 0 V REF O Internal Voltage Reference. The value of V REF is V CC / - 650mV. LDO O Loop Output. This output provides the result of the quadrature phase detection. TIM R I Timing Resistor Input. This pin connects to the timing resistor of the VCO. 3 TIM C I Timing Capacitor Input. The timing capacitor connects between this pin and pin 4. 4 TIM C I Timing Capacitor Input. The timing capacitor connects between this pin and pin 3. 3

ELECTRICAL CHARACTERISTICS Test Conditions: V CC = V, T A = +5 C, R O = 30K, C O = 0.033 F, unless otherwise specified. Parameter Min. Typ. Max. Unit Conditions General Supply Voltage 4.5 0 V Supply Current 4 7 ma R 0 > 0K. See Figure 4. Oscillator Section Frequency Accuracy + +3 % Deviation from f O = /R 0 C 0 Frequency Stability Temperature +0 +50 ppm/ C See Figure 8. Power Supply 0.05 0.5 %/V V CC = +V. See Figure 7. 0. %/V V CC = + 5V. See Figure 7. Upper Frequency Limit 00 300 khz R 0 = 8.K, C 0 = 400pF Lowest Practical Operating Frequency 0.0 Hz R 0 = M, C 0 = 50 F Timing Resistor, R 0 - See Figure 5 Operating Range 5 000 K Recommended Range 5 K See Figure 7 and Figure 8. Loop Phase Dectector Section Peak Output Current +50 +00 +300 A Measured at Pin Output Offset Current A Output Impedance M Maximum Swing +4 + 5 V Referenced to Pin 0 Quadrature Phase or Measured at Pin 3 Peak Output Current 00 300 A Output Impedance M Maximum Swing V PP Input Preampt Section Measured at Pin Input Impedance 0 K Input Signal Voltage Required to Cause Limiting 0 mv rms Notes Parameters are guaranteed over the recommended operating conditions, but are not 00% tested in production. Bold face parameters are covered by production test and guaranteed over operating temperature range. 4

DC ELECTRICAL CHARACTERISTICS (CONT D) Test Conditions: V CC = V, T A = +5 C, R O = 30K, C O = 0.033 F, unless otherwise specified. Parameter Min. Typ. Max. Unit Conditions Voltage Comparator Section Input Impedance M Measured at Pins 3 and 8 Input Bias Current 00 na Voltage Gain 55 70 db R L = 5.K Output Voltage Low 300 500 mv I C = 3mA Output Leakage Current 0.0 0 A V O = 0V Internal Reference Voltage Level 4.9 5.3 5.7 V Measured at Pin 0 Output Impedance 00 AC Small Signal Maximum Source Current 80 A Notes Parameters are guaranteed over the recommended operating conditions, but are not 00% tested in production. Bold face parameters are covered by production test and guaranteed over operating temperature range. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Power Supply.............................. 0V Input Signal Level........................ 3V rms Power Dissipation....................... 900mW Package Power Dissipation Ratings CDIP.................................. 750mW Derate Above T A = 5 C............... 8mW/ C PDIP.................................. 800mW Derate Above T A = 5 C.............. 60mW/ C SOIC.................................. 390mW Derate Above T A = 5 C............... 5mW/ C SYSTEM DESCRIPTION The main PLL within the XR- is constructed from an input preamplifier, analog multiplier used as a phase detector and a precision voltage controlled oscillator (VCO). The preamplifier is used as a limiter such that input signals above typically 0mV rms are amplified to a constant high level signal. The multiplying-type phase detector acts as a digital exclusive or gate. Its output (unfiltered) produces sum and difference frequencies of the input and the VCO output. The VCO is actually a current controlled oscillator with its normal input current (f O ) set by a resistor (R 0 ) to ground and its driving current with a resistor (R ) from the phase detector. The output of the phase detector produces sum and difference of the input and the VCO frequencies (internally connected). When in lock, these frequencies are f IN + f VCO ( times f IN when in lock) and f IN - f VCO (0Hz when lock). By adding a capacitor to the phase detector output, the times f IN component is reduced, leaving a DC voltage that represents the phase difference between the two frequencies. This closes the loop and allows the VCO to track the input frequency. The FSK comparator is used to determine if the VCO is driven above or below the center frequency (FSK comparator). This will produce both active high and active low outputs to indicate when the main PLL is in lock (quadrature phase detector and lock detector comparator). 5

PRINCIPLES OF OPERATION Signal Input (Pin ): Signal is AC coupled to this terminal. The internal impedance at pin is 0K. Recommended input signal level is in the range of 0mV rms to 3V rms. Quadrature Phase or Output (Pin 3): This is the high impedance output of quadrature phase detector and is internally connected to the input of lock detect voltage comparator. In tone detection applications, pin 3 is connected to ground through a parallel combination of R D and C D (see Figure 3) to eliminate the chatter at lock detect outputs. If the tone detect section is not used, pin 3 can be left open. Lock Output, Q (Pin 6): The output at pin 6 is at low state when the PLL is out of lock and goes to high state when the PLL is locked. It is an open collector type output and requires a pull-up resistor, R L, to V CC for proper operation. At low state, it can sink up to 5mA of load current. Lock Complement, (Pin 5): The output at pin 5 is the logic complement of the lock detect output at pin 6. This output is also an open collector type stage which can sink 5mA of load current at low or on state. FSK Data Output (Pin 7): This output is an open collector logic stage which requires a pull-up resistor, R L, to V CC for proper operation. It can sink 5mA of load current. When decoding FSK signals, FSK data output is at high or off state for low input frequency, and at low or on state for high input frequency. If no input signal is present, the logic state at pin 7 is indeterminate. FSK Comparator Input (Pin 8): This is the high impedance input to the FSK voltage comparator. Normally, an FSK post-detection or data filter is connected between this terminal and the PLL phase detector output (pin ). This data filter is formed by R F and C F (see Figure 3.) The threshold voltage of the comparator is set by the internal reference voltage, V REF, available at pin 0. Reference Voltage, V REF (Pin 0): This pin is internally biased at the reference voltage level, V REF : V REF = V CC / - 650mV. The DC voltage level at this pin forms an internal reference for the voltage levels at pins 5, 8, and. Pin 0 must be bypassed to ground with a 0. F capacitor for proper operation of the circuit. Loop Phase or Output (Pin ): This terminal provides a high impedance output for the loop phase detector. The PLL loop filter is formed by R and C connected to pin (see Figure 3.) With no input signal, or with no phase error within the PLL, the DC level at pin is very nearly equal to V REF. The peak to peak voltage swing available at the phase detector output is equal to x V REF. VCO Control Input (Pin ): VCO free-running frequency is determined by external timing resistor, R 0, connected from this terminal to ground. The VCO free-running frequency, f O, is: f O R 0 C 0 Hz where C 0 is the timing capacitor across pins 3 and 4. For optimum temperature stability, R 0 must be in the range of 0K to 00K (see Figure 9.) This terminal is a low impedance point, and is internally biased at a DC level equal to V REF. The maximum timing current drawn from pin must be limited to < 3mA for proper operation of the circuit. VCO Timing Capacitor (Pins 3 and 4): VCO frequency is inversely proportional to the external timing capacitor, C 0, connected across these terminals (see Figure 6.) C 0 must be non-polar, and in the range of 00pF to 0 F. VCO Frequency Adjustment: VCO can be fine-tuned by connecting a potentiometer, R X, in series with R 0 at pin (see Figure 0.) VCO Free-Running Frequency, f O : XR- does not have a separate VCO output terminal. Instead, the VCO outputs are internally connected to the phase detector sections of the circuit. For set-up or adjustment purposes, the VCO free-running frequency can be tuned by using the generalized circuit in Figure 3, and applying an alternating bit pattern of O s and s at the known mark and space frequencies. By adjusting R 0, the VCO can then be tuned to obtain a 50% duty cycle on the FSK output (pin 7). This will ensure that the VCO f O value is accurately referenced to the mark and space frequencies. 6

Loop Filter ÎÎÎ ÎÎÎ ÎÎÎ φ Det ÎÎÎ Data Filter Î ÎÎÎÎÎ FSK Output FSK Comp ÎÎÎ Input Preamp φ ÎÎÎ VCO φ ÎÎÎ ÎÎÎ ÎÎÎ φ Det ÎÎÎ Î ÎÎ Lock Outputs Lock Filter Lock Comp Figure. Functional Block Diagram of a Tone and FSK Decoding System Using XR- V CC R B Loop Phase C R F 8 C F + 7 FSK Comp. R l Input Signal 0. F VCO 4 3 R 0. F R 0 0 Internal Reference Quad Phase C 0 3 + Lock Comp. 6 5 LDOQ LDOQN R D C D Figure 3. Generalized Circuit Connection for FSK and Tone ion 7

DESIGN EQUATIONS (All resistance in, all frequency in Hz and all capacitance in farads, unless otherwise specified) (See Figure 3 for definition of components). VCO Center Frequency, f O : f O R 0 C 0. Internal Reference Voltage, V REF (measured at pin 0): V REF V CC 650mV in volts 3. Loop Low-Pass Filter Time Constant, : C R PP (seconds) where: R PP R R F R R F if R F is or C F reactance is, then R PP = R 4. Loop Damping, : 50 C 0 R C Note: For derivation/explanation of this equation, please see TAN-0. 5. Loop-tracking bandwidth, f f 0 f R 0 f 0 R Tracking Bandwidth f f f LL f f O f f LH 8

6. FSK Data filter time constant, tf: F R B R F ( R B R F ) C F (seconds) 7. Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage across pin 0 and pin, per unit of phase error at phase detector input): K d V REF R 0, 000 volt radian Note: For derivation/explanation of this equation, please see TAN-0. 8. VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit of DC voltage change at pin ): K 0 V REF C 0 R 9. The filter transfer function: F(s) 0. Total loop gain. K T : radian second volt SR C at 0 Hz. S = J and = 0 K T K O K d F(s). Peak detector current I A : I A R F seconds 5, 000 C 0 (R R F ) V REF 0, 000 (V REF in volts and I A in amps) Note: For derivation/explanation of this equation, please see TAN-0. 9

APPLICATIONS INFORMATION FSK Decoding Figure 0 shows the basic circuit connection for FSK decoding. With reference to Figure 3 and Figure 0, the functions of external components are defined as follows: R 0 and C 0 set the PLL center frequency, R sets the system bandwidth, and C sets the loop filter time constant and the loop damping factor. C F and R F form a one-pole post-detection filter for the FSK data output. The resistor R B from pin 7 to pin 8 introduces positive feedback across the FSK comparator to facilitate rapid transition between output logic states. Design Instructions: The circuit of Figure 0 can be tailored for any FSK decoding application by the choice of five key circuit components: R 0, R, C 0, C and C F. For a given set of FSK mark and space frequencies, f O and f, these parameters can be calculated as follows: (All resistance in s, all frequency in Hz and all capacitance in farads, unless otherwise specified) a) Calculate PLL center frequency, f O : f O F F b) Choose value of timing resistor R 0, to be in the range of 0K to 00K. This choice is arbitrary. The recommended value is R 0 = 0K. The final value of R 0 is normally fine-tuned with the series potentiometer, R X. R O R O R X c) Calculate value of C0 from design equation () or from Figure 7: C O R 0 f 0 d) Calculate R to give the desired tracking bandwidth (See design equation 5). R R 0 f 0 (f f ) e) Calculate C to set loop damping. (See design equation 4): Normally, = 0.5 is recommended. C 50 C 0 R 0

f) The input to the XR- may sometimes be too sensitive to noise conditions on the input line. Figure 4 illustrates a method of de-sensitizing the XR- from such noisy line conditions by the use of a resistor, Rx, connected from pin to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level. V IN minimum (peak) V a V b V.8mV offset V REF 0, 000 (0, 000 R X ) or R X 0, 000 V REF V V IN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold) V CC Input Va Vb To Phase or Rx 0K 0K ÎÎ V REF 0 Figure 4. Desensitizing Input Stage g) Calculate Data Filter Capacitance, C F : R sum (R F R ) R B (R R F R B ) C F 0.5 (R sum Baud Rate) Baud rate in seconds Note: All values except R 0 can be rounded to nearest standard value.

Supply vs. Current (ma) 0 5 R 0 =5KΩ 0 R 0 =0KΩ 5 R 0 >00K 0 4 6 8 0 4 6 8 0 4 Supply Voltage, V + (Volts) C 0 ( F).0 0. ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ R 0 =5K ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ R 0 =0K ÎÎÎÎÎÎÎÎÎÎÎ R ÎÎÎÎÎÎÎÎÎÎÎ 0 =0K ÎÎÎÎÎÎÎÎÎÎÎ R 0 =40K ÎÎÎÎÎÎÎÎÎÎÎ R ÎÎÎÎÎÎÎÎÎÎÎ 0 =80K ÎÎÎÎÎÎÎÎÎÎÎ R 0 =60K 0.0 00 000 0000 f O (HZ) R 0 (K ),000 00 Figure 5. Typical Supply Current vs. V+ (Logic Outputs Open Circuited) ÎÎÎÎÎÎÎÎÎÎÎÎ C ÎÎÎÎÎÎÎÎÎÎÎÎ 0 =0.00 F ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ C 0 =0.0033 F ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ C ÎÎÎÎÎÎÎÎÎÎÎÎ 0 =0.0 F C ÎÎÎÎÎÎÎÎÎÎÎÎ 0 =0. F ÎÎÎÎÎÎÎÎÎÎÎÎ C 0 =0.033 F ÎÎÎÎÎÎÎÎÎÎÎÎ C 0 =0.33 F 0 0 000 0000 f O (Hz) Figure 7. VCO Frequency vs. Timing Capacitor Figure 6. VCO Frequency vs. Timing Resistor Normalized Frequency.0.0.00 4 5 f O = khz R F = 0R 0 4 5 3 0.99 Curve R 0 5K 0.98 0K 3 30K 4 00K 0.97 5 300K 4 6 8 0 4 6 8 0 4 V+ (Volts) Figure 8. Typical f O vs. Power Supply Characteristics 3 Normalized Frequency Drift (% of f O ) +.0 +0.5 0 R 0 =0K R0=50K R0=500K MΩ 500K 50K 0K -0.5 V+ = V R0=MΩ R = 0 R 0 -.0 f O = khz -50-5 0 5 50 75 00 5 Temperature ( C) Figure 9. Typical Center Frequency Drift vs. Temperature

Design Example: 00 Baud FSK demodulator with mark and space frequencies of 00/00. Step : Calculate f O : from design instructions (a) f O 00 00 =64 Step : Calculate R 0 : R 0 =0K with a potentiometer of 0K. (See design instructions (b)) (b) R T 0 0 5K Step 3: Calculate C 0 from design instructions (c) C O 5000 64 39nF Step 4: Calculate R : from design instructions (d) R 0000 64 (00 00) 5, 000 Step 5: Calculate C : from design instructions (e) C 50 39nF 5000 0.5 3.9nF Step 6: Calculate R F : R F should be at least five times R, R F = 5,000 5 = 55 K Step 7: Calculate R B : R B should be at least five times R F, R B = 55,000 5 =. M Step 8: Calculate R SUM : R SUM (R F R ) R B (R F R R B ) 40K Step 9: Calculate C F : C F 0.5 R SUM Baud Rate nf Note: All values except R 0 can be rounded to nearest standard value. 3

V CC Input Signal 0.µF Loop Phase Quad Phase VCO 4 3 C O 7nF 5% R F 78K C 5% C.7nF nf F 0% 5% R 35.K 0 % 0.µF R 0 0K % Rx 0K VCO Fine Tune R B.8m 5% 8 7 + Lock Comp. FSK Comp. Internal Reference 6 5 LDOQ R L 5.K 5% Data Output LDOQN Figure 0. Circuit Connection for FSK Decoding of Caller Identification Signals (Bell 0 Format) V CC Input Signal 0.µF Loop Phase C VCO 4 3 R F R 0.µF R 0 8 C F 0 R B + 7 FSK Comp. Internal Reference R L 5.k C 0 Rx 6 LDOQ Quad Phase Between 400K and 600K R D 3 C D Lock Comp. 5 LDOQN Figure. External Connectors for FSK Demodulation with Carrier Capability 4

V CC Loop Phase VCO C 0pF 5% R 00K % 0.µF 8 0 + 7 FSK Comp. Internal Reference Tone Input 0.µF Quad Phase 4 3 C 0 50nF 5% R D 470K 3 R 0 0K % Rx 5K VCO Fine Tune C D 80nF + Lock Comp. 6 LDOQ V CC 5 LDOQN RL 5.K RL3 5.K Logic Output Figure. Circuit Connection for Tone ion FSK Decoding with Carrier The lock detect section of XR- can be used as a carrier detect option for FSK decoding. The recommended circuit connection for this application is shown in Figure. The open collector lock detect output, pin 6, is shorted to data output (pin 7). Thus, data output will be disabled at low state, until there is a carrier within the detection band of the PLL and the pin 6 output goes high to enable the data output. Note: Data Output is Low When No Carrier is Present. The minimum value of the lock detect filter capacitance C D is inversely proportional to the capture range, + fc. This is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. It is further limited by C. For most applications, fc > f/. For R D = 470K, the approximate minimum value of C D can be determined by: C D 6 f C in F and f in Hz. C in F and f in Hz. With values of C D that are too small, chatter can be observed on the lock detect output as an incoming signal frequency approaches the capture bandwidth. Excessively large values of C D will slow the response time of the lock detect output. For Caller I.D. applications choose C D = 0. F. Tone ion Figure shows the generalized circuit connection for tone detection. The logic outputs, LDOQN and LDOQ at pins 5 and 6 are normally at high and low logic states, respectively. When a tone is present within the detection band of the PLL, the logic state at these outputs become reversed for the duration of the input tone. Each logic output can sink 5mA of load current. Both outputs at pins 5 and 6 are open collector type stages, and require external pull-up resistors R L and R L3, as shown in Figure. With reference to Figure 3 and Figure, the functions of the external circuit components can be explained as follows: R 0 and C 0 set VCO center frequency; R sets the detection bandwidth; C sets the low pass-loop filter time constant and the loop damping factor. 5

Design Instructions: The circuit of Figure can be optimized for any tone detection application by the choice of the 5 key circuit components: R 0, R, C 0, C and C D. For a given input, the tone frequency, f S, these parameters are calculated as follows: (All resistance in s, all frequency in Hz and all capacitance in farads, unless otherwise specified) a) Choose value of timing resistor R 0 to be in the range of 0K to 50K. This choice is dictated by the max./min. current that the internal voltage reference can deliver. The recommended value is R 0 = 0K. The final value of R 0 is normally fine-tuned with the series potentiometer, R X. b) Calculate value of C 0 from design equation () or from Figure 7 f S = f O : C O R 0 fs c) Calculate R to set the bandwidth + f (See design equation 5): R R 0 f 0 f Note: The total detection bandwidth covers the frequency range of f O + f d) Calculate value of C for a given loop damping factor: Normally, = 0.5 is recommended. C 50 C 0 R Increasing C improves the out-of-band signal rejection, but increases the PLL capture time. e) Calculate value of the filter capacitor C D. To avoid chatter at the logic output, with R D = 470K, C D must be: C D 6 f Cin F Increasing C D slows down the logic output response time. Design Examples: Tone detector with a detection band of + 00Hz: a) Choose value of timing resistor R 0 to be in the range of 0K to 50K. This choice is dictated by the max./min. current that the internal voltage reference can deliver. The recommended value is R 0 = 0 K. The final value of R 0 is normally fine-tuned with the series potentiometer, R X. b) Calculate value of C 0 from design equation () or from Figure 6 f S = f O : C 0 R 0 f S 50nF 0, 000, 000 6

c) Calculate R to set the bandwidth + f (See design equation 5): R R 0 f O f 0, 000, 000 00 400K Note: The total detection bandwidth covers the frequency range of f O + f d) Calculate value of C 0 for a given loop damping factor: Normally, = 0.5 is recommended. C 50 C 0 50 50 0 9 6.5pF R 400, 000 0.5 Increasing C improves the out-of-band signal rejection, but increases the PLL capture time. e) Calculate value of the filter capacitor C D. To avoid chatter at the logic output, with R D = 470K, C D must be: C D 6 f 6 80nF 00 Increasing C D slows down the logic output response time. f) Fine tune center frequency with 5K potentiometer, R X. V CC V CC Loop Phase C VCO R 0.µF 8 0 + 7 FSK Comp. Internal Reference R F 00K C F 0.µF 4 3 + LM34 Demodulated Output FM Input 0.µF 4 3 R 0 C 6 0 + Quad Phase 5 Lock Comp. LDOQ LDOQN Figure 3. Linear FM or Using XR- and an External Op Amp. (See Section on Design Equation for Component Values.) 7

Linear FM ion XR- can be used as a linear FM detector for a wide range of analog communications and telemetry applications. The recommended circuit connection for this application is shown in Figure 3. The demodulated output is taken from the loop phase detector output (pin ), through a post-detection filter made up of R F and C F, and an external buffer amplifier. This buffer amplifier is necessary because of the high impedance output at pin. Normally, a non-inverting unity gain op amp can be used as a buffer amplifier, as shown in Figure 3. The FM detector gain, i.e., the output voltage change per unit of FM deviation can be given as: V OUT R V REF 00 R 0 where VR is the internal reference voltage (V REF = V CC / - 650mV). For the choice of external components R, R 0, C D, C and C F, see the section on design equations. V + 0K 0K REF Voltage Output 0 Input 0K 0K B From VCO B Lock Filter 3 6 Lock Outputs 5 Internal Voltage Reference Input Preamplifier and Limiter Quadrature Phase or Lock Comparator K K A Timing Capacitor 3 C0 4 B B A A From VCO A Loop or Output 8 FSK Comparator Input 7 FSK Data Output 4 Ground R 0 Timing Resistor Voltage Controlled Oscillator 8K Loop Phase or FSK Comparator Figure 4. Equivalent Schematic Diagram 8

4 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev..00 4 8 7 E D E Base Plane A A Seating Plane L B e B α c INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.00 0.00.54 5.08 A 0.05 0.060 0.38.5 B 0.04 0.06 0.36 0.66 B 0.045 0.065.4.65 c 0.008 0.08 0.0 0.46 D 0.685 0.785 7.40 9.94 E 0.50 0.30 6.35 7.87 E 0.300 BSC 7.6 BSC e 0.00 BSC.54 BSC L 0.5 0.00 3.8 5.08 α 0 5 0 5 Note: The control dimension is the inch column 9

4 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev..00 4 8 7 E D E Seating Plane A L B e B A A α e A e B C INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.45 0.0 3.68 5.33 A 0.05 0.070 0.38.78 A 0.5 0.95.9 4.95 B 0.04 0.04 0.36 0.56 B 0.030 0.070 0.76.78 C 0.008 0.04 0.0 0.38 D 0.75 0.795 8.4 0.9 E 0.300 0.35 7.6 8.6 E 0.40 0.80 6.0 7. e 0.00 BSC.54 BSC e A 0.300 BSC 7.6 BSC e B 0.30 0.430 7.87 0.9 L 0.5 0.60.9 4.06 α 0 5 0 5 Note: The control dimension is the inch column 0

4 LEAD SMALL OUTLINE (50 MIL JEDEC SOIC) Rev..00 D 4 8 E H 7 Seating Plane C A α e B A L INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.053 0.069.35.75 A 0.004 0.00 0.0 0.5 B 0.03 0.00 0.33 0.5 C 0.007 0.00 0.9 0.5 D 0.337 0.344 8.55 8.75 E 0.50 0.57 3.80 4.00 e 0.050 BSC.7 BSC H 0.8 0.44 5.80 6.0 L 0.06 0.050 0.40.7 α 0 8 0 8 Note: The control dimension is the millimeter column

Notes

Notes 3

NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 995 EXAR Corporation Datasheet June 997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 4