SMALL-SINAL ANALYSIS AND ONTROL DESIN OF ISOLATED POWER SUPPLIES WITH OPTOOUPLER FEEDAK Yuri Panov and Milan Jovanović Power Electronics Laboratory Delta Products orporation P.O. ox 273, 5 Davis Drive Research Triangle Park, N 2779, USA Abstract - Optocouplers are widely used in isolated power supplies to transer the eedback signal rom the secondary to the primary side. In many power supplies, the eedback ampliier is supplied rom the output voltage that creates additional eedback path which should be accounted in the control design. The paper compares two possible loop gains corresponding to breaking the eedback loop at dierent locations. These loop gains are analyzed and are shown to have an unequal value or the design. Dynamic limitations o the TL43 shunt regulator and the optocoupler are discussed. Practical guidelines or the error ampliier design and a design example are presented. I. INTRODUTION enerally, oline and telecom power supplies require the galvanic isolation between a relatively high input voltage and low output voltages. The most widely used devices to transer signals across the isolation boundary are pulse transormers and optocouplers. The typical isolated power supply with the primaryside PWM control is shown in Fig.. The eedback signal is transerred rom the secondary to the primary side through the optocoupler O. The eedback circuit shown in Fig. is very popular in low-power / low-cost power supplies which usually do not have the standby converter to supply the TL43 shunt regulator but use output voltage V O or this purpose. It is well known [-7] that by supplying the TL43 rom the output voltage an additional eedback path is introduced. Thereore, in the control circuit in Fig. two loop gains which correspond to breaking the loop at locations A and can be considered. The existence o two loops immediately raises the question which loop gain should be analyzed and measured in order to meet the power supply stability and dynamic response speciications. From the general control theory, each loop gain o the entire control system yields the same characteristic polynomial and, thereore, reveals the system stability. However, depending on the chosen loop gain, error ampliier (EA) design is dierent which leads to dierent stability margins and dierent dynamic perormance. So ar, these issues have not been addressed in the literature. The purpose o the paper is to present comparative analysis o the loop gains corresponding to points A and and to provide design guidelines to power supply engineers. Section II o the paper provides general loop gain analysis and interpretation. Section III presents the comparative analysis o loop gains T A and T or the power supplies with the voltage-mode and the currentmode controls. Section III also discusses EA design limitations o the TL43 shunt regulator and o the optocoupler circuit. Sections + - IV and V present the design example and experimental results, respectively, whereas Section VI summarizes the paper. II. LOOP AIN ANALYSIS AND INTERPRETION A. Loop ain T A The small-signal block diagram corresponding to breaking the loop at point A is shown in Fig. 2. Figure 2 contains ollowing blocks: K D output voltage divider gain, = Vˆ Vˆ - error ampliier transer unction, EA O K R X A = Vˆ Vˆ - optocoupler circuit gain, = Vˆ Vˆ - control-to-output transer unction, VV ( OL ) O = Vˆ Vˆ - open-loop audio susceptibility, O( OL ) d PWM I PWM omp. O O N: O S IN Idc R2 Z = Vˆ î - open-loop output impedance. Z3 At point A in Fig. 2, the eedback signal is conined to a single path. Loop gain T A, corresponding to breaking the loop at point A is derived as: = AO ( + K D EA ) () The plant transer unction that provides the basis or the EA design is deined as LF R O Rc F POWER SE Z2 TL43 if Z RD2 +VO Fig.. Simpliied circuit diagram o isolated power supply with optocoupler eedback. E VK VR A RD KD VX -783-827-6/4/$7. () 24 IEEE
VV(OL) ZO(OL) io VV(OL) ZO(OL) io Plant A A VO KD TINNER VO KD -AO VR EA Plant -AO VR EA Fig. 2. Small-signal block diagram corresponding to breaking the loop at point A. Fig. 3. Small-signal block diagram corresponding to breaking the loop at point. PL( A ) = A. (2) It should be noted that the EA is not connected in series with the plant and zeroes o EA generally do not translate into the same zeroes o the loop gain T A. However, in many cases, K D EA >> within the loop bandwidth and loop gain T A can be written as PL( A ) K D EA. (3) For loop gain T A given in (3), the EA design procedure does not dier rom that or the implementation where the optocoupler is supplied rom the ixed voltage. I condition K D EA >> is not satisied within the loop bandwidth, the relationship between the zeroes o terms K D EA and [ + K D EA ] can be very complex, particularly, when the EA transer unction has more than two poles. To simpliy the EA design in this case, it is recommended to keep the order o the EA transer unction not higher than two, but to add necessary poles and zeroes by connecting compensation network Z 3 on the primary side, as shown in Fig.. There is one more reason to connect compensation network Z 3 on the primary side. Term [ + K D EA ] in () has the slope o d/dec at high requencies. To attenuate the switching noise at high requencies, it is desirable to add the primary-side pole at the crossover requency o term [ + K D EA.]. It is important to ind the relationship between loop gain T A and the converter requency-domain response to line and load variations. To simpliy the analysis, it is assumed that the converter operates with the voltage-mode control. The closed loop audio susceptibility VV(L) and output impedance Z O(L) are derived rom the block diagram in Fig. 2 as VV ( OL ) Z O( OL ) VV ( L ) = and Z O( L ) =. (4) + + Relationships (4) are straightorward imply that it is desirable to maximize loop gain T A in order to achieve the best rejection o the line and load disturbances.. Loop ain T The small-signal block diagram corresponding to breaking the loop at point is shown in Fig. 3. Ater opening the loop at point, the eedback signal propagates through resistor R and aects LED current i F in Fig.. Observation o the block diagram in Fig. 3 shows that ater breaking the loop at location the inner control loop still exists with the gain o TINNER = AO. (5) Loop gain T, corresponding to breaking at point in Fig. 3, is derived as O T A O INNER = K D EA = K D EA. (6) + AO INNER enerally, since loop contains the inner eedback loop, the design o loop gain T is a two-step procedure. Namely, prior to loop gain T analysis, T INNER gain must be examined or stability. The inner loop gain is relatively low because it does not contain the high-gain EA and its stability rarely becomes a practical problem. It should be noted that T INNER can be compensated by connecting network Z 3 on the primary side, as shown in Fig., so that the design o loop gain T can be urther optimized. The analysis and implementation o the inner loop compensation was presented in [8] in the context o the magamp control. In act, the control o the isolated power supply with optocoupler supplied rom the output voltage is similar to the magamp control where the magamp reset circuit is supplied rom the output voltage [8, 9]. Equations (), (5) and (6) are used to derive the relationship between T A and T : = TINNER + ( INNER ) T. (7) The last equation indicates that there is no unique relationship between T A and T, unless T INNER is known. The plant transer unction that provides the basis or the EA design is deined as TINNER AO PL( A ) PL( ) = = =. (8) INNER + AO + PL( A ) omparison o (2) and (8) reveals that the poles o plant transer unction PL() are dierent rom those o plant transer unction PL(A). Namely, at low requencies, where T INNER >>, transer unction PL(). At high requencies, where T INNER <<, transer unction PL() PL(A). The poles o PL() are actually shited to higher requencies with respect to those o PL(A) [8, 9]. Hence, the compensator poles and zeroes are selected dierently depending on which loop gain, T A or T, is used or the design. Loop gain T can be written as T = PL( ) K D EA. (9) From the block diagram in Fig. 3, the relationship between loop gain T and closed-loop audio susceptibility VV(L) and output impedance Z O(L) o the converter with the voltage-mode control is VV ( OL ) ( INNER ) VV ( ) VV ( L ) = =, and T -783-827-6/4/$7. () 24 IEEE
Z O( L ) where ( ) Z O( OL ) INNER Z L( ) = =, () VV ( ) VV ( OL ) = and Z INNER L( ) Z O( OL ) =. () INNER It should be noted that transer unctions VV() and Z L() given in () represent the audio susceptibility and output impedance o the converter with only the inner loop closed. Equations () and () indicate that or optimal rejection o line and load disturbances loop gain T as well as loop gain T INNER should me maximized. Loop gain T INNER can be maximized by compensating optocoupler circuit gain A O, whereas loop gain T can be optimized by compensating EA gain EA. However, placement o A O poles and zeroes at desired locations is not straightorward because their requencies are dependent on the optocoupler circuit smallsignal parameters, as it will be shown in Section III. Moreover, loop gain T INNER aects plant transer unction PL() which is the basis or the EA design. Thereore, the design procedure or optimization o the audiosusceptibility and output impedance based on breaking the loop gain at point is more complex than in the case o the design based on loop gain T A. The purpose o the next Section is to compare EA designs based on loop gains T A and T. III. ERROR AMPLIFIER DESIN ONSIDERATIONS A. Power Supplies with Voltage-Mode ontrol ontrol-to-output transer unction o the orward converter in Fig. in the case o the voltage-mode control becomes = FM VD, (2) where F M is the gain o the pulse-width modulator (PWM) that is shown inside the control I in Fig.. Then, plant transer unctions PL(A) and PL() o the converter operating in M can be written as PL( A ) PL( ) = A F, (3) O M PL( A ) VD PL( A ) =, (4) + + s ω Z where VD =, (5) 2 2 N + s ( ω Q ) + s ω LF F ω =, Q =, ω Z = and R L LF L F F RL + R F R F is the load resistance. Equations (3) and (5) indicate that transer unction PL(A) has a pair o complex-conjugate poles near resonant requency A = ω ( 2 π ). To achieve stability and high dynamic perormance, the EA transer unction or the voltage-mode control has two zeroes and three poles: ω i [ + s ω Z ] [ + s ω Z 2 ] EA =. (6) s [ + s ω P ] [ + s ω P 2 ] Asymptotic ode plots o the plant and EA transer unctions, as well as o loop gain T A, are shown in Fig. 4 or the compensation design based on loop gain T A. ompensation zero Z is placed at plant A resonant requency A and zero Z2 is placed between A and expected loop crossover requency. ompensation pole P is placed at the ESR zero requency, and pole P2 is placed between P and the switching requency. oth loop gains T A and T have same crossover requency and expected to have similar stability margins. Since the loop gains cross d axis with the slope, the phase margin up to 9º is anticipated. When the EA design is based on loop gain T, the corresponding asymptotic ode plots are shown in Fig. 5. Plant has the resonant requency A + PL( A )( ) [9]. ompensator zero Z is placed between A and, whereas compensator zero Z2 is placed around. Observation o loop gain T A in Fig. 5 indicates the conditional stability since the phase can go down to 27º within the loop bandwidth. The conditionally stable loop becomes unstable when the loop gain is reduced. It is particularly unacceptable in the case o the optocoupler eedback since the optocoupler TR varies signiicantly with temperature variations and with aging. It should be noted that loop gain T shows no sign o the conditional stability since it does not reveal the low-requency dynamics o the power supply. The conditional stability can be avoided i compensator zero Z is placed below resonant requency A o plant A. Then, loop gain T A has 2 slope in the requency range between A and, and T A phase characteristic does not go below 8º. PL() KDEA(A) - 2 + T A Z Z2 + PL(A)() PL(A) zc P P2 Fig. 4. EA design based on loop gain T A or voltage-mode control. -783-827-6/4/$7. () 24 IEEE
PL(A) PL() A zc - PL(A) PL() PA P KDEA(A) PL(A)() zc - + KDEA() - z P T Z2 Z -3 P P2 T c 8 [deg] -9 7 Fig.5. EA design based on loop gain T or voltage-mode control.. Power Supplies with urrent-mode ontrol In the case o the current-mode control, the ramp signal or the PWM in Fig. is derived by measuring the inductor L F current. It should be noted that in real power supplies the measurement o the inductor current is replaced with the measurement o the primary switch current. Simpliied control-to-output transer unction o the orward converter with the current-mode control is given by [] RL + s ω Z PL( A ) = AO = AO, (7) R + s ω where requencies o poles and zeroes are ω Z = ( R F ) and ω = \ [( R + R ) ], and R S is the current-sensing PA L F gain. To explain the EA design, asymptotic ode plots o the converter transer unctions are employed. The asymptotic ode plots o the plant transer unctions PL(A) and PL() are shown in Fig. 6. Plant has higher pole requency than that o plant A which is governed by equation: S PA Fig. 6. EA design based on loop gain T A or current-mode control. P PA PL( A )( ). (8) As can be seen in Fig. 6, PL() magnitude stays close to unity in the requency range below P. Thereore, the transer unction o plant does not reveal the low-requency dynamic characteristics o the power stage. Fig. 6 also shows the asymptotic ode plot o the compensation network or plant A with one zero and two poles ωi [ + s ωz ] + K D EA K D EA =, (9) s [ + s ωp which is typically used in converters with the current-mode control. The compensation zero Z = ω Z /(2 π) is placed at pole PA requency, and compensation pole P = ω P /(2 π) is placed at zero Z requency. The resulting asymptotic ode plots o loop gains T A and T in Fig. 6 have same crossover requency and expected to have similar ample stability phase margins. When the error ampliier design is based on loop gain T, the corresponding asymptotic ode plots are shown in Fig. 7. ompensation zero Z and pole P are placed to coincide with pole P and zero Z, respectively. As Fig. 7 demonstrates, crossover requencies and the predicted phase margins are essentially the same or loop gains T A and T. Since the loop gains cross the d axis with the slope, the phase margin is expected to be close to 9º.. TL43 Frequency Response Limitations Subsections A and were presented assuming that EA transer unction EA is completely determined by compensation networks Z and Z 2, namely, EA = Z 2 Z. (2) This assumption is valid only when the EA has the ininite gain -783-827-6/4/$7. () 24 IEEE
PL(A) PL() KDEA() T PA P in the requency range o interest. I the TL43 inite gainbandwidth product is accounted, the EA transer unction can be derived as: Z 2 EA = Z + ( Z + Z 2 ), (2) TL43 where TL43 (s) is the TL43 open-loop gain. I the TL43 characteristic were well deined, the last equation would provide or an accurate EA design. Unortunately, the inormation about the TL43 open-loop requency response, available rom the manuacturer data sheets, is very sketchy and insuicient or the accurate EA design. In addition, the TL43 requency response strongly depends on the regulator bias cathode current and values o the components connected to its output, namely, R and Z 2. Nevertheless, based on the authors practical experience, several practical observations can be made. First, or EA transer unction EA to be completely determined by (2), relationship EA << TL43 (22) must be observed. Inequality (22) is practically observed i its let side is by 34-4 d less than its right side. I (22) is violated, but still EA < TL43, then (2) can be used with the typical values o 5-6 d dc gain and MHz bandwidth. The TL43 certainly cannot implement the EA transer unction whose gain is above the shunt regulator open loop gain. Second, as in the case o an operational ampliier, the large capacitance connected to the TL43 output severely limits the regulator bandwidth. Thereore, compensation network Z 2 Z c zc P Fig. 7. EA design based on loop gain T or current-mode control. should be implemented with the minimum capacitance amount. Namely, the value o the capacitor between the TL43 cathode and reerence pins should not exceed several hundred pf. D. Optocoupler ircuit Small-Signal Model The dynamic model o the isolated power supply is incomplete without considering the small-signal characteristics o the optocoupler. The optocoupler small-signal model [], corresponding to the circuit in Fig., is shown in Fig. 8. The circuit in Fig. 8 contains the bipolar transistor hybrid model in the common-emitter coniguration with ollowing parameters: h ie input resistance with shorted output, h oe output conductance with open input, h e orward ampliication gain. The phototransistor model in Fig. 8 also includes collector-base junction capacitance and two dependent current sources îp = îf TR h e and h e î. Since the collector-base junction in phototransistors is used as a light detector, its area is relatively large. As a result, phototransistors have high capacitance that limits their bandwidth. The typical values o the optocoupler parameters used in the power supplies are = 5 pf and h FE = 35. Using the diagram in Fig. 8 and assuming Vˆ E << Vˆ E, hoe >> R2 Z 3, the optocoupler circuit transer unction is derived: TR AO =. (23) R ( R2 Z 3 ) + s hfe When network Z 3 consists o single capacitor 2, equation (23) is simpliied to: R2 AO = TR, (24) R + s ω where ω = [ R ( + h )] O 2 2 FE O. It should be noted that the maximum value o pole requency ω O is limited by the phototransistor parameters and h FE. For example, or R2 = kω the requency o this pole is below 3 khz. h ie i b i p h e i b E Phototransistor Model h oe IV. DESIN EXAMPLE R2 Z3 Fig. 8. Small-signal model o the optocoupler circuit. This section considers the 38-V/5-V, 2-A, -khz orward power supply, whose simpliied schematic is shown in Fig.. Transormer with turns ratio N o 2: is assumed. The output ilter inductor value is L F = µh, whereas output capacitance consists o two 33-µF aluminum capacitors with 8-mΩ ESR each. The design example also assumes F M = V -783-827-6/4/$7. () 24 IEEE
and the optocoupler circuit values o TR = % and R = R 2 = kω. A. Power Supply with Voltage Mode ontrol The ode plots o plant transer unctions PL(A) and PL() o the power supply with the voltage-mode control are shown in Fig. 9. The plant transer unctions in Fig. 9 are dierent at low requencies where A O >>. Actually, due to the inner loop inluence, the loop gain T does not reveal the control loop dynamics at low requencies where its value is close to unity. Also between resonant requencies A =.6 khz and = 2.8 khz, the phase lag o loop gain T A is considerably higher than that o loop gain T. The plots in Fig. 9 indicate that it is much easier to design the EA or plant than or plant A. The next step is to compare EA designs based on loop gains PL(A) and PL(). Error Ampliier Design ased On Loop ain T A. The ode plots o the plant and EA transer unctions, as well as the ode plots o loop gain T A, are shown in Fig.. The EA compensation with ω i =.2 3 rad/sec, Z = Z2 = 55 Hz, P = P2 = khz was chosen to provide 7.-kHz T A bandwidth with the corresponding phase margin o 63º. As can be seen rom Fig., or this EA compensation, loop gain T has only 9-Hz bandwidth and corresponding 5º phase margin. This implies that a wide bandwidth o T A does not translate into a wide bandwidth o T. Error Ampliier Design ased On Loop ain T. The ode plots o the plant and EA transer unctions, as well as o the loop gain T, are shown in Fig.. The EA compensation with ω i = 4 3 rad/sec, Z = Z2 = 2 khz, P = 2.6 khz, and P2 = 4 khz was selected to provide 6.9-kHz T bandwidth with the corresponding phase margin o 58º. Figure also shows loop gain T A or the EA design mentioned above. Observation o Fig. reveals 7.2-kHz T A bandwidth with the phase margin o 55º. Figure also shows that loop gain T A is conditionally stable since its phase drops below 8º around -khz requency which is within the bandwidth o T A. The conditional stability is more pronounced at high Q values o the power stage transer unction. enerally, the conditional stability is not acceptable since the power supply can become unstable during large-signal line transients or as a result o component degradation. Loop gain T in Fig. does not show the conditional stability problem because the power stage characteristics are hidden within T INNER bandwidth and PL() is not proportional to such critical gains o the inner loop, as the input voltage and the optocoupler TR. Thereore, the EA design based on loop gain T A is preerable to the one based on loop gain T.. Power Supply with urrent-mode ontrol The parameter values assumed or the current-mode control are F M = 2.86 V and R S = 25 mω. Figure 2 shows the detailed small-signal block diagram o the converter with the currentmode control. The diagram contains the internal current control loop with ollowing blocks: ID = î dˆ - duty-ratio-to-inductor-current transer unction, L H E sampling transer unction [2], R S current sensing gain, 4 3 2 2 3 Magnitude [d] 4. 3. 4. 5 3 3 6 9 2 5 PL(A) PL() A PL(A) PL() 8. 3. 4. 5 Fig. 9. Transer unctions o plants A and or voltage-mode control. Magnitude [d] 5 4 3 EA(A) 2 T 2 3 4 5. 3. 4. 5 6 3 3 6 9 2 5 T EA(A) 8. 3. 4. 5 Fig.. Loop gain design based on plant A or voltage-mode control. -783-827-6/4/$7. () 24 IEEE
A Magnitude [d] 8 7 6 5 4 3 EA() 2 T 2 3 4. 3. 4. 5 ID d FM RS He VD -AO VO EA KD 3 EA() Fig. 2. Small-signal block diagram o isolated power supply with currentmode control. 3 6 9 2 5 8 2. 3. 4. 5 F M PWM gain. ased on the diagram in Fig. 2, the control-to-output transer unction is described by equation FM VD =. (25) + FM ID RS H E Transer unction ID in (25) is derived based on the PWM switch model [3] + s ω Z 2 ID =, (26) 2 2 N R + s ( ω Q ) + s ω where = ( R ) ω. Z 2 F L Fig.. Loop gain design based on plant or voltage-mode control. The ode plots o plant transer unctions PL(A) and PL() are shown in Fig. 3. As Fig. 3 demonstrates, the plant transer unctions are dierent at low requencies where A O >>. Actually, due to the inner loop inluence, the plant phase characteristic exhibits less phase lag at low requencies and, thereore, loop gain T is easier to compensate than loop gain T A. The next step is to compare EA designs based on loop gains T A and T. Error Ampliier Design ased On Loop ain T A. Figure 4 shows the loop gain design or plant A which produces ollowing locations o compensator poles and zeroes ω i = 3.45 3 rad/s, z = Hz, and p = 5 khz. This design provides -khz loop bandwidth with the corresponding phase margin o 97º. Figure 4 also shows loop gain T corresponding to the compensator design or plant A. The loop gain T has 2.7-kHz loop bandwidth with the corresponding phase margin o 33º. T Magnitude [d] 5 4 3 PL(A) 2 2 PL() 3 4. 3. 4. 5 3 3 6 9 2 5 PL(A) PL() 8. 3. 4. 5 Fig. 3. Transer unctions o plants A and or current-mode control. Error Ampliier Design ased On Loop ain T. The corresponding EA transer unction and loop gain T are plotted in Fig. 5. The compensator has ollowing poles and zeroes: ω i = 5 3 rad/s, z = 2 khz, and p = 5 khz. This design provides -khz loop bandwidth or loop gain T, the same as the bandwidth or loop gain T A in the case when the design was done or plant A. The phase margin o loop gain T is 95º. Figure 5 also shows loop gain T A corresponding to the compensator design or plant. The loop gain T A has 5-kHz loop bandwidth with the phase margin o 68º. Observation o Figs. 9 and 35 implies that the magnitude o loop gain T A is higher than that o loop gain T. T A is higher than T at low requencies since PL(A) is higher than PL() at low requencies. T A is higher than T at high -783-827-6/4/$7. () 24 IEEE
Magnitude [d] 6 5 4 3 EA(A) 2 T 2 3 4. 3. 4. 5 3 6 9 2 5 EA(A) T 8. 3. 4. 5 Fig. 4. Loop gain design based on plant A or current-mode control. 8 6 4 2 2 T Magnitude [d] EA() EA() 4. 3. 4. 5 3 6 T design is based on loop gain T A, loop gain T is expected to have lower bandwidth and higher stability margins than loop gain T A. The presented design example implies that, in the case o the current-mode control, both loop gains T A and T can be used or the EA design. V. EXPERIMENL RESULTS The 38-V/2-V, 45-A two-switch orward power supply operating at -khz switching requency was used as an experimental prototype. The power transormer has N = : turns ratio. The output ilter inductor value was L F =.5 uh, whereas output capacitance F consisted o three 33-uF aluminum capacitors with 35-mΩ ESR each. The converter operated with the current-mode control that was implemented by measuring the primary switch current with the.5-ω resistor. ompensation network Z 2 was a series connection o 27-kΩ resistor and 5.6-nF capacitor, whereas network Z was not used. Thereore, EA transer unction had the single pole at the origin and one zero at -khz requency. The second compensation pole was introduced by the optocoupler network on the primary side. The prototype employs SHF67-3 optocoupler with the TR range o % or I F = ma. The component values o the optocoupler circuit are R = R 2 = kω, 2 = 4.7 nf, where 2 is the sole component o compensation network Z 3 in Fig.. ode plots o the transer unctions corresponding to breaking the loop at point A are shown in Fig. 6. As expected 7 6 5 4 3 2 2 3 KD EA PL(A) MANITUDE [D] calculated 4. 3. 4. 5 Frequency [Hz] 9 2 5 8 2 4 6 8 PHASE [DE] KD EA 2. 3. 4. 5 Fig. 5. Loop gain design based on plant or current-mode control. requencies since +K D EA is higher than K D EA at high requencies. At the same time, the phase lag o loop gain T A is generally higher than that o loop gain T. Thereore, i the EA 2 4 6 8 calculated PL(A) 2. 3. 4. 5 Fig. 6. Measured and calculated transer unctions corresponding to breaking the loop at point A. -783-827-6/4/$7. () 24 IEEE
MANITUDE [D] 7 6 5 4 3 2 T KD EA 2 PL() calculated T 3 4. 3. 4. 5 Frequency [Hz] 2 2 4 6 8 2 4 6 8 PL() calculated T PHASE [DE] KD EA 2. 3. 4. 5 or the current-mode control, PL(A) is the irst-order transer unction with the dominant pole located around 4 Hz. Since K D EA >> in the requency range up to hal o the switching requency, the loop gain is PL _ A AO K D EA, and EA design procedure is conventional. Loop gain T A has the crossover requency o 6.7 khz, the phase margin o 68º and the gain margin o 8 d. Figure 7 shows ode plots o the transer unctions corresponding to breaking the loop at point. At low requencies, plant transer unction PL() is close to d and its phase is also close to zero. The EA phase is supposed to reach º at high requencies and stay at this value. However, at requencies above khz the EA phase starts to drop because o the insuicient TL43 open-loop gain in the high-requency range. Resulting gain T has the bandwidth o 5.6 khz, the phase margin o 9º and the gain margin o 9 d. Observation o Figs. 6 and 7 implies that loop gains T A and T have similar crossover requencies and stability margins or the optimized compensation and can be both used or the EA design. For analysis veriication, Figs. 6 and 7 also show calculated loop gains T A and T. Measured and calculated loop gains demonstrate reasonable agreement with each other. T Fig. 7. Measured and calculated transer unctions corresponding to breaking the loop at point. VI. SUMMARY In the isolated power supplies with the optocoupler eedback, two loops can be identiied with corresponding loop gains T A and T. The comparative analysis shows that loop gain T A provides more straightorward design approach and more meaningul relationship between the loop gain and converter response to the line and load disturbances. It was ound that in power supplies with the current-mode control both loop gains can be used or the compensation design. However, in the power supplies with the voltage-mode control the bandwidth can be very dierent depending on which loop gain was used or the compensator design. Also, in the power supplies with the voltage-mode control it is preerable to use the loop gain T A or the EA design in order to avoid the conditional stability. Dynamic limitations o the TL43 shunt regulator and o the optocoupler were discussed. Practical guidelines or the compensation design in converters with current-mode and voltage-mode controls, as well as experimental results were presented. REFERENES []. Mammono, "Isolating The ontrol Loop,", Unitrode Seminar Proc., 997, pp. 2-25. [2] K. illings, "Handbook O Switchmode Power Supplies", Mcraw-Hill Publishing ompany, 989. [3] D. Venable, "Stability Testing o Multiloop onverters", Venable Technical Paper #, www.venable.biz/tr-papers2.html. [4] T. H hen, "Dynamic Modeling And ontrol Design O Flyback onverter," IEEE Transactions on Aerospace and Electronic Systems, Vol. 35, No. 4, pp. 23239, Oct. 999. [5] R. Kollman, J. etten, "losing the Loop with a Popular Shunt Regulator," Power Electronics Technology Magazine, pp. 3-36, Sept. 23. [6] R. Kollman, J. etten, "ompensating the (Oten Missed) Inner and Outer ontrol Loops Using the TL43," Power Electronics Technology onerence Proc., Rosemont, Illinois, pp. 366-377, Oct. 22. [7] I. Ozkaynak, "Use o Optocoupler or urrent Mirror to Eliminate L Output Filter Eects in uck-oost Topology," Power Electronics Technology onerence Proc., Rosemont, Illinois, pp. 378-388, Oct. 22. [8].H. Yang, D.Y. hen,. Jamerson, Y.P. Wu, "Stabilizing Magamp ontrol Loop by Using an Inner-Loop ompensation," Applied Power Electronics onerence Proc., pp. 365-372, March 99. [9] I.J. Lee, D.Y. hen,. Jamerson, Y.P. Wu, "Modeling o ontrol Loop ehavior o Magamp Post Regulators," Applied Power Electronics onerence Proc., pp. 365-372, March 99. [] R. W. Erickson, D. Maksimovic, "Fundamentals o Power Electronics," Norwell, MA: Kluwer Academic Publishers. [] J. liss, "Theory and haracteristics o Phototransistors," Motorola Application Note AN-44, Motorola Databook Optoelectronics Device Data, pp. 9.3-93. [2] R.. Ridley, "A New, ontinuous-time Model or urrent-mode ontrol," Power onversion and Intelligence Motion onerence Proc., Long each, A, pp. 455-464, Oct. 989. [3] V. Vorperian, "Simpliied Analysis o PWM onverters Using the Model o the PWM Switch Part I: ontinuous onduction Mode", VPE Seminar Proc., lacksburg, VA, September 989, pp. -9. -783-827-6/4/$7. () 24 IEEE