CS/EE 181a 2010/11 Lecture 1

CS/EE 181a 2010/11 Lecture 1 CS/EE 181 is about designing digital CMOS systems. Functional Specification Approximate domain of CS181 Circuit Specification Simulation Architectural Specification Abstract Geometry ("magic") Extracted netlist Mask Geometry graphics Simulation Physical Mask Testing Chip CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 1

Related Courses APh 9 solid state electronics EE185 fabrication APh 114 solid state physics CS20 CS138 computation algorithms CS185 Asynch VLSI CS139 concurrency CS/EE 181 digital VLSI CS/CNS/EE182 analog VLSI CS/EE 4 digital elec. CS/CNS/EE184 analog lab EE/CS 5x microproc. CS/EE 11 digital lab Is there method to this madness? Or does the designer have to be an expert in all these areas? CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 2

Why CMOS? All we really care about is implementing algorithms in hardware so why digital, synchronous CMOS? There are many alternatives: TTL, NMOS, ECL... Ge, GaAs... currents instead of voltages(?) Analog design Asynchronous Optical, superconducting, quantum Goals: Correctness (most important) High performance speed and/or power (almost as important) CMOS is ideal for achieving our goals with reasonable effort. (And computer scientists love it because it is easy to program. ) CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 3

Abstraction In CMOS, it is not difficult to translate basically any logic equation into reasonably efficient hardware. Architectural Specification Circuit Specification Permits efficient design methodologies that generate circuits correct by construction. But human designers can still intervene & generate Faster, lower-power (i.e., better) circuits More errors... CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 4

Scaling What happens to performance when we scale down the design? Parameter Was Now What happened scale factor 1 1/α linear size x x/α Reduce dimensions voltage V V/α Reduce voltages E-field E E constant E-field current i i/α Reduce currents power vi vi/α 2 (per device) delay τ τ/α Reduce delays energy viτ viτ/α 3! Constant E-field scaling. The circuits get α faster with α 3 less energy. But they still work the same! Plus ça change, plus c est la même chose. (Industrial concerns long kept voltages fixed constantvoltage scaling.) CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 5

Is everything wonderful...? No...! Problem with long wires Delay in short wires: drift of charge carriers in electrical field: t L/E scales with α. Delay in long wires: diffusion of charge carriers: t RCL 2 t remains constant with scaling. Bad news! Long wires become relatively slower...and more capacitive. Problem with power and energy consumption More bad news! Increased PVT variability CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 6

More Abstraction Abstract Geometry Mask Geometry In magic, all our dimensions are in λ. The CMOS scaling properties allow us to abstract away the actual physical dimensions. We can design a circuit once and refabricate it (ideally without functional verification) in a more modern technology... We can think about our systems the same way. So a 2.0- µm Tinychip has more than it might seem in common with a modern 40-nano-m 500-million-transistor microprocessor. CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 7

Trends Scaling has been pursued aggressively since 1970. For the leading chips: 1G 1 Gb DRAM components 256M 16M 16 Mb DRAM DEC AXP 256 Mb DRAM PA 8400 Pentium 4 1M 64K 4K 256 16 Logic Components Memory Processors 1 year 1960 65 1970 75 1980 85 1990 95 2000 Moore s Law. The number of transistors doubles every 18 months...or so. (Moore 1979.) CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 8

Imagine a city with each street as a wire on our chip, 200 m between blocks. (Seitz and Mead, 1979.) 1963 W=50 µm 1 mm 4 km Rose Bowl Caltech Town 1975 W=10 µm 5 mm 100 km 01 00 11 0 01 1 1 0 01 Pasadena Santa Monica 1 Disneyland City 1985 W=2 µm 10 mm 1000 km C A NEV L I F 1995 W=.5 µm 20 mm 8000 km 2000 W=.2 µm 25 mm 2010?? W=.05µm 40 mm CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 9

Where we are today There has been remarkable progress in microelectronics since 1960. Moore s Law has held through the entire period. (How long now...?) Because we can design systems abstractly and because we can scale, the things we can learn from designing a Tinychip are relevant to research and product development in current and future CMOS VLSI technologies. We can use: The same design tools. The same hierarchical design style. The same circuits. And we confront most of the same problems. CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 10

The MOSFET Our basic building block. drain source gate substrate gate substrate source drain The basic building block in CMOS is the MOSFET, of which we use two kinds: n-channel and p-channel. source gate drain channel substrate CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 11

How does it work? The two types of transistors are used in a complementary way. The pfet passes high voltages and the nfet passes low voltages (because of the types of free carriers in the channel). V gs > V T - + gate + + drain source n+ n+ + + p inversion layer (n-type) When enough voltage is applied at the gate terminal, the p-type diffusion between the source and drain is robbed of its holes (they are pushed down) and turns into an n-type semiconductor the reverse biased p-n junctions at the source and drain are bypassed and the MOSFET turns on. CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 12

An inverter Since the nfet conducts low voltages and is turned on by a high voltage (and vice versa for the pfet), CMOS logic is inverting (or antimonotonic). We can build things like inverters: Vdd a not(a) GND CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 13

What CS/EE 181 is not about Some of the topics we will not cover in the class include Industrial design tools Synopsys, Cadence Standard HDLs VHDL, Verilog FPGAs, ASICs CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 14

Next Time One-hour crash course on CMOS circuit design. (If you pay attention, you might not have to come to class again this term!)***written by a TA*** ***Very bad advice*** Transistors and their properties. Noise margins and principles of systematic logic design. magic layout. switch-level simulation with irsim. Other important things to remember: First two homework assignments out; get started early... TA office hours: TBA. Change of schedule: Next time (Wednesday) Magic tutorial in the lab! CS/EE181 Digital VLSI Design Laboratory L1 9/27/10 15