/5/25 22: igital esign equential Logic esign (Latch & FF) A. ahu ept of omp. c. & Engg. Indian Institute of Technology Guwahati Outline ombinational Vs equential Logic esign esign a flip flop, that stores one bit latch tabilizing latch: Level ensitive locked Latch : Flip Flop Edge ensitive,, T flip flops haracterization Table and Equation,, and T Flip flop olution: Ensure, tabilize, tore Level-sensitive latch X L lock Period =2ns locks En Ensure tage Never Happens = tabilize tage When = tabilize and Use when = tore tage tore bit ns ns 2ns 3ns 4ns 5ns 6ns 7ns Time lock period: time interval between pulses lock cycle: one such time interval Freq lock frequency: /period GHz frequency = / 2 ns = 5 MHz MHz Hz = /s MHz Period ns ns ns lock ignal for latch Level-sensitive latch X lock ignals for a Latch How do we know when it s safe to set =? Most common solution make pulse up/down =: afe to change X, =: Must notchange X, locksignal Pulsing signal used to enable latches Because it ticks like a clock equential circuit whose storage components all use clock signals: synchronouscircuit X Level-sensitive latch lk lk
/5/25 Level ensitive Latch latch requires careful design to ensure = never occurs latch relieves designer of that burden Inserted inverter ensures always opposite of latch latch symbol Level ensitive Latches uppose FFs are arrange in linear fashion connected using a single clock signal lk Every clock we want to shift one bit to right ight shift one bit per cycle lk lk_a 2 2 3 3 4 2 3 4 oes this circuit (with level sensitive latch) lk_b hift one bit per cycle? 4 Problem with Level ensitive Latch latch still has problem (as does latch) When =, through how many latches will a signal travel? epends on for how long = lk_a signal may travel through multiple latches lk_b signal may travel through fewer latches Hard to pick that is just the right length lk 2 2 3 3 4 2 3 4 4 Problem with Level ensitive Latch We want do the work: one per clock cycle Independent of length of clock ( time) Is there any solution to this? lk_a lk_b Problem with Level ensitive Latch We want do the work: one per clock cycle Independent of length of clock ( time) anwedesignbitstoragethatonlystoresa storage that only stores a value on the rising edge of a clock signal? There is exactly one rising edge per clock cycle There is exactly one falling edge per clock cycle rising edges Make Edge ensitive Bit torage Latch : Level sensitive storage Flip Flop : Edge sensitive storage Value get changed only at edges of clock How to make a Flip Flop out of Latch? lk 2
/5/25 Master lave Flip Flop Two latches, output of first goes to input of second, master latch has inverted clock signal o master loaded when =, then servant when= When changes from to, master disabled, servant loaded with value that was at just before changed i.e., Value at during rising edge of Master lave Flip Flop Flip flop:stores lk m m latch Master m stores on clock edge, not level flip-flop latch s s s s ervant lk /m m m/s Master loaded when =, then servant when = When changes from to, master disabled, servant loaded with value that was at just before changed i.e., value at during rising edge of s s Flip Flop ( ising & Falling Edges) The triangle means clock input, edge triggered ymbol for rising-edge triggered flip-flop ising edges ymbol for falling-edge triggered flip-flop Internal design: ust invert servant clock rather than master Falling edges Flip Flops olves problem of not knowing through how many latches a signal travels when = ignal travels through exactly one FF, for lk_aor lk_b. Why? Because on rising edge of lk, all four flip flops are loaded simultaneously then all four no longer pay attention to their input, until the next rising edge. oesn t matter how long lkis. 2 2 3 3 4 4 lk lk lk lk_a lk_b Two latches inside each flip-flop Latch vs. Flip Flop Latch is level sensitive: tores when = Flip flop is edge triggered: tores when changes from to aying level sensitive latch, or edge triggered flipflop, is redundant Two types of flip flops rising or falling edge triggered. Positive Edge Triggered Flip Flop: Optimization Master P P lave GATE OUNT: 4 NO, 4 AN and 2 NOT 3
/5/25 emember: Latch with NAN Gates + ** (Unpredictable) Opposite to Latch with NO Gates et will do = and eset will = Positive EgdeTrigeered FF: Economical L Positive Edge Triggered FF: Economical When L=, =, + = (Independent of ) Positive Edge Triggered FF: Economical When L=, =, + = L + = L + = Positive Edge Triggered FF: Economical After that When L=, =: No changes to : + = It locked L + = L Positive EgdeTrigeered FF: Economical GATE OUNT: 6 6 NAN, ame types 4
/5/25 Transistor level optimization is out of syllabus Master lave Edge Triggered Flip Flop 2 x 8 = 6 Transistors MATE LAVE Butshowingtwoslides two slides M L L More Efficient Master lave Edge Triggered Flip Flop alled a 2 MO (locked MO) design L L MATE V GN L L LAVE V GN 8 Transistors Problem handled in esigning FF O Gate : worked just like a ringing bell O gate with Feed back : (= can never be changed) Two NO gates with cross coupled out put and input : olved to store a bit but ace condition Ensure = will not happed by adding Not and AN gate Enable ignal to put remove : delay of added kt Master lave Latches to make a FF Optimized FF (using only NAN Gates) onventions The circuit is setmeans output = The circuit is resetmeans output = Flip flops have two output and ue to time related characteristic of the flip flop: t or : present state t+ or + : next state 2 3 4 Type of Flip Flop Flip Flop : et/eset Flip Flop Flip Flop : ata Flip Flop to store Bit Flip Flop: Unavoidable = state to Toggle (Allinput values areuseful) The Flip Flop was named to honour"ack ilby" of Texas Instrument engineer who invented the concept of I. T Flip Flop: Toggle Flip Flop 5
/5/25 Latches The flip flop augments the behavior of the flip flop (=et, =eset) by interpreting the = = condition as a "flip" or toggle command. FF from + t t + = + Master lave Flip Flop + = + Master lave Flip Flop + = + Flip Flop To synthesize a flip flop, simply set equal to the complement of. The flip flop is a universal flip flop Because it can be configured to work as any FF T flip flop or flip flop or flip flop. =T =T + t t = = + t t = = + t t ==, + = T Toggle Flip Flop: T FF Flip Flop T T Flip Flop + t U 4 Types of Flip Flops + t t + T + t t 6
/5/25 Given a FF: onstruct FF Given a FF: onstruct T FF L + + + + + L T T +T + + = + = T + T Thanks 7