CD5/7HC6A, CD5/7HCT6A Data sheet acquired from Harris Semiconductor SCHSC February 99 - Revised March High-Speed CMOS Logic Phase-Locked-Loop with VCO [ /Title (CD7 HC 6A, CD7 HCT 6A) /Subject (High- Speed CMOS Features Operating Frequency Range - Up to MHz (Typ) at = 5V - Minimum Center Frequency of MHz at Choice of Three Phase Comparators - EXCLUSIVE-OR - Edge-Triggered JK Flip-Flop - Edge-Triggered RS Flip-Flop Excellent VCO Frequency Linearity VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption Minimal Frequency Drift Operating Power Supply Range - VCO Section.......................... 3V to 6V - Digital Section........................ V to 6V Fanout (Over Temperature Range) - Standard Outputs............... LSTTL Loads - Bus Driver Outputs............. 5 LSTTL Loads Wide Operating Temperature Range... -55 o C to 5 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - V to 6V Operation - High Noise Immunity: N IL = 3%, N IH = 3% of at = 5V HCT Types -.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL =.V (Max), V IH = V (Min) - CMOS Input Compatibility, I l µa at V OL, V OH Description The HC6A and HCT6A are high-speed silicon-gate CMOS devices that are pin compatible with the CD6B of the B series. They are specified in compliance with JEDEC standard number 7. The HC6A and HCT6A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC, PC and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 6A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD5HC6AF -55 to 5 6 Ld CERDIP CD5HC6AF3A -55 to 5 6 Ld CERDIP CD7HC6AE -55 to 5 6 Ld PDIP CD7HC6AM -55 to 5 6 Ld SOIC CD7HC6ANSR -55 to 5 6 Ld SOP CD5HCT6AF3A -55 to 5 6 Ld CERDIP CD7HCT6AE -55 to 5 6 Ld PDIP CD7HCT6AM -55 to 5 6 Ld SOIC NOTES:. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Applications FM Modulation and Demodulation Frequency Synthesis and Multiplication Frequency Discrimination Tone Decoding Data Synchronization and Conditioning -to-frequency Conversion Motor-Speed Control CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright, Texas Instruments Incorporated
Pinout CD5HC6A, CD5HCT6A (CERDIP) CD7HC6A (PDIP, SOIC, SOP) CD7HCT6A (PDIP, SOIC) TOP VIEW PCP OUT 6 PC OUT 5 PC3 OUT COMP IN 3 SIG IN VCO OUT 3 PC OUT INH 5 R C A 6 R C B 7 DEM OUT GND 9 VCO IN Functional Diagram COMP IN SIG IN 3 φ 5 3 PC OUT PC3 OUT PC OUT PCP OUT C A C B R R VCO IN INH 6 7 9 5 VCO VCO OUT DEM OUT Pin Descriptions PIN NUMBER SYMBOL NAME AND FUNCTION PCP OUT Phase Comparator Pulse Output PC OUT Phase Comparator Output 3 COMP IN Comparator Input VCO OUT VCO Output 5 INH Inhibit Input 6 C A Capacitor C Connection A 7 C B Capacitor C Connection B GND Ground (V) 9 VCO IN VCO Input DEM OUT Demodulator Output R Resistor R Connection R Resistor R Connection 3 PC OUT Phase Comparator Output SIG IN Signal Input 5 PC3 OUT Phase Comparator 3 Output 6 Positive Supply
C 6 7 3 C A CB VCO OUT COMP IN SIG IN PC OUT R R R V REF -+ VCO S D Q Q R D PC3 OUT 5 R R5 DEM OUT - + - + D Q CP Q R D UP p 3 PC OUT R3 C n D Q GND CP Q R D DOWN INH VCO IN 5 9 PCP OUT FIGURE. LOGIC DIAGRAM General Description VCO The VCO requires one external capacitor C (between C A and C B ) and one external resistor R (between R and GND) or two external resistors R and R (between R and GND, and R and GND). Resistor R and capacitor C determine the frequency range of the VCO. Resistor R enables the VCO to have a frequency offset if required. See logic diagram, Figure. The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin (DEM OUT ). In contrast to conventional techniques where the DEM OUT voltage is one threshold voltage lower than the VCO input voltage, here the DEM OUT voltage equals that of the VCO input. If DEM OUT is used, a load resistor (R S ) should be connected from DEM OUT to GND; if unused, DEM OUT should be left open. The VCO output (VCO OUT ) can be connected directly to the comparator input (COMP IN ), or connected via a frequency-divider. The VCO output signal has a guaranteed duty factor of 5%. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption. Phase Comparators The signal input (SIG IN ) can be directly coupled to the selfbiasing amplifier at pin, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings. Phase Comparator (PC) This is an Exclusive-OR network. The signal and comparator input frequencies (f i ) must have a 5% duty factor to obtain the maximum locking range. The transfer characteristic of PC, assuming ripple (f r = f i ) is suppressed, is: V DEMOUT =( /π) (φsig IN - φcomp IN ) where V DEMOUT is the demodulator output at pin ; V DEMOUT =V PCOUT (via low-pass filter). The average output voltage from PC, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin (V DEMOUT ), is the resultant of the phase differences of signals (SIG IN ) and the comparator input (COMP IN )as shown in Figure. The average of V DEM is equal to / when there is no signal or noise at SIG IN, and with this input the VCO oscillates at the center frequency (f o ). Typical waveforms for the PC loop locked at f o are shown in Figure 3. 3
The frequency capture range (f C ) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (f L )is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration retains lock behavior even with very noisy input signals. Typical of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO center frequency. V DEMOUT = ( /π) (φsig IN - φcomp IN ) where V DE- MOUT is the demodulator output at pin ; V DEMOUT = V PCOUT (via low-pass filter). The average output voltage from PC, fed to the VCO via the low-pass filter and seen at the demodulator output at pin (V DEMOUT ), is the resultant of the phase differences of SIG IN and COMP IN as shown in Figure. Typical waveforms for the PC loop locked at f o are shown in Figure 5. V DEMOUT (AV) / V DEMOUT (AV) / -36 o o φ DEMOUT 36 o o 9 o φ DEMOUT o FIGURE. PHASE COMPARATOR : AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: V DEMOUT = V PCOUT = ( /π) (φsig IN - φcom- P IN ); φ DEMOUT =(φsig IN - φcomp IN ) FIGURE. PHASE COMPARATOR : AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: V DEMOUT = V PCOUT = ( /π) (φsig IN - φcom- P IN ); φ DEMOUT =(φsig IN - φcomp IN ) SIG IN SIG IN COMP IN VCO OUT COMP IN VCO OUT PC OUT VCO IN PCP OUT HIGH IMPEDANCE OFF - STATE GND PC OUT VCO IN FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR, LOOP LOCKED AT f o Phase Comparator (PC) GND This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN are not important. PC comprises two D-type flip-flops, control-gating and a three-state output stage. The circuit functions as an up-down counter (Figure ) where SIG IN causes an up-count and COMP IN a downcount. The transfer function of PC, assuming ripple (f r =f i ) is suppressed, is: FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR, LOOP LOCKED AT f o When the frequencies of SIG IN and COMP IN are equal but the phase of SIG IN leads that of COMP IN, the p-type output driver at PC OUT is held ON for a time corresponding to the phase difference (φ DEMOUT ). When the phase of SIG IN lags that of COMP IN, the n-type driver is held ON. When the frequency of SIG IN is higher than that of COMP IN, the p-type output driver is held ON for most of the input signal cycle time, and for the remainder of the cycle both n- and p-type drivers are OFF (three-state). If the SIG IN frequency is lower than the COMP IN frequency, then it is the n-type driver that is held ON for most of the cycle. Subsequently, the voltage at the capacitor (C) of the low-pass filter connected to PC OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable
point the voltage on C remains constant as the PC output is in three-state and the VCO input at pin 9 is a high impedance. Also in this condition, the signal at the phase comparator pulse output (PCP OUT ) is a HIGH level and so can be used for indicating a locked condition. Thus, for PC, no phase difference exists between SIG IN and COMP IN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both p- and n-type drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIG IN, the VCO adjusts, via PC, to its lowest frequency. Phase Comparator 3 (PC3) This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN are not important. The transfer characteristic of PC3, assuming ripple (f r = f i ) is suppressed, is: V DEMOUT = ( /p) (fsig IN - fcomp IN ) where V DE- MOUT is the demodulator output at pin ; V DEMOUT = V PC3OUT (via low-pass filter). The average output from PC3, fed to the VCO via the lowpass filter and seen at the demodulator at pin (V DE- MOUT), is the resultant of the phase differences of SIG IN and COMP IN as shown in Figure 6. Typical waveforms for the PC3 loop locked at f o are shown in Figure 7. The phase-to-output response characteristic of PC3 (Figure 6) differs from that of PC in that the phase angle between SIG IN and COMP IN varies between o and 36 o and is o at the center frequency. Also PC3 gives a greater voltage swing than PC for input phase differences but as a consequence the ripple content of the VCO input signal is higher. With no signal present at SIG IN, the VCO adjusts, via PC3, to its highest frequency. The only difference between the HC and HCT versions is the input level specification of the INH input. This input disables the VCO section. The comparator s sections are identical, so that there is no difference in the SIG IN (pin ) or COMP IN (pin 3) inputs between the HC and the HCT versions. V DEMOUT (AV) / o o φ DEMOUT 36 o FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: V DEMOUT = V PC3OUT = ( /π) (φsig IN - φcom- P IN ); φ DEMOUT = (φsig IN - φcomp IN ) SIG IN COMP IN VCO OUT PC3 OUT VCO IN GND FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 3, LOOP LOCKED AT f o 5
Absolute Maximum Ratings DC Supply,........................ -.5V to 7V DC Input Diode Current, I IK For V I < -.5V or V I > +.5V......................±mA DC Output Diode Current, I OK For V O < -.5V or V O > +.5V....................±mA DC Drain Current, per Output, I O For -.5V < V O < +.5V..........................±5mA DC Output Source or Sink Current per Output Pin, I O For V O > -.5V or V O < +.5V....................±5mA DC or Ground Current, I CC.........................±5mA Thermal Information Package Thermal Impedance, θ JA (see Note 3): PDIP Package..................................67 o C/W SOIC Package..................................73 o C/W SOP Package................................. 6 o C/W Maximum Junction Temperature....................... 5 o C Maximum Storage Temperature Range..........-65 o C to 5 o C Maximum Lead Temperature (Soldering s)............. 3 o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A...................... -55 o C to 5 o C Supply Range, HC Types.....................................V to 6V HCT Types..................................5V to 5.5V DC Input or Output, V I, V O................. V to Input Rise and Fall Time V...................................... ns (Max).5V...................................... 5ns (Max) 6V....................................... ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. The package thermal impedance is calculated in accordance with JESD 5-7. DC Electrical Specifications PARAMETER HC TYPES VCO SECTION INH High Level Input INH Low Level Input VCO OUT High Level Output CMOS Loads VCO OUT High Level Output TTL Loads VCO OUT Low Level Output CMOS Loads VCO OUT Low Level Output TTL Loads CA, CB Low Level Output (Test Purposes Only) SYMBOL TEST CONDITIONS 5 o C - o C TO 5 o C -55 o C TO 5 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH - - 3. - -. -. - V.5 3.5 - - 3.5-3.5 - V 6. - -. -. - V V IL - - 3 - -.9 -.9 -.9 V.5 - -.35 -.35 -.35 V 6 - -. -. -. V V OH V IH or V IL -. 3.9 - -.9 -.9 - V -..5. - -. -. - V -. 6 5.9 - - 5.9-5.9 - V UNITS - - - - - - - - - V -.5 3.9 - - 3. - 3.7 - V -5. 6 5. - - 5.3-5. - V V OL V IH or V IL. - -. -. -. V..5 - -. -. -. V. 6 - -. -. -. V - - - - - - - - - V.5 - -.6 -.33 -. V 5. 6 - -.6 -.33 -. V V OL V IL or V IH.5 - -. -.7 -.5 V 5. 6 - -. -.7 -.5 V 6
DC Electrical Specifications (Continued) PARAMETER INH VCO IN Input Leakage Current I I or GND - 6 - - ±. - ± - ± µa R Range (Note ) - - -.5 3-3 - - - - kω R Range (Note ) - - -.5 3-3 - - - - kω C Capacitance - - - 3 - - No - - - - pf Range.5 - - Limit - - - - pf 6 - - - - - - pf VCO IN Operating Range - Over the range specified for R for Linearity See Figure, and 35-3 (Note 5) 3. -.9 - - - - V.5. - 3. - - - - V 6. -.6 - - - - V PHASE COMPARATOR SECTION SIG IN, COMP IN V IH - -.5 - -.5 -.5 - V DC Coupled High-Level Input.5 3.5 - - 3.5-3.5 - V 6. - -. -. - V SIG IN, COMP IN V IL - - - -.5 -.5 -.5 V DC Coupled Low-Level Input.5 - -.35 -.35 -.35 V 6 - -. -. -. V PCP OUT, PCn OUT V OH V IL or V IH -..9 - -.9 -.9 - V High-Level Output.5. - -. -. - V CMOS Loads 6 5.9 - - 5.9-5.9 - V PCP OUT, PCn OUT V OH V IL or V IH -.5 3.9 - - 3. - 3.7 - V High-Level Output TTL Loads -5. 6 5. - - 5.3-5. - V PCP OUT, PCn OUT Low-Level Output CMOS Loads PCP OUT, PCn OUT Low-Level Output TTL Loads SIG IN, COMP IN Input Leakage Current PC OUT Three-State Off-State Current SIG IN, COMP IN Input Resistance SYMBOL V OL V IL or V IH. - -. -. -. V.5 - -. -. -. V 6 - -. -. -. V V OL V IL or V IH.5 - -.6 -.33 -. V 5. 6 - -.6 -.33 -. V I I or GND - - - ±3 - ± - ±5 µa 3 - - ±7 - ±9 - ± µa.5 - - ± - ±3 - ±9 µa 6 - - ±3 - ±3 - ±5 µa I OZ V IL or V IH - 6 - - ±.5 - ±5 - ± µa R I V I at Self-Bias Operation Point: V I,.5V, See Figure DEMODULATOR SECTION Resistor Range R S at R S > 3kΩ Leakage Current Can Influence V DEMOUT TEST CONDITIONS 5 o C - o C TO 5 o C -55 o C TO 5 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS 3 - - - - - - kω.5-5 - - - - - kω 6-5 - - - - - kω 3 5-3 - - - - kω.5 5-3 - - - - kω 6 5-3 - - - - kω 7
DC Electrical Specifications (Continued) PARAMETER Offset VCO IN V OFF V I = V VCO IN = 3 - ±3 - - - - - mv to V DEM.5 - ± - - - - - mv Values Taken Over R S Range See Figure 6 - ± - - - - - mv Dynamic Output R D V DEMOUT = 3-5 - - - - - Ω Resistance at DEM OUT.5-5 - - - - - Ω 6-5 - - - - - Ω Quiescent Device Current HCT TYPES VCO SECTION INH High Level Input INH Low Level Input VCO OUT High Level Output CMOS Loads VCO OUT High Level Output TTL Loads VCO OUT Low Level Output CMOS Loads VCO OUT Low Level Output TTL Loads CA, CB Low Level Output (Test Purposes Only) INH VCO IN Input Leakage Current I CC Pins 3, 5 and at Pin 9 at GND, I at Pins 3 and to be excluded V IH - -.5 to 5.5 V IL - -.5 to 5.5 6 - - - - 6 µa - - - - V - -. -. -. V V OH V IH or V IL -..5. - -. -. - V -.5 3.9 - - 3. - 3.7 - V V OL V IH or V IL..5 - -. -. -. V.5 - -.6 -.33 -. V V OL V IH or V IL.5 - -. -.7 -.5 V I I Any Between and GND 5.5 - ±. - ± - ± µa R Range (Note ) - - -.5 3-3 - - - - kω R Range (Note ) - - -.5 3-3 - - - - kω C Capacitance Range VCO IN Operating Range PHASE COMPARATOR SECTION SIG IN, COMP IN DC Coupled High-Level Input SYMBOL TEST CONDITIONS 5 o C - o C TO 5 o C -55 o C TO 5 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX - - -.5 - No Limit - Over the range specified for R for Linearity See Figure, and 35-3 (Note 5) V IH - -.5 to 5.5 UNITS - - - - pf.5. - 3. - - - - V - - - - V
DC Electrical Specifications (Continued) PARAMETER SIG IN, COMP IN DC Coupled Low-Level Input PCP OUT, PCn OUT High-Level Output CMOS Loads PCP OUT, PCn OUT High-Level Output TTL Loads PCP OUT, PCn OUT Low-Level Output CMOS Loads PCP OUT, PCn OUT Low-Level Output TTL Loads SIG IN, COMP IN Input Leakage Current PC OUT Three-State Off-State Current SIG IN, COMP IN Input Resistance V IL - -.5 to 5.5 - -. -. -. V V OH V IL or V IH -.5. - -. -. - V V OH V IL or V IH -.5 3.9 - - 3. - 3.7 - V V OL V IL or V IH -.5 - -. -. -. V V OL V IL or V IH -.5 - -.6 -.33 -. V I I Any Between and GND - 5.5 - - ±3 ±3 ±5 µa I OZ V IL or V IH - 5.5 - - ±.5 ±5 - - ± µa R I V I at Self-Bias Operation Point: V I,.5V, See Figure DEMODULATOR SECTION Resistor Range R S at R S > 3kΩ Leakage Current Can Influence V DEM OUT.5-5 - - - - - kω.5 5-3 - - - - kω Offset VCO IN.5 - ± - - - - - mv to V DEM V OFF V I = V VCO IN = Values taken over R S Range See Figure Dynamic Output Resistance at DEM OUT R D V DEM OUT =.5-5 - - - - - Ω Quiescent Device Current Additional Quiescent Device Current Per Input Pin: Unit Load SYMBOL I CC I CC Note 6 TEST CONDITIONS 5 o C - o C TO 5 o C -55 o C TO 5 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX or GND -. Excluding Pin 5-5.5 - - - - 6 µa -.5 to 5.5-36 - 5-9 µa NOTES:. The value for R and R in parallel should exceed.7kω. 5. The maximum operating voltage can be as high as -.9V, however, this may result in an increased offset voltage. 6. For dual-supply systems theoretical worst case (V I =.V, = 5.5V) specification is.ma. UNITS 9
HCT Input Loading Table INPUT UNIT LOADS INH NOTE: Unit load is I CC limit specific in DC Electrical Specifications Table, e.g., 36µA max. at 5 o C. Switching Specifications C L = 5pF, Input t r, t f = 6ns TEST CONDITIONS 5 o C - o C TO 5 o C -55 o C TO 5 o C PARAMETER SYMBOL (V) MIN TYP MAX MIN MAX MIN MAX HC TYPES PHASE COMPARATOR SECTION Propagation Delay t PLH, t PHL SIG IN, COMP IN to PCI OUT - - - 5-3 ns.5 - - - 5-6 ns 6 - - 3-3 - 5 ns SIG IN, COMP IN to PCP OUT - - 3-375 - 5 ns.5 - - 6-75 - 9 ns 6 - - 5-6 - 77 ns SIG IN, COMP IN to PC3 OUT - - 5-35 - 37 ns.5 - - 9-6 - 7 ns 6 - - - 5-63 ns Output Transition Time t THL, t TLH - - 75-95 - ns.5 - - 5-9 - ns 6 - - 3-6 - 9 ns Output Enable Time, SIG IN, t PZH, t PZL - - 65-33 - ns COMP IN to PC OUT.5 - - 53-66 - ns 6 - - 5-56 - 6 ns Output Disable Time, SIG IN, t PHZ, t PLZ - - 35-395 - 75 ns COMP IN to PC OUT.5 - - 63-79 - 95 ns 6 - - 5-67 - ns AC Coupled Input Sensitivity ( P- V I(P-P) 3 - - - - - - mv P ) at SIG IN or COMP IN.5-5 - - - - - mv 6-33 - - - - - mv VCO SECTION Frequency Stability with Temperature Change f T R = kω, R = Maximum Frequency f MAX C = 5pF R = 3.5kΩ R = C = pf R = 9.kΩ R = UNITS 3 - - TYP - - %/ o C.5 - -. - - %/ o C 6 - - - - %/ o C 3 - - - - - - MHz.5 - - - - - - MHz 6 - - - - - - MHz 3-3 - - - - - MHz.5-3 - - - - - MHz 6-3 - - - - - MHz
Switching Specifications C L = 5pF, Input t r, t f = 6ns (Continued) PARAMETER Center Frequency C = pf R = 3kΩ R = VCO IN = VCC/ Frequency Linearity f VCO R = kω R = C = pf Offset Frequency DEMODULATOR SECTION V OUT V S f IN R = kω C = nf R = kω R = C = pf R S = kω R 3 = kω C = pf 3 7 - - - - - MHz.5 7 - - - - - MHz 6 - - - - - MHz 3 -. - - - - - %.5 -. - - - - - % 6 -. - - - - - % 3 - - - - - - khz.5 - - - - - - khz 6 - - - - - - khz 3 - - - - - - - mv/khz.5-33 - - - - - mv/khz 6 - - - - - - - mv/khz HCT TYPES PHASE COMPARATOR SECTION Propagation Delay t PHL, t PLH SIG IN, COMP IN to PCI OUT C L = 5pF.5 - - 5-56 - 6 ns SIG IN, COMP IN to PCP OUT t PHL, t PLH C L = 5pF.5 - - 6-5 - ns SIG IN, COMP IN to PC3 OUT t PHL, t PLH C L = 5pF.5 - - 5-73 - 7 ns Output Transition Time t TLH, t THL C L = 5pF.5 - - 5-9 - ns Output Enable Time, SIG IN, COMP IN to PC OUT t PZH, t PZL C L = 5pF.5 - - 6-75 - 9 pf Output Disable Time, SIG IN, t PHZ, t PLZ C L = 5pF.5 - - 6-5 - pf COMP IN to PCZ OUT AC Coupled Input Sensitivity V I(P-P) 3 - - - - - - mv ( P-P ) at SIG IN or COMP IN.5-5 - - - - - mv 6-33 - - - - - mv VCO SECTION Frequency Stability with Temperature Change f T R = kω, R = Maximum Frequency f MAX C = 5pF R = 3.5kΩ R = Center Frequency SYMBOL TEST CONDITIONS C = pf R = 9.kΩ R = C = pf R = 3kΩ R = VCO IN = VCC/ (V) 5 o C - o C TO 5 o C -55 o C TO 5 o C MIN TYP MAX MIN MAX MIN MAX UNITS.5 -. - - - - - %/ o C.5 - - - - - - MHz.5-3 - - - - - MHz 3 7 - - - - - MHz.5 7 - - - - - MHz 6 - - - - - MHz
Switching Specifications C L = 5pF, Input t r, t f = 6ns (Continued) PARAMETER Frequency Linearity f VCO R = kω R = C = pf Offset Frequency DEMODULATOR SECTION V OUT V S f IN SYMBOL TEST CONDITIONS R = kω C = nf R = kω R = C = pf R S = kω R 3 = kω C = pf (V) 5 o C - o C TO 5 o C -55 o C TO 5 o C MIN TYP MAX MIN MAX MIN MAX UNITS.5 -. - - - - - %.5 - - - - - - khz.5-33 - - - - - mv/khz Test Circuits and Waveforms SIG IN COMP IN INPUTS V S SIG IN INPUTS V S PCP OUT PC OUT PC3 OUT OUTPUTS t TLH t PHL V S t PHL t TLH COMP IN INPUTS PC OUT OUTPUT t PZH V S t PZH 9% V S t PZL t PZL % FIGURE. INPUT TO OUTPUT PROPAGATION DELAYS AND OUTPUT TRANSITION TIMES FIGURE 9. THREE STATE ENABLE AND DISABLE TIMES FOR PC OUT Typical Performance Curves I I 7 V I R MIN OR R MIN (OHMS) 6 5 3 SELF-BIAS OPERATING POINT FIGURE. TYPICAL INPUT RESISTANCE CURVE AT SIG IN, COMP IN V I 3 5 6 SUPPLY VOLTAGE, (V) FIGURE. HC/HCT6A R (MIN) OR R (MIN) vs SUPPLY VOLTAGE ( )
Typical Performance Curves (Continued) CENTER FREQUENCY (Hz) 7 6 5 R =.K R = K R = K R =.M R = M CENTER FREQUENCY (Hz) 7 6 5 R =3K R = 3K R =33K R = 3M R = 5M VCO IN =.5 5 6 VCO IN =.5 = 6.V 5 6 CAPACITANCE, C (pf) CAPACITANCE, C (pf) FIGURE. HC6A TYPICAL CENTER FREQUENCY vs R, C () FIGURE 3. HC6A TYPICAL CENTER FREQUENCY vs R, C ( = 6V) CENTER FREQUENCY (Hz) 7 6 5 R =.5K R = 5K R = 5K R =.5M R = 7.5M VCO IN =.5 = 3.V R = OPEN 5 6 CENTER FREQUENCY (Hz) 7 6 5 R =.K R = K R = K R =.M R = M VCO IN =.5 5 6 CAPACITANCE, C (pf) CAPACITANCE, C (pf) FIGURE. HC6A TYPICAL CENTER FREQUENCY vs R, C ( = 3V, R = OPEN) CENTER FREQUENCY (Hz) 7 6 5 VCO IN =.5 = 5.5V 5 6 CAPACITANCE, C (pf) R = 3K R = 3K R = 3K R = 3M R = 5M FIGURE 6. HCT6A TYPICAL CENTER FREQUENCY vs R, C ( = 5.5V) FIGURE 5. HCT6A TYPICAL CENTER FREQUENCY vs R, C () VCO FREQUENCY (khz) 6 R =.5M = 3V = 6V 3 5 6 VCO IN (V) FIGURE 7. HC6A TYPICAL VCO FREQUENCY vs VCO IN (R =.5MΩ, ) 3
Typical Performance Curves (Continued) 9 C =.µf R =.5M = 6V 7 C =.µf R = 5K = 6V VCO FREQUENCY (Hz) 7 6 5 3 = 3V VCO FREQUENCY (Hz) 6 5 3 = 3V 3 5 6 VCO IN (V) FIGURE. HC6A TYPICAL VCO FREQUENCY vs VCO IN (R =.5MΩ, C =.µf) 3 5 6 VCO IN (V) FIGURE 9. HC6A TYPICAL VCO FREQUENCY vs VCO IN (R = 5kΩ, C =.µf) VCO FREQUENCY (khz) 6 6 C =.µf R = 5.6k = 3V = 6V VCO FREQUENCY (khz) 6 R = 5K = 3V = 6V 3 5 6 VCO IN (V) FIGURE. HC6A TYPICAL VCO FREQUENCY vs VCO IN (R = 5.6kΩ, C =.µf) 3 5 6 VCO IN (V) FIGURE. HC6A TYPICAL VCO FREQUENCY vs VCO IN (R = 5kΩ, ) VCO FREQUENCY (MHz) 6 R = 5.6K = 3V = 6V VCO FREQUENCY CHANGE, f (%) 6 - - - VCO IN =.5, = 3V R = OPEN R =.5M R =.5K R = 5K R = 3K 3 5 6-6 -75-5 -5 5 5 75 5 5 VCO IN (V) AMBIENT TEMPERATURE, T A ( o C) FIGURE. HC6A TYPICAL VCO FREQUENCY vs VCO IN (R = 5.6kΩ, ) FIGURE 3. HC6A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R ( = 3V)
Typical Performance Curves (Continued) VCO FREQUENCY CHANGE, f (%) 6 - - VCO IN =.5, R = OPEN R =.M R =.K R = K - -75-5 -5 5 5 75 5 5 AMBIENT TEMPERATURE, T A ( o C) VCO FREQUENCY CHANGE, f (%) 6 - - - VCO IN =.5, = 6.V R = OPEN R = 3M R = 3K R = 3K -75-5 -5 5 5 75 5 5 AMBIENT TEMPERATURE, T A ( o C) FIGURE. HC6A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R () FIGURE 5. HC6A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R ( = 6V) VCO FREQUENCY CHANGE, f (%) 6 - - VCO IN =.5, = 5.5V R = OPEN R = 3M R = 3K R = 3K VCO FREQUENCY CHANGE, f (%) 6 - - VCO IN =.5, R = OPEN R =.M R =.K R = K - -75-5 -5 5 5 75 5 5 AMBIENT TEMPERATURE, T A ( o C) FIGURE 6. HCT6A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R - -75-5 -5 5 5 75 5 5 AMBIENT TEMPERATURE, T A ( o C) FIGURE 7. HC6A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R () 5
Typical Performance Curves (Continued) 7 7 OFFSET FREQUENCY (Hz) 6 5 R =.K R = K R = K R =.M OFFSET FREQUENCY (Hz) 6 5 R =.5K R = 5K R = 5K R =.5M VCO IN =.5 R = M 5 6 CAPACITANCE, C (pf) FIGURE. HC6A OFFSET FREQUENCY vs R, C () VCO IN =.5 = 3V R = 7.5M 5 6 CAPACITANCE, C (pf) FIGURE 9. HC6A OFFSET FREQUENCY vs R, C ( = 3V) 7 7 OFFSET FREQUENCY (Hz) 6 5 R =.K R = K R = K R =.M VCO IN =.5 R = M 5 6 OFFSET FREQUENCY (Hz) 6 5 R = 3K R = 3K R = 3K R = 3M VCO IN =.5 HC = 6V HCT = 5.5V R = 5M 5 6 CAPACITANCE, C (pf) CAPACITANCE, C (pf) FIGURE 3. HCT6A OFFSET FREQUENCY vs R, C () FIGURE 3. HC6A AND HCT6A OFFSET FREQUENCY vs R, C ( = 6V, = 5.5V) PIN 9 =.95 FOR f MAX PIN 9 = V FOR f MIN = 3V,.5V, 6V PIN 9 =.95 FOR f MAX PIN 9 = V FOR f MIN TO 5.5V f MAX /f MIN f MAX /f MIN - - R/R - - R/R FIGURE 3. HC6A f MIN /f MAX vs R/R ( = 3V,.5V, 6V) FIGURE 33. HCT6A f MAX /f MIN vs R/R ( TO 5.5V) 6
Typical Performance Curves (Continued) f 6 R = OPEN VCO IN =.5V ± V f f f f V V V =.5V OVER THE RANGE: FOR VCO LINEARITY f o = f + f LINEARITY = f o - f o f x % o LINEARITY (%) - - -6 VCO IN =.5V ±.5V MIN / MAX V VCOIN - K K K M M R (OHMS) FIGURE 3. DEFINITION OF VCO FREQUENCY LINEARITY FIGURE 35. HC6A VCO LINEARITY vs R () LINEARITY (%) 6 - = 3V R = OPEN VCO IN =.5V ±.V VCO IN =.5V ±.3V LINEARITY (%) 6 - = 6V R = OPEN VCO IN = 3V ±.5V - -6 - -6 VCO IN = 3V ±.6V - K K K M M R (OHMS) - K K K M M R (OHMS) FIGURE 36. HC6A VCO LINEARITY vs R ( = 3V) FIGURE 37. HC6A VCO LINEARITY vs R ( = 6V) LINEARITY (%) 6 - - -6 = 5.5V, VCO IN =.75V ±.3V, VCO IN =.5V ±.V = 5.5V, VCO IN =.75V ±.55V, VCO IN =.5V ±.5V R = OPEN - K K K M M R (OHMS) DEMODULATOR POWER DISSIPATION, P D (µw) VCO IN =.5 = 3V = 6V K K K M RS (OHMS) FIGURE 3. HCT6A VCO LINEARITY vs R (, = 5.5V) FIGURE 39. HC6A DEMODULATOR POWER DISSIPATION vs RS (TYP) ( = 3V,.5V, 6V) 7
Typical Performance Curves (Continued) DEMODULATOR POWER DISSIPATION, P D (µw) VCO IN =.5 R = R = OPEN = 3V = 6V K K K M RS (OHMS) VCO POWER DISSIPATION, P D (µw) 6 5 VCO IN =.5 R = RS = OPEN C L = 5pF = 3V C = µf = 6V = 3V C = µf = 6V C = µf K K K M R (OHMS) FIGURE. HCT6A DEMODULATOR POWER DISSIPATION vs RS (TYP) ( = 3V,.5V, 6V) FIGURE. HC6A VCO POWER DISSIPATION vs R (, µf) VCO POWER DISSIPATION, P D (µw) 6 5 = 6V C = µf = 6V C = µf VCO IN = V (AT f MIN ) R = RS = OPEN C L = 5pF VCO POWER DISSIPATION, P D (µw) 6 5 = 5.5V C = µf = 5.5V C = µf VCO IN =.5V R = RS = OPEN K K K M R (OHMS) FIGURE. HCT6A VCO POWER DISSIPATION vs R (, µf) K K K M R (OHMS) FIGURE 3. HCT6A VCO POWER DISSIPATION vs R (, µf) VCO POWER DISSIPATION, P D (µw) 6 5 = 3V C = µf = 3V = 6V C = µf VCO IN = V (AT f MIN ) R = RS = OPEN C L = 5pF = 6V C = µf K K K M R (OHMS) FIGURE. HC6A VCO POWER DISSIPATION vs R (, µf)
HC/HCT6A C PD CHIP SECTION HC HCT UNIT Comparator 5 pf Comparators and 3 39 pf References should be made to Figures through 6 and Figures through 33 as indicated in the table. Values of the selected components should be within the following ranges: VCO 6 53 pf R Between 3kΩ and 3kΩ Application Information This information is a guide for the approximation of values of external components to be used with the HC6A and HCT6A in a phase-lock-loop system. R R + R C Between 3kΩ and 3kΩ Parallel Value >.7kΩ Greater Than pf SUBJECT VCO Frequency Without Extra Offset PHASE COMPARATOR PC, PC or PC3 DESIGN CONSIDERATIONS VCO Frequency Characteristic With R = and R within the range 3kΩ < R < 3kΩ, the characteristics of the VCO operation will be as shown in Figures - 6. (Due to R, C time constant a small offset remains when R =.) f MAX f VCO f o f L f MIN MIN / V VCOIN MAX FIGURE 5. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT OFFSET: f o = CENTER FREQUENCY: f L = FREQUENCY LOCK RANGE VCO Frequency with Extra Offset PC Selection of R and C Given f o, determine the values of R and C using Figures - 6. PC or PC3 Given f MAX calculate f o as f MAX / and determine the values of R and C using Figures - 6. To obtain f L :f L. ( -.V)/(RC) where valid range of VCO IN is.v < VCO IN < -.9V PC, PC or PC3 VCO Frequency Characteristic With R and R within the ranges 3kΩ < R < 3kΩ,3kΩ, < R < 3kΩ, the characteristics of the VCO operation will be as shown in Figures - 33. f MAX f VCO fo f L f MIN MIN / V VCOIN MAX FIGURE 6. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET: f o = CENTER FREQUENCY: f L = FREQUENCY LOCK RANGE PC, PC or PC3 Selection of R, R and C Given f o and f L, offset frequency, f MIN, may be calculated from f MIN f o -.6 f L. Obtain the values of C and R by using Figures - 3. Calculate the values of R from Figures 3-33. 9
SUBJECT PLL Conditions with No Signal at the SIG IN Input PLL Frequency Capture Range PHASE COMPARATOR PC VCO adjusts to f o with φ DEMOUT = 9 o and V VCOIN = / (see Figure ) PC VCO adjusts to f MIN with φ DEMOUT = -36 o and V VCOIN = V (see Figure ) PC3 VCO adjusts to f MAX with φ DEMOUT = 36 o and V VCOIN = (see Figure 6) PC, PC or PC3 Loop Filter Component Selection R3 DESIGN CONSIDERATIONS F (jω) INPUT C OUTPUT -/ τ ω (A) τ = R3 x C (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM A small capture range (f c ) is obtained if τ > f c /π (πf L /τ.) / FIGURE 7. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET R3 INPUT R C OUTPUT F (jω) m m = R R3 + R -/ τ -/ τ3 / τ3 / τ ω (A) τ = R3 x C; (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM τ = R x C; τ3 = (R3 + R) x C PLL Locks on Harmonics at Center Frequency Noise Rejection at Signal Input AC Ripple Content when PLL is Locked PC or PC3 PC PC PC or PC3 PC PC PC3 FIGURE. SIMPLE LOOP FILTER FOR PLL WITH OFFSET Yes No High Low f r = f i, large ripple content at φ DEMOUT = 9 o f r = f i, small ripple content at φ DEMOUT = o f r = fsig IN, large ripple content at φ DEMOUT = o
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