a FEATURES Excellent Speed:. V/ms Typ Fast Settling (.%): ms Typ Unity-Gain Stable High-Gain Bandwidth: MHz Typ Low Input Offset Voltage: mv Max Low Offset Voltage Drift: mv/ C Max High Gain: V/mV Min Outstanding CMR: db Min Industry Standard -Pin Dual Pinout Available in Die Form High-Speed, Dual Operational Amplifier OP PIN CONNECTIONS IN A +IN A NC V NC +IN B IN B NC OUT A NC NC V+ NC NC OUT B 9 NC GENERAL DESCRIPTION The OP is a unity-gain stable monolithic dual op amp featuring excellent speed,. V/ms typical, and fast settling time, ms typical to. %. The OP has a gain bandwidth of MHz with a high phase margin of. Input offset voltage of the OP is under mv with input offset voltage drift below mv/ C, guaranteed over the full military temperature range. Open-loop gain exceeds, into a kw load ensuring outstanding gain accuracy and linearity. The input bias current is under na limiting errors due to source resistance. The OP s outstanding CMR, over db, and low PSRR, under. mv/v, reduce NC = NO CONNECT -Pin SOL (S-Suffix) OUT A IN A +IN A A B + + V+ OUT B IN B V +IN B errors caused by ground noise and power supply fluctuations. In addition, the OPl exhibits high CMR and PSRR over a wide frequency range, further improving system accuracy. Epoxy Mini-DIP (P-Suffix) -Pin Hermetic DIP (Z-Suffix) V+ BIAS OUT IN +IN V Figure. Simplified Schematic (One of the two amplifiers is shown.) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: /9- www.analog.com Fax: /- Analog Devices, Inc.,
OP SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V S = ± V, T A = C, unless otherwise noted.) OPA/E OPF OPG Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE V OS mv INPUT OFFSET CURRENT I OS V CM = V na INPUT BIAS CURRENT I B V CM = V na INPUT NOISE VOLTAGE DENSITY e n f O = khz... nv/hz LARGE-SIGNAL V O = ± V VOLTAGE A VO R L = kw V/mV GAIN R L = kw V/mV INPUT VOLTAGE RANGE IVR ± ±. ± ±. ± ±. V OUTPUT VOLTAGE SWING V O R L kw ± ± ± ± ± ± V COMMON-MODE REJECTION CMR V CM = ± V 9 db POWER SUPPLY REJECTION PSRR V S = ±. V...... mv/v RATIO to ± V SLEW RATE SR...... V/ms PHASE MARGIN u m A V = + degrees SUPPLY CURRENT (ALL AMPLIFIERS) I SY No Load..... ma GAIN BANDWIDTH PRODUCT GBW MHz CHANNEL CS V O = V p-p db SEPARATION f O = Hz db INPUT CAPACITANCE C IN pf INPUT RESISTANCE DIFFERENTIAL- MODE R IN... MW INPUT RESISTANCE COMMON MODE R INCM GW SETTLING TIME t S AV = +, V Step to.% ms NOTES Guaranteed by CMR test. Guaranteed but not % tested.
ELECTRICAL CHARACTERISTICS OPA Parameter Symbol Conditions Min Typ Max Unit INPUT OFFSET VOLTAGE V OS mv AVERAGE INPUT OFFSET VOLTAGE DRIFT TCV OS. mv/ C INPUT OFFSET CURRENT I OS V CM = V. na INPUT BIAS CURRENT IB V CM = V na LARGE-SIGNAL VOLTAGE A VO V O = ± V GAIN R L = kw V/mV R L = kw V/mV INPUT VOLTAGE RANGE IVR ± ±. V OUTPUT VOLTAGE SWING V O R L kw ± ± V COMMON-MODE REJECTION CMR V CM = ± V db POWER SUPPLY REJECTION RATIO PSRR V S = ±. V to ± V.. mv/v SUPPLY CURRENT (ALL AMPLIFIERS) I SY No Load. ma NOTE Guaranteed by CMR test. ELECTRICAL CHARACTERISTICS OP OPA/E OPF OPG Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE V OS mv AVERAGE INPUT OFFSET VOLTAGE DRIFT TCV OS.. mv/ C INPUT OFFSET CURRENT I OS V CM = V na INPUT BIAS CURRENT I B V CM = V na LARGE-SIGNAL A VO V O = ± V VOLTAGE GAIN R L = kw V/mV R L = kw 9 V/mV INPUT VOLTAGE RANGE IVR ± ±. ± ±. ± ±. V OUTPUT VOLTAGE SWING V O R L kw ± ± ± ± ± ± V COMMON-MODE REJECTION CMR V CM = ± V 9 9 db POWER SUPPLY REJECTION PSRR V S = ±. V.... mv/v RATIO to ± V SUPPLY CURRENT (ALL AMPLIFIERS) I SY No Load...... ma NOTE Guaranteed by CMR test. (V S = ± V, C T A C for OPA, unless otherwise noted.) (V S = ± V, C T A + C, unless otherwise noted.)
OP (Continued from Page ) The OP offers outstanding dc and ac matching between channels. This is especially valuable for applications such as multiple gain blocks, high-speed instrumentation and amplifiers, buffers and active filters. The OP conforms to the industry standard, -pin dual op amp pinout. It is pin compatible with the TL, TL, LF, and / dual op amps and can be used to significantly improve systems using these devices. For applications requiring lower voltage noise, see the OP. For a quad version of the OP, see the OP. ABSOLUTE MAXIMUM RATINGS Supply Voltage............................... ± V Differential Input Voltage...................... ±. V Differential Input Current.................... ± ma Input Voltage......................... Supply Voltage Output Short-Circuit Duration.............. Continuous Storage Temperature Range............ C to + C Lead Temperature (Soldering, sec)............ C Junction Temperature (Tj)............. C to + C Operating Temperature Range OPA........................... C to + C OPE, OPF, OPG........... C to + C ORDERING GUIDE Package T A = C Operating V OS Max CERDIP Temperature (mv) -Pin Plastic Range *OPAZ MIL *OPEZ XND *OPFZ XND OPGP XND *OPGS XND *Not for new design, obsolete April. Package Type ja jc Unit -Pin Hermetic DIP (Z) C/W -Pin Plastic DIP (P) 9 C/W -Pin SOIC (S) 9 C/W NOTES Absolute maximum ratings apply to packaged parts, unless otherwise noted. The OP s inputs are protected by back-to-back diodes. Current limiting resistors are not used in order to achieve low-noise performance. If differential voltage exceeds ±. V, the input current should be limited to ± ma. ja is specified for worst case mounting conditions, i.e., ja is specified for device in socket for CERDIP and P-DIP packages; ja is specified for device soldered to printed circuit board for SOIC package. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE
Typical Performance Characteristics OP VOLTAGE NOISE DENSITY nv/ Hz /f CORNER = Hz VOLTAGE NOISE DENSITY nv/ Hz AT Hz AT khz TOTAL HARMONIC DISTORTION %. TA = C V O = V p-p R L = k. A V = A V = A V = k TPC. Voltage Noise Density vs. SUPPLY VOLTAGE Volts TPC. Voltage Noise Density vs. Supply Voltage. k k TPC. Total Harmonic Distortion vs. CURRENT NOISE DENSITY pa/ Hz.. /f CORNER = Hz INPUT OFFSET VOLTAGE V CHANGE IN OFFSET VOLTAGE V 9. k k TEMPERATURE C TIME Minutes TPC. Current Noise Density vs. TPC. Input Offset Voltage vs. Temperature TPC. Warm-Up Offset Voltage Drift INPUT BIAS CURRENT na V CM = V INPUT OFFSET CURRENT na INPUT BIAS CURRENT na TEMPERATURE C TEMPERATURE C..... COMMON MODE VOLTAGE Volts. TPC. Input Bias Current vs. Temperature TPC. Input Offset Current vs. Temperature TPC 9. Input Bias Current vs. Common-Mode Voltage
OP CMR db 9 k k k TPC. CMR vs. M TOTAL SUPPLY CURRENT ma T A = + C T A = + C T A = C SUPPLY VOLTAGE Volts TPC. Total Supply Current vs. Supply Voltage TOTAL SUPPLY CURRENT ma TEMPERATURE C TPC. Total Supply Current vs. Temperature PSR db +PSR PSR OPEN-LOOP GAIN db CLOSED-LOOP GAIN db k k k M M M TPC. PSR vs. k k k M M M TPC. Open-Loop Gain vs. k k k M TPC. Closed-Loop Gain vs. M OPEN-LOOP GAIN db PHASE GAIN PHASE MARGIN = C PHASE SHIFT DEG OPEN-LOOP GAIN V/mV R L = k PHASE MARGIN DEG GBW m GAIN-BANDWIDTH PRODUCT MHz FREQUENCY MHz TPC. Open-Loop Gain, Phase Shift vs. SUPPLY VOLTAGE Volts TPC. Open-Loop Gain vs. Supply Voltage TEMPERATURE C TPC. Gain-Bandwidth Product, Phase Margin vs. Temperature
OP PEAK-TO-PEAK AMPLITUDE Volts k k k M THD = % R L = k M TPC 9. Maximum Output Swing vs. MAXIMUM OUTPUT Volts POSITIVE SWING NEGATIVE SWING k k LOAD RESISTANCE TPC. Maximum Output Voltage vs. Load Resistance OUTPUT IMPEDANCE A V = A V = k k k M M TPC. Output Impedance vs. SLEW RATE V/ S 9 +SR SR TEMPERATURE C TPC. Slew Rate vs. Temperature CHANNEL SEPARATION db 9 9 k k k M M TPC. Channel Separation vs. A V = + A V = + V s mv ns TPC. Large-Signal Transient Response TPC. Small Signal Transient Response
OP APPLICATION INFORMATION Capacitive Load Driving and Power Supply Considerations The OP is unity-gain stable and is capable of driving large capacitive loads without oscillating. Nonetheless, good supply bypassing is highly recommended. Proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the OP. In the standard feedback amplifier, the op amp s output resistance combines with the load capacitance to form a low-pass filter that adds phase shift in the feedback network and reduces stability. A simple circuit to eliminate this effect is shown in Figure. The added components, C and R, decouple the amplifier from the load capacitance and provide additional stability. The values of C and R shown in Figure are for a load capacitance of up to pf when used with the OP. V+ C F + When R f > k, a pole created by R f and the amplifier s input capacitance ( pf) creates additional phase shift and reduces phase margin. A small capacitor in parallel with R f helps eliminate this problem. Computer Simulations Many electronic design and analysis programs include models for op amps which calculate AC performance from the location of poles and zeros. As an aid to designers utilizing such a program, major poles and zeros of the OP are listed below. Their location will vary slightly between production lots. Typically, they will be within % of the frequency listed. Use of this data will enable the designer to evaluate gross circuit performance quickly, but should not supplant rigorous characterization of a breadboard circuit. POLES ZEROS Hz. MHz. MHz X MHz X MHz - X MHz - V IN R R OP V C. F R R V OUT C C L F pf + The low phase error amplifier performs second-order frequency C. F C pf PLACE SUPPLY DECOUPLING CAPACITORS AT OP Figure. Driving Large Capacitive Loads Unity-Gain Buffer Applications When R f and the input is driven with a fast, large-signal pulse (> V), the output waveform will look as shown in Figure. During the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input, and a current, limited only by the output short-circuit protection, will be drawn by the signal generator. With R f, the output is capable of handling the current requirements (I L ma at V); the amplifier will stay in its active mode and a smooth transition will occur. APPLICATIONS Low Phase Error Amplifier The simple amplifier depicted in Figure, utilizes a monolithic dual operational amplifier and a few resistors to substantially reduce phase error compared to conventional amplifier designs. At a given gain, the frequency range for a specified phase accuracy is over a decade greater than for a standard single op amp amplifier. compensation through the response of op amp A in the feedback loop of A. Both op amps must be extremely well matched in frequency response. At low frequencies, the A feedback loop forces V /(K + )=V IN. The A feedback loop forces V O /V IN =K +. The DC gain is determined by the resistor divider around A. Note that, like a conventional single op amp amplifier, the DC gain is set by resistor ratios only. Minimum gain for the low phase error amplifier is. V IN R K / OPE A / OPE A R R V R = R R K OP.V/ s ASSUME: A AND A ARE MATCHED. A O (s) = s V O V O = (K +) V IN Figure. Low Phase Error Amplifier Figure. Pulsed Operation
OP PHASE SHIFT DEG. SINGLE OP AMP, CONVENTIONAL DESIGN CASCADED (TWO STAGES) LOW PHASE ERROR AMPLIFIER...... FREQUENCY RATIO / / Figure. Phase Error Comparison Figure compares the phase error performance of the low phase error amplifier with a conventional single op amp amplifier and a cascaded two-stage amplifier. The low phase error amplifier shows a much lower phase error, particularly for frequencies where T <.. For example, phase error of -. occurs at. T for the single op amplifier, but at. T for the low phase error amplifier. For more detailed information on the low phase error amplifier, see Application Note AN-. Dual -Bit Voltage Output DAC The dual voltage output DAC shown in Figure will settle to -bit accuracy from zero to full scale in s typically. The CMOS DAC- utilizes a -bit, double-buffered input structure allowing faster digital throughput and minimizing digital feedback. Fast Current Pump Maximum output current of the fast current pump shown in Figure is ma. Voltage compliance exceeds V with V supplies. The current pump has an output resistance of over M and maintains -bit linearity over its entire output range. V IN R k R k R k / OPFZ R k +V / OPFZ R I OUT ma I OUT = V IN V = IN =ma/v RS V Figure. Fast Current Pump +V F V. F V REFERENCE VOLTAGE DAC-EW V DD R FB A pf V REF A I OUT A DAC A -BIT DATABUS PINS AGND / OPEZ + V OUT A V. F F DAC CONTROL 9 V REF B DAC B DAC A/DAC B LDAC WR DGND I OUT B R FB B pf / OPEZ + V OUT B Figure. Dual -Bit Voltage Output DAC 9
OP OUTLINE DIMENSIONS -Lead Ceramic Dip-Glass Hermetic Seal [CERDIP] (Q-) Dimensions shown in inches and (millimeters) -Lead Plastic Dual-in-Line Package [PDIP] (N-) Dimensions shown in inches and (millimeters) PIN. (.) MAX. (.). (.). (.). (.). (.) MIN. (.) MAX. (.). (.9). (.) BSC. (.9) MAX. (.). (.). (.). (.). (.) MIN SEATING PLANE. (.).9 (.). (.). (.) CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. (.) MAX. (9.). (9.). (9.).9 (.9). (.). (.9). (.) BSC. (.) MIN. (.). (.) SEATING PLANE. (.9). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.) COMPLIANT TO JEDEC STANDARDS MO-9AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) -Lead Standard Small Outline Package [SOIC] Narrow Body (RN-) Dimensions shown in millimeters and (inches). (.9). (.9). (.). (.9). (.). (.). (.9). (.) COPLANARITY.. (.) BSC SEATING PLANE. (.). (.). (.). (.). (.9).9 (.). (.9). (.99). (.). (.) COMPLIANT TO JEDEC STANDARDS MS-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
OP Revision History Location Page / Data Sheet changed from REV. to. Deleted PIN CONNECTIONS Caption...................................................................... Edits to ORDERING GUIDE.............................................................................. Edits to ABSOLUTE MAXIMUM RATINGS................................................................. Edits to Figure........................................................................................ 9 Updated OUTLINE DIMENSIONS.......................................................................
C--/(A) PRINTED IN U.S.A.