Data Sheet Compact, 8 ma, 3 MHz, Step-Down DC-to-DC Converter ADP38/ADP39 FEAURES Input voltage:.3 V to 5.5 V Peak efficiency: 95% 3 MHz fixed frequency operation ypical quiescent current: μa Very small solution size 6-lead, mm.5 mm WLCSP package Fast load and line transient response % duty cycle low dropout mode Internal synchronous rectifier, compensation, and soft start Current overload and thermal shutdown protections Ultralow shutdown current:. μa (typical) Forced PWM and automatic PWM/PSM modes Supported by ADIsimPower design tool APPLICAIONS PDAs and palmtop computers Wireless handsets Digital audio, portable media players Digital cameras, GPS navigation units GENERAL DESCRIPION he ADP38 and ADP39 are high efficiency, low quiescent current, synchronous step-down dc-to-dc converters. he ADP39 has the additional feature of an internal discharge switch. he total solution requires only three tiny external components. When the MODE pin is set high, the buck regulator operates in forced PWM mode, which provides low peak-to-peak ripple for power supply noise sensitive loads at the expense of light load efficiency. When the MODE pin is set low, the buck regulator automatically switches operating modes, depending on the load current level. At higher output loads, the buck regulator operates in PWM mode. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving light load efficiency. he ADP38/ADP39 operate on input voltages of.3 V to 5.5 V, which allows for single lithium or lithium polymer cell, multiple alkaline or NiMH cell, PCMCIA, USB, and other standard power sources. he maximum load current of 8 ma is achievable across the input voltage range. he ADP38/ADP39 are available in fixed output voltages of 3.3 V, 3. V,.8 V,.5 V,.8 V,.5 V,. V,. V, and.8 V. All versions include an internal power switch and synchronous rectifier for minimal external part count and high efficiency. he ADP38/ADP39 have internal soft start and they are internally compensated. During logic controlled shutdown, the input is disconnected from the output and the ADP38/ADP39 draw. μa (typical) from the input source. Other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current overshoot at startup. he ADP38/ADP39 are available in a 6-ball wafer level chip scale package (WLCSP). YPICAL APPLICAIONS CIRCUI.3V O 5.5V.µH V OU VIN.7µF ADP38/.7µF ADP39 ON OFF EN VOU FORCE PWM AUO MODE GND Figure. 996- Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. rademarks and registered trademarks are the property of their respective owners. One echnology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. el: 78.39.7 3 Analog Devices, Inc. All rights reserved. echnical Support www.analog.com
ADP38/ADP39 ABLE OF CONENS Features... Applications... General Description... ypical Applications Circuit... Revision History... Specifications... 3 Input and Output Capacitor, Recommended Specifications.. 3 Absolute Maximum Ratings... hermal Resistance... ESD Caution... Pin Configuration and Function Descriptions... 5 ypical Performance Characteristics... 6 heory of Operation... Control Scheme... PWM Mode... Power Save Mode... Enable/Shutdown... Data Sheet Short-Circuit Protection... Undervoltage Lockout... hermal Protection... Soft Start... Current Limit... % Duty Operation... Discharge Switch... Applications Information... 3 ADIsimPower Design ool... 3 External Component Selection... 3 hermal Considerations... PCB Layout Guidelines...... 5 Layout... 5 Outline Dimensions... 6 Ordering Guide... 7 REVISION HISORY /3 Rev. B to Rev. C Change to Figure 8, Caption... 8 Change to Figure 8, Caption... 6/ Rev. A to Rev. B Change to Features Section... Added ADIsimPower Design ool Section... 3 Changes to Ordering Guide... 7 / Rev. to Rev. A Change to Features Section... Added Figure 3, Renumbered Figures Sequentially... Changes to Ordering Guide... 6 / Revision : Initial Version Rev. C Page of
Data Sheet ADP38/ADP39 SPECIFICAIONS VIN = 3.6 V, V OU =.8 V 3.3 V, J = C to +5 C for minimum/maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). able. Parameter est Conditions/Comments Min yp Max Unit INPU CHARACERISICS Input Voltage Range.3 5.5 V Undervoltage Lockout hreshold VIN rising.3 V OUPU CHARACERISICS VIN falling..5.5 V Output Voltage Accuracy PWM mode + % Line Regulation VIN =.3 V to 5.5 V, PWM mode.5 %/V Load Regulation ILOAD = ma 8 ma.95 %/A PWM O POWER SAVE MODE CURREN HRESHOLD ma INPU CURREN CHARACERISICS DC Operating Current ILOAD = ma, device not switching 3 3 μa Shutdown Current EN = V, A = J = C to +85 C.. μa CHARACERISICS On Resistance PFE 55 mω NFE 5 mω Current Limit PFE switch peak current limit 5 65 ma Discharge Switch (ADP39) Ω ENABLE AND MODE CHARACERISICS Input High hreshold. V Input Low hreshold. V Input Leakage Current EN/MODE = V (min), 3.6 V (max ) + μa OSCILLAOR FREQUENCY.6 3. 3. MHz SAR-UP IME 5 μs HERMAL CHARACERISICS hermal Shutdown hreshold 5 C hermal Shutdown Hysteresis C INPU AND OUPU CAPACIOR, RECOMMENDED SPECIFICAIONS A = C to +5 C, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). able. Parameter Symbol Min yp Max Unit MINIMUM INPU AND OUPU CAPACIANCE CMIN.7 µf CAPACIOR ESR RESR. Ω Rev. C Page 3 of
ADP38/ADP39 ABSOLUE MAXIMUM RAINGS able 3. Parameter Rating VIN, EN, MODE. V to +6.5 V VOU, to GND. V to (VIN +. V) emperature Range Operating Ambient C to +85 C Operating Junction C to +5 C Storage emperature 65 C to +5 C Lead emperature Range 65 C to +5 C Soldering ( sec) 3 C Vapor Phase (6 sec) 5 C Infrared (5 sec) C ESD Model Human Body ±5 V Charged Device ±5 V Machine ± V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HERMAL DAA Absolute maximum ratings apply individually only, not in combination. ADP38/ADP39 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (J) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit for as long as the junction temperature is within specification limits. he junction temperature (J) of the device is dependent on the ambient temperature (A), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θja). Maximum junction temperature (J) is calculated from the ambient temperature (A) and power dissipation (PD) using the formula J = A + (PD θja) Data Sheet Junction-to-ambient thermal resistance (θja) of the package is based on modeling and calculation using a -layer board. he junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. he value of θja may vary, depending on PCB material, layout, and environmental conditions. he specified values of θja are based on a -layer, in. 3 in., circuit board. Refer to JEDEC JESD 5-9 for detailed information pertaining to board construction. For additional information, see AN-67 Application Note, MicroCSP M Wafer Level Chip Scale Package. ΨJB is the junction-to-board thermal characterization parameter measured in units of C/W. ΨJB of the package is based on modeling and calculation using a -layer board. he JESD5-, Guidelines for Reporting and Using Package hermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than through a single path, which is the procedure for measuring thermal resistance, θjb. herefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package; factors that make ΨJB more useful in real-world applications than θjb. Maximum junction temperature (J) is calculated from the board temperature (B) and power dissipation (PD) using the formula J = B + (PD ΨJB) Refer to JEDEC JESD5-8 and JESD5- for more detailed information about ΨJB. HERMAL RESISANCE θja and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. able. hermal Resistance Package ype θja ΨJB Unit 6-Ball WLCSP 7 8 C/W ESD CAUION Rev. C Page of
Data Sheet ADP38/ADP39 PIN CONFIGURAION AND FUNCION DESCRIPIONS VIN GND 3 EN MODE 5 VOU 6 OP VIEW (BALL SIDE DOWN) Not to Scale Figure. Pin Configuration (op View) 996- able 5. Pin Function Descriptions Pin No. Mnemonic Description VIN Power Source Input. VIN is the source of the PFE high-side switch. Bypass VIN to GND with a.7 μf or greater capacitor as close to the ADP38/ADP39 as possible. Switch Node Output. is the drain of the P-channel MOSFE switch and N-channel synchronous rectifier. Connect the output LC filter between and the output voltage. 3 GND Ground. Connect the input and output capacitors to GND. EN Buck Activation. o turn on the buck, set EN to high. o turn off the buck, set EN to low. 5 MODE Mode Input. Drive the MODE pin high for the operating mode to force continuous PWM switching. Drive the MODE pin low to allow automatic PWM/PSM operating mode. 6 VOU Output Voltage Sensing Input. Rev. C Page 5 of
ADP38/ADP39 Data Sheet YPICAL PERFORMANCE CHARACERISICS VIN = 3.6 V, A = 5 C, VEN = VIN, unless otherwise noted. 9 9 8 8 7 7 EFFICIENCY (%) 6 5 EFFICIENCY (%) 6 5 3 3 V IN =.3V V IN = 3.6V V IN =.V V IN = 5.5V... I OU (A) 996-3 V IN =.3V V IN = 3.6V V IN =.V V IN = 5.5V... I OU (A) 996-6 Figure 3. Efficiency vs. Load Current, Across Input Voltage, VOU =.8 V, PSM Mode Figure 6. Efficiency vs. Load Current, Across Input Voltage, VOU =.8 V, PWM Mode 9 9 8 8 7 7 EFFICIENCY (%) 6 5 EFFICIENCY (%) 6 5 3 3 V IN =.3V V IN = 3.6V V IN =.V V IN = 5.5V V IN = 3.9V V IN =.V V IN = 5.5V... I OU (A) 996-... I OU (A) 996-7 Figure. Efficiency vs. Load Current, Across Input Voltage, VOU =.8 V, PWM Mode Figure 7. Efficiency vs. Load Current, Across Input Voltage, VOU = 3.3 V, PSM Mode 9 9 8 8 7 7 EFFICIENCY (%) 6 5 EFFICIENCY (%) 6 5 3 3 V IN =.3V V IN = 3.6V V IN =.V V IN = 5.5V V IN = 3.9V V IN =.V V IN = 5.5V... I OU (A) 996-5... I OU (A) 996-8 Figure 5. Efficiency vs. Load Current, Across Input Voltage, VOU =.8 V, PSM Mode Figure 8. Efficiency vs. Load Current, Across Input Voltage, VOU = 3.3 V, PWM Mode Rev. C Page 6 of
Data Sheet ADP38/ADP39 V OU A (V).85.85.85.795 V IN =.3V V IN = 3.6V V IN =.V V IN = 5.5V FREQUENCY (MHz) 3.5 3. 3.3 3. 3. 3..9.8 C +5 C +85 C +5 C.785.7.6.775...3..5.6.7.8 I OU (A) Figure 9. Load Regulation Across Input Voltage, VOU =.8 V, PWM Mode V OU A (V).85.8.85.8.795.79.785 V IN =.3V V IN = 3.6V V IN =.V V IN = 5.5V.78...3..5.6.7.8 I OU (A) Figure. Load Regulation Across Input Voltage, VOU =.8 V, PWM Mode 996-9 996- FREQUENCY (MHz).5...3..5.6.7 I OU (A) Figure. Frequency vs. Output Current, Across emperature, VOU =.8 V, PWM Mode 3.5 3. 3.3 3. 3. 3..9.8.7.6.5 V IN =.3V V IN = 3.6V V IN =.V V IN = 5.5V...3..5.6.7 I OU (A) Figure 3. Frequency vs. Output Current, Across Supply Voltage, VOU =.8 V 996-996-3 V OU A (V) 3.378 3.358 3.338 3.38 3.98 3.78 3.58 V IN = 3.9V V IN =.V V IN = 5.5V OUPU VOLAGE (mv) 9 8 7 6 5 3 I OU = µa I OU = 5mA I OU = 5mA 3.38 3.8...3..5.6.7.8 I OU (A) Figure. Load Regulation Across Input Voltage, VOU = 3.3 V, PWM Mode 996-.3.8 3.3 3.8.3.8 5.3 INPU VOLAGE (V) Figure. Output Voltage Ripple vs. Input Voltage, Across Output Current, VOU =.8 V 996-3 Rev. C Page 7 of
ADP38/ADP39 Data Sheet 35 3 C +5 C +5 C 5 V OU R DSON (mω) 5 I OU 5.3.8 3.3 3.8.3.8 5.3 INPU VOLAGE (V) Figure 5. RDSON PFE vs. Input Voltage, Across emperature 996-36 CH mv CH 5mA Ω CH 5.V M.µs A CH 5mA 6.% Figure 8. Response to Load ransient, 5 ma to 5 ma, VOU =.8 V, Automatic Mode 996-5 5 C +5 C +5 C R DSON (mω) 5 V OU I OU 5.3.8 3.3 3.8.3.8 5.3 INPU VOLAGE (V) Figure 6. RDSON NFE vs. Input Voltage, Across emperature 996-37 CH mv CH 5mA Ω CH 5.V M.µs A CH 5mA 6.% Figure 9. Response to Load ransient, 5 ma to 5 ma, VOU =.8 V, PWM Mode 996-6 V OU V OU I OU I OU CH mv CH 5mA Ω CH 5.V M.µs A CH 5mA 6.% 996- CH mv CH ma Ω M.µs A CH 3mA CH 5.V 6.% 996-7 Figure 7. Response to Load ransient, 5 ma to 5 ma, VOU =.8 V, PWM Mode Figure. Response to Load ransient, 5 ma to ma, VOU =.8 V, Automatic Mode Rev. C Page 8 of
Data Sheet ADP38/ADP39 V IN V OU I OU V OU 3 CH mv CH 5mA Ω CH 5.V M.µs A CH 75mA 6.% Figure. Response to Load ransient, 5 ma to 5 ma, VOU = 3.3 V, PWM Mode 996-8 CH.mV CH3.V M.µs A CH3.5V 8.µs Figure. Response to Line ransient, VOU =.8 V, VIN =. V to.8 V, PWM Mode 996- V IN V OU I OU V OU 3 CH mv CH ma Ω CH 5.V M.µs A CH ma 6.% Figure. Response to Load ransient, 5 ma to ma, VOU = 3.3 V, Automatic Mode 996-9 CH.mV CH3.V M.µs A CH3.5V 8.µs Figure 5. Response to Line ransient, VOU =.8 V, VIN =. V to.8 V, PWM Mode 996-33 V IN I IN 3 V OU 3 V OU E N CH.mV CH3.V M.µs A CH3.5V 8.µs Figure 3. Response to Line ransient, VOU = 3.3 V, VIN =. V to.8 V, PWM Mode 996- CH.V Ω CH3 5.V CH 5mA Ω M.µs A CH3.5V CH 5.V.% Figure 6. Startup, VOU =.8 V, IOU = ma 996- Rev. C Page 9 of
ADP38/ADP39 Data Sheet I IN I L V OU V OU 3 E N CH.V Ω CH3 5.V CH 5mA Ω M.µs A CH3.5V CH 5.V.% Figure 7. Startup, VOU =.8 V, IOU = ma 996-3 CH.mVΩ CH 5mA Ω CH.V M.µs 5.% A CH.3V Figure 3. ypical Waveform, VOU =.8 V, PWM Mode, IOU = ma 996-6 V OU I IN MODE 3 V OU 3 E N CH 5.V Ω CH3 5.V CH 5mA Ω M.µs A CH3.5V CH 5.V.% Figure 8. Startup, VOU = 3.3 V, IOU = ma 996- CH mv CH3.V CH.V M.µs A CH3.36V 9.6% Figure 3. Mode ransition from PSM to PWM to PSM, VOU =.8 V 996-35 CH.mVΩ I L V OU CH 5mA Ω CH.V M.µs A CH 5.% 3.8mV Figure 9. ypical Waveform, VOU =.8 V, PSM Mode, IOU = ma 996-5 V OU RIPPLE (mv) 3 9.8V, V IN = 5.5V, AUO.8V, V IN = 3.6V, AUO.8V, V IN =.3V, AUO.8V, V IN = 5.5V, PWM.8V, V IN = 3.6V, PWM.8V, V IN =.3V, PWM 8 7 6 5 3... I OU (A) Figure 3. VOU Peak-to-Peak Ripple vs. Output Current, VOU =.8 V 996- Rev. C Page of
Data Sheet ADP38/ADP39 HEORY OF OPERAION GM ERROR AMP PWM COMP SOF SAR VIN VOU I LIMI PSM COMP PWM/ PSM CONROL LOW CURREN MODE OSCILLAOR UNDERVOLAGE LOCK OU ADP38 he ADP38 and ADP39 are step-down dc-to-dc converters that use a fixed frequency and high speed current-mode architecture. he high switching frequency and tiny 6-ball WLCSP package allow for a small step-down dc-to-dc converter solution. he ADP38/ADP39 operate with an input voltage of.3 V to 5.5 V, and regulate an output voltage down to.8 V. CONROL SCHEME he ADP38/ADP39 operate with a fixed frequency, currentmode PWM control architecture at medium to high loads for high efficiency, but shift to a power save mode control scheme at light loads to lower the regulation power losses. When operating in PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in power save mode at light loads, the output voltage is controlled in a hysteretic manner, with higher VOU ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. Each ADP38/ADP39 has a MODE pin, which determines the operation of the buck regulator in either PWM mode (when the MODE pin is set high) or power save mode (when the mode pin is set low). PWM MODE In PWM mode, the ADP38/ADP39 operate at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, the PFE switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFE switch and turns on the NFE synchronous rectifier. his sends a negative voltage across the inductor, causing the inductor current to decrease. he synchronous rectifier stays on for the rest of the cycle. EN DRIVER AND ANISHOO HROUGH HERMAL SHUDOWN Figure 33. ADP38 Functional Block Diagram Rev. C Page of GND he ADP38/ADP39 regulate the output voltage by adjusting the peak inductor current threshold. POWER SAVE MODE he ADP38/ADP39 smoothly transition to the power save mode of operation when the load current decreases below the power save mode current threshold. When the ADP38 and ADP39 enter power save mode, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately.5% above the PWM regulation level, PWM operation turns off. At this point, both power switches are off, and the ADP38/ ADP39 enter into idle mode. COU discharges until VOU falls to the PWM regulation voltage, at which point the device drives the inductor to cause VOU to rise again to the upper threshold. his process is repeated for as long as the load current is below the power save mode current threshold. Power Save Mode Current hreshold he power save mode current threshold is set to ma. he ADP38/ADP39 employ a scheme that enables this current to remain accurately controlled, independent of VIN and VOU levels. his scheme also ensures that there is very little hysteresis between the power save mode current threshold for entry to and exit from the power save mode. he power save mode current threshold is optimized for excellent efficiency across all load currents. ENABLE/SHUDOWN he ADP38/ADP39 start operating with soft start when the EN pin is toggled from logic low to logic high. Pulling the EN pin low forces the device into shutdown mode, reducing the shutdown current to. μa (typical). 996-7
ADP38/ADP39 SHOR-CIRCUI PROECION he ADP38/ADP39 include frequency fold back to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. he reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. UNDERVOLAGE LOCKOU o protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated on the ADP38/ADP39. If the input voltage drops below the.5 V UVLO threshold, the ADP38/ADP39 shut down, and both the power switch and the synchronous rectifier turn off. When the voltage rises above the UVLO threshold, the soft start period is initiated, and the part is enabled. HERMAL PROECION In the event that the ADP38/ADP39 junction temperature rises above 5 C, the thermal shutdown circuit turns off the converter. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A C hysteresis is included so that when thermal shutdown occurs, the ADP38/ADP39 do not return to operation until the on-chip temperature drops below 3 C. When coming out of thermal shutdown, soft start is initiated. SOF SAR he ADP38/ADP39 have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. his prevents Data Sheet possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. After the EN pin is driven high, internal circuits begin to power up. Start-up time in the ADP38/ADP39 is the measure of when the output is in regulation after the EN pin is driven high. Start-up time consists of the power-up time and the soft start time. CURREN LIMI Each ADP38/ADP39 has protection circuitry to limit the amount of positive current flowing through the PFE switch and the synchronous rectifier. he positive current limit on the power switch limits the amount of current that can flow from the input to the output. he negative current limit prevents the inductor current from reversing direction and flowing out of the load. % DUY OPERAION With a drop in VIN or with an increase in ILOAD, the ADP38/ ADP39 reach a limit where, even with the PFE switch on % of the time, VOU drops below the desired output voltage. At this limit, the ADP38/ADP39 smoothly transition to a mode where the PFE switch stays on % of the time. When the input conditions change again and the required duty cycle falls, the ADP38/ADP39 immediately restart PWM regulation without allowing overshoot on VOU. DISCHARGE ICH he ADP39 has an integrated switched resistor (of typically Ω) to discharge the output capacitor when the EN pin goes low or when the device enters undervoltage lockout or thermal shutdown. he time to discharge is typically μs. GM ERROR AMP PWM COMP SOF SAR VIN VOU I LIMI PSM COMP PWM/ PSM CONROL LOW CURREN MODE OSCILLAOR UNDER-VOLAGE LOCK OU ADP39 EN DRIVER AND ANISHOO HROUGH HERMAL SHUDOWN Figure 3. ADP39 Functional Block Diagram GND 996-8 Rev. C Page of
Data Sheet APPLICAIONS INFORMAION ADIsimPower DESIGN OOL he ADP38/ADP39 is supported by ADIsimPower design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. he tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating conditions and limitations of the IC and all real external components. For more information about ADIsimPower design tools, refer to www.analog.com/adisimpower. he tool set is available from this website, and users can also request an unpopulated board through the tool. EXERNAL COMPONEN SELECION rade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure. Inductor he high switching frequency of the ADP38/ADP39 allows for the selection of small chip inductors. For best performance, use inductor values between.7 μh and 3 μh. Recommended inductors are shown in able 6. he peak-to-peak inductor current ripple is calculated using the following equation: I RIPPLE VOU ( VIN = V f IN V L OU where: f is the switching frequency. L is the inductor value. he minimum dc current rating of the inductor must be greater than the inductor peak current. he inductor peak current is calculated using the following equation: I RIPPLE I PEAK = I LOAD( MAX) + Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal DCR. Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the ADP38/ADP39 are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low electromagnetic interference (EMI). ) able 6. Suggested. μh Inductors Dimensions Vendor Model (mm) ADP38/ADP39 ISA (ma) DCR (mω) Murata LQMMPNRNGB..6.9 85 LQM8PNR.6.8.33 7 5 aiyo Yuden CBMF68RM.6.8.8 9 9 EPL-ML... 9 59 Coilcraft DK GLFR68RM-LR.6.8.8 36 8 63LS-.8.7. 8 Coilcraft oko MD5-CN.5.. 8 Output Capacitor Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. he worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COU ( EMPCO) ( OL) where: CEFF is the effective capacitance at the operating voltage. EMPCO is the worst-case capacitor temperature coefficient. OL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (EMPCO) over C to +85 C is assumed to be 5% for an X5R dielectric. he tolerance of the capacitor (OL) is assumed to be %, and COU is.66 μf at.8 V, as shown in Figure 35. Substituting these values in the equation yields CEFF =.66 μf (.5) (.) = 3.956 μf o guarantee the performance of the ADP38/ADP39, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Rev. C Page 3 of
ADP38/ADP39 Data Sheet CAPACIANCE (µf) 6 5 3 3 5 6 DC BIAS VOLAGE (V) Figure 35. ypical Capacitor Performance he peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: V RIPPLE = V IN ( π f ) L COU I = 8 f RIPPLE C OU Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: VRIPPLE ESRCOU I RIPPLE he effective capacitance needed for stability, which includes temperature and dc bias effects, is 3 µf. able 7. Suggested.7 μf Capacitors Vendor ype Model Case Size Murata X5R GRM88R6J75 63 6.3 aiyo Yuden X5R JMK7BJ75 63 6.3 Coilcraft DK X5R C68X5RJ75 63 6.3 Input Capacitor 996-9 Voltage Rating (V) Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: I CIN I LOAD( MAX) V OU ( V V IN IN V o minimize supply noise, place the input capacitor as close to the VIN pin of the ADP38/ADP39 as possible. As with the output capacitor, a low ESR capacitor is recommended. he list of recommended capacitors is shown in able 8. able 8. Suggested.7 μf Capacitors Vendor ype Model OU ) Case Size Murata X5R GRM88R6J75 63 6.3 aiyo Yuden X5R JMK7BJ75 63 6.3 Coilcraft DK X5R C68X5RJ75 63 6.3 Voltage Rating (V) HERMAL CONSIDERAIONS Because of the high efficiency of the ADP38/ADP39, only a small amount of power is dissipated inside the ADP38/ADP39 package, which reduces thermal constraints. However, in applications with maximum loads at high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is great enough that it may cause the junction temperature of the die to exceed the maximum junction temperature of 5 C. If the junction temperature exceeds 5 C, the converter enters thermal shutdown. It recovers when the junction temperature falls below 3 C. he junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: J = A + R where: J is the junction temperature. A is the ambient temperature. R is the rise in temperature of the package due to power dissipation. he rise in temperature of the package is directly proportional to the power dissipation in the package. he proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: R = θja PD where: R is the rise in temperature of the package. θja is the thermal resistance from the junction of the die to the ambient temperature of the package. PD is the power dissipation in the package. PCB LAYOU GUIDELINES Poor layout can affect ADP38/ADP39 performance, causing EMI and electromagnetic compatibility problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. o implement a good layout, use the following rules: Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. hese components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and node to minimize noise and magnetic interference. Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Rev. C Page of
Data Sheet ADP38/ADP39 EVALUAION BOARD B VIN B EN CIN.7µF EN VIN 3 5 VIN GND EN MODE U VOU L µh 6 COU.7µF B3 VOU B6 MODE 5 GND IN B GND OU 996-3 Figure 36. Schematic EVALUAION BOARD LAYOU 996-3 996-3 Figure 37. op Layer Figure 38. Bottom Layer Rev. C Page 5 of
ADP38/ADP39 Data Sheet OULINE DIMENSIONS.7.3.99 BALL A IDENIFIER.55.55.65. REF A B.6.595.55 OP VIEW (BALL SIDE DOWN) SIDE VIEW.37.355.3.5 REF COPLANARIY.5.5 REF BOOM VIEW (BALL SIDE UP) C SEAING PLANE.3.3.3.7.. Figure 39. 6-Ball Wafer Level Chip Scale Package [WLCSP] (CB-6-) Dimensions shown in millimeters 8---A Rev. C Page 6 of
Data Sheet ADP38/ADP39 ORDERING GUIDE Model emperature Range Output Voltage (V) Package Description Package Option ADP38ACBZ-.8-R7 C to +5 C.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LJH ADP38ACBZ-.-R7 C to +5 C. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L88 ADP38ACBZ-.-R7 C to +5 C. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L89 ADP38ACBZ-.5-R7 C to +5 C.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L8A ADP38ACBZ-.8-R7 C to +5 C.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L8C ADP38ACBZ-.5-R7 C to +5 C.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L93 ADP38ACBZ-.8-R7 C to +5 C.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LDH ADP38ACBZ-3.-R7 C to +5 C 3. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LDJ ADP38ACBZ-3.3-R7 C to +5 C 3.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LDP ADP39ACBZ-.8-R7 C to +5 C.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LJJ ADP39ACBZ-.-R7 C to +5 C. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LHN ADP39ACBZ-.-R7 C to +5 C. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LHP ADP39ACBZ-.5-R7 C to +5 C.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LHQ ADP39ACBZ-.8-R7 C to +5 C.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LHR ADP39ACBZ-.5-R7 C to +5 C.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LHS ADP39ACBZ-.8-R7 C to +5 C.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LH ADP39ACBZ-3.-R7 C to +5 C 3. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LHU ADP39ACBZ-3.3-R7 C to +5 C 3.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LHV ADP38CB-.8EVALZ ADP38CB-.EVALZ ADP38CB-.EVALZ ADP38CB-.5EVALZ ADP38CB-.8EVALZ ADP38CB-.5EVALZ ADP38CB-.8EVALZ ADP38CB-3.EVALZ ADP38CB-3.3EVALZ ADP39CB-.8EVALZ ADP39CB-.EVALZ ADP39CB-.EVALZ ADP39CB-.5EVALZ ADP39CB-.8EVALZ ADP39CB-.5EVALZ ADP39CB-.8EVALZ ADP39CB-3.EVALZ ADP39CB-3.3EVALZ Z = RoHS Compliant Part. Branding Rev. C Page 7 of
ADP38/ADP39 Data Sheet NOES Rev. C Page 8 of
Data Sheet ADP38/ADP39 NOES Rev. C Page 9 of
ADP38/ADP39 Data Sheet NOES 3 Analog Devices, Inc. All rights reserved. rademarks and registered trademarks are the property of their respective owners. D996--/3(C) Rev. C Page of