FDS9AS Dual N-Ch PowerTrench SyncFET General Description The FDS9AS is designed to replace two single SO- MOSFETs and Schottky diode in synchronous DC:DC power supplies that provide various peripheral voltages for notebook computers and other battery powered electronic devices. FDS9AS contai two unique 3V, N-channel, logic level, PowerTrench MOSFETs designed to maximize power conversion efficiency. The high-side switch () is designed with specific emphasis on reducing switching losses while the lowside switch () is optimized to reduce conduction losses. also includes an integrated Schottky diode using Fairchild s monolithic SyncFET technology. Features May 25 : Optimized to minimize conduction losses Includes SyncFET Schottky body diode.2a, 3V R DS(on) = 22mΩ @ V GS = V R DS(on) = 2mΩ @ V GS =.5V : Optimized for low switching losses Low Gate Charge (nc typical).9a, 3V R DS(on) = 27mΩ @ V GS = V R DS(on) = 3mΩ @ V GS =.5V % R G (Gate Resistance) Tested FDS9AS SD2 SD2 SD2 D G D D D 2 3 7 SO- Pin SO- G S S S D DG2 S2 Dual N-Channel SyncFet 5 Absolute Maximum Ratings T A = 25 C unless otherwise noted Symbol Parameter Units V DSS Drain-Source Voltage 3 3 V V GSS Gate-Source Voltage ±2 ±2 V I D Drain Current - Continuous (Note a).2.9 A - Pulsed 3 2 P D Power Dissipation for Dual Operation 2 W Power Dissipation for Single Operation (Note a). (Note b) (Note c).9 T J, T STG Operating and Storage Junction Temperature Range 55 to +5 C Thermal Characteristics R θja Thermal Resistance, Junction-to-Ambient (Note a) 7 C/W R θjc Thermal Resistance, Junction-to-Case (Note ) C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS9AS FDS9AS 3 2mm 25 units FDS9AS FDS9AS_NL (Note ) 3 2mm 25 units 25 Fairchild Semiconductor Corporation FDS9AS Rev B(X)
Electrical Characteristics T A = 25 C unless otherwise noted Symbol Parameter Test Conditio Type Min Typ Max Units Off Characteristics BV DSS Drain-Source Breakdown V GS = V, I D = ma Voltage V GS = V, I D = 25 ua BVDSS Breakdown Voltage I D = ma, Referenced to 25 C T J Temperature Coefficient I D = 25 µa, Referenced to 25 C I DSS Zero Gate Voltage Drain V DS = 2 V, V GS = V Current I GSS Gate-Body Leakage V GS = ±2 V, V DS = V 3 3 27 22 V mv/ C 5 µa ± na FDS9AS On Characteristics (Note 2) V GS(th) Gate Threshold Voltage V DS = V GS, I D = ma VGS(th) T J R DS(on) Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance V DS = V GS, I D = 25 µa I D = ma, Referenced to 25 C I D = 25 ua, Referenced to 25 C V GS = V, I D =.2 A V GS = V, I D =.2 A, T J = 25 C V GS =.5 V, I D = 7. A V GS = V, I D =.9 A V GS = V, I D =.9 A, T J = 25 C V GS =.5 V, I D =.2 A I D(on) On-State Drain Current V GS = V, V DS = 5 V g FS Forward Traconductance V DS = 5 V, I D =.2 A V DS = 5 V, I D =.9 A Dynamic Characteristics C iss Input Capacitance V DS = 5 V, f =. MHz V GS = V, C oss Output Capacitance C rss Reverse Trafer Capacitance R G Gate Resistance.9.9 3.2.2 7 23 2 22 3 27 3 2 25 2 57 5 7 7 2. 2.2 3 3 22 3 2 27 3 3.9 3. V mv/ C mω A S pf pf pf Ω Switching Characteristics (Note 2) t d(on) Turn-On Delay Time t r Turn-On Rise Time V DD = 5 V, I D = A, t d(off) Turn-Off Delay Time V GS = V, R GEN = Ω t f Turn-Off Fall Time t d(on) Turn-On Delay Time t r Turn-On Rise Time V DD = 5 V, I D = A, t d(off) Turn-Off Delay Time V GS =.5 V, R GEN = Ω t f Turn-Off Fall Time 9 5 2 23 3 3 5 9 9 2 32 2 9 27 29 25 2 FDS9AS Rev B (X)
Electrical Characteristics (continued) T A = 25 C unless otherwise noted Symbol Parameter Test Conditio Type Min Typ Max Units Switching Characteristics (Note 2) Q g(tot) Q g Q gs Q gd Total Gate Charge at Vgs=V Total Gate Charge at Vgs=5V Gate Source Charge Gate Drain Charge : V DS = 5 V, I D =.2A : V DS = 5 V, I D =.9A Drain Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current 2.3 A.3 T rr Reverse Recovery Time I F =.2 A, 5 Q rr Reverse Recovery Charge d if /d t = 3 A/µs (Note 3) nc T rr Reverse Recovery Time I F =.9 A, 9 Q rr Reverse Recovery Charge d if /d t = A/µs (Note 3) nc V SD Drain-Source Diode Forward Voltage V V GS = V, I S = 2.3 A (Note 2) V GS = V, I S = 5 A (Note 2) V GS = V, I S =.3 A (Note 2) 5....7 2. 2.2..7.7 5 5.2.5.7..2 nc nc nc nc FDS9AS Notes:. R θja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pi. R θjc is guaranteed by design while R θca is determined by the user's board design. a) 7 C/W when mounted on a.5in 2 pad of 2 oz copper b) 25 C/W when mounted on a.2 in 2 pad of 2 oz copper c) 35 C/W when mounted on a minimum pad. Scale : on letter size paper 2. Pulse Test: Pulse Width < 3µs, Duty Cycle < 2.% 3. See SyncFET Schottky body diode characteristics below.. FDS9AS_NL is a lead free product. The FDS9AS_NL marking will appear on the reel label. FDS9AS Rev B (X)
Typical Characteristics: 3 2 V GS = V.V.V.5V 3.5V 3.V 2.5V.5.5 2 2.5 3 V DS, DRAIN-SOURCE VOLTAGE (V) Figure. On-Region Characteristics. R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 2. 2.2 2....2. V GS = 3.V 3.5V.V.5V 5.V.V V 5 5 2 25 3 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. FDS9AS R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE...2. I D =.2A V GS = V R DS(ON), ON-RESISTANCE (OHM)..5..3.2 T A = 25 o C T A = 25 o C I D = A. -5-25 25 5 75 25 5 T J, JUNCTION TEMPERATURE ( o C) Figure 3. On-Resistance Variation with Temperature.. 2 V GS, GATE TO SOURCE VOLTAGE (V) Figure. On-Resistance Variation with Gate-to-Source Voltage. 3 25 2 5 5 V DS = 5V T A = 25 o C 25 o C -55 o C.5 2 2.5 3 3.5 V GS, GATE TO SOURCE VOLTAGE (V) Figure 5. Trafer Characteristics. I S, REVERSE DRAIN CURRENT (A)... V GS = V T A = 25 o C 25 o C -55 o C.2... V SD, BODY DIODE FORWARD VOLTAGE (V) Figure. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS9AS Rev B (X)
Typical Characteristics: V GS, GATE-SOURCE VOLTAGE (V) I D =.2A V DS = V 2V 5V 2 CAPACITANCE (pf) 2 C oss C iss f = MHz V GS = V FDS9AS C rss 3 9 2 Q g, GATE CHARGE (nc) 5 5 2 25 3 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. Figure. Capacitance Characteristics. 5. R DS(ON) LIMIT V GS = V R θja = 35 o C/W T A = 25 o C DC s s ms ms ms µs P(pk), PEAK TRANSIENT POWER (W) 3 2 R θja = 35 C/W T A = 25 C.. V DS, DRAIN-SOURCE VOLTAGE (V)... t, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. D =.5.2..5.2...... t, TIME (sec) R θja (t) = r(t) * R θja R θja = 35 C/W P(pk) t t 2 T J - T A = P * R θja (t) Duty Cycle, D = t / t 2 Figure. Traient Thermal Respoe Curve. Thermal characterization performed using the conditio described in Note c. Traient thermal respoe will change depending on the circuit board design. FDS9AS Rev B (X)
Typical Characteristics 2 2 V GS = V.V.5V.V 3.5V 3.V 2.5V...2. 2 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 2. On-Region Characteristics. R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 2.2 2....2. V GS = 3.V 3.5V.V.5V 5.V.V V 2 2 Figure 3. On-Resistance Variation with Drain Current and Gate Voltage. FDS9AS R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE...2. I D =.9A V GS = V R DS(ON), ON-RESISTANCE (OHM).7..5..3 T A = 25 o C T A = 25 o C I D = 3.5A. -5-25 25 5 75 25 5 T J, JUNCTION TEMPERATURE ( o C) Figure. On-Resistance Variation with Temperature..2 2 V GS, GATE TO SOURCE VOLTAGE (V) Figure 5. On-Resistance Variation with Gate-to-Source Voltage. 2 2 V DS = 5V T A = 25 o C -55 o C 25 o C I S, REVERSE DRAIN CURRENT (A)... V GS = V T A = 25 o C 25 o C -55 o C.5 2 2.5 3 3.5 V GS, GATE TO SOURCE VOLTAGE (V) Figure. Trafer Characteristics...2....2 V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 7. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS9AS Rev B (X)
Typical Characteristics V GS, GATE-SOURCE VOLTAGE (V) I D =.9A V DS = V 2V 5V 2 CAPACITANCE (pf) 2 C oss C iss f = MHz V GS = V FDS9AS C rss 2 2 Q g, GATE CHARGE (nc) 5 5 2 25 3 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. 5. R DS(ON) LIMIT V GS = V R θja = 35 o C/W T A = 25 o C ms ms ms s s DC µs P(pk), PEAK TRANSIENT POWER (W) 3 2 R θja = 35 C/W T A = 25 C.. V DS, DRAIN-SOURCE VOLTAGE (V)... t, TIME (sec) Figure 2. Maximum Safe Operating Area. Figure 2. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. D =.5.2..5.2...... t, TIME (sec) P(pk) R θja (t) = r(t) * R θja R θja = 35 o C/W t t 2 T J - T A = P * R θja (t) Duty Cycle, D = t / t 2 Figure 22. Traient Thermal Respoe Curve. Thermal characterization performed using the conditio described in Note c. Traient thermal respoe will change depending on the circuit board design. FDS9AS Rev B (X)
Typical Characteristics (continued) SyncFET Schottky Body Diode Characteristics FDS9AS Fairchild s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 23 shows the reverse recovery characteristic of the FDS9AS. Current:.A/DIV Time: ns/div Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. I DSS, REVERSE LEAKAGE CURRENT (A)..... 25 o C o C 25 o C 5 5 2 25 3 V DS, REVERSE VOLTAGE (V) Figure 25. SyncFET body diode reverse leakage versus drain-source voltage and temperature Figure 23. FDS9AS SyncFET body diode reverse recovery characteristic. For comparison purposes, Figure 2 shows the reverse recovery characteristics of the body diode of an equivalent size MOSFET produced without SyncFET (FDS9). Current:.A/DIV Time: ns/div Figure 2. Non-SyncFET (FDS9) body diode reverse recovery characteristic. FDS9AS Rev B (X)
Typical Characteristics FDS9AS V DS L BV DSS V GS R GE V V GS tp vary t P to obtain required peak I AS DUT I AS.Ω + V DD - I AS t P V DS V DD Figure 2. Unclamped Inductive Load Test Circuit Drain Current Same type as t AV Figure 27. Unclamped Inductive Waveforms + - V µf 5kΩ µf + V GS DUT - V DD V Q G(TOT) V GS Q GS Q GD I g(ref Charge, (nc) Figure 2. Gate Charge Test Circuit Figure 29. Gate Charge Waveform V DS R L V DS t ON t d(on) t r 9% toff t d(off ) t f 9% V GS R GEN DUT V DD - V GS Pulse Width µs Duty Cycle.% + V V GS V % 5% % Pulse Width 9% 5% % Figure 3. Switching Time Test Circuit Figure 3. Switching Time Waveforms FDS9AS Rev B (X)
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