Improving Design Reliability By Avoiding EOS. Matthew Hogan, Mentor Graphics

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Improving Design Reliability By Avoiding EOS. Matthew Hogan, Mentor Graphics

BACKGROUND With the advent of more complex design requirements and greater variability in operating environments, electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage portions of the design. The techniques for ensuring circuit reliability must evolve, even for established technologies. Many power-efficient designs today have multiple voltage domains. Device EOS occurs when a low-voltage device is driven by a high-voltage power rail, signal, or bulk connection with the potential to cause long-term damage (usually in the form of oxide breakdown). This damage results in circuit degradation over time. Conversely, when insufficient voltage is applied to a high-voltage device and the device is driven by a low-voltage net, the device may not switch, or may switch slowly, again degrading circuit performance. [1] EOS events can result in a wide spectrum of outcomes, ranging from catastrophic damage, where the IC is permanently non-functional (Figure 1) to electrical floating nodes/gates detection (which can create logic errors and/or gradual degradation in performance), to no short-term perceptible damage or performance degradation. EOS is an important concern for both analog and digital designers, due to the variety of power conditions commonly used in all designs, such as multiple power domains, standby/ wake-up/low power/power-down conditions (in which there is no bias current, but the battery is present), and the presence of high-voltage signals. Figure 1: Damage to input pin due to EOS (source: http:/klabs.org/richcontent/old_ news/old_news/14/eos_example.jpg) Thin-oxide transistors, which are less robust against electrical failure, are being used extensively at advanced nodes, and impose new EOS verification challenges. Thinner oxide generally allows for the use of lower voltage and provides less power. When power domain design errors occur, effects such as negative bias temperature instability (NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting in reduced switching speeds for logic gates, and hot carrier injection (HCI) issues, which alters the threshold voltage of NMOS devices over time. Soft breakdown (SBD) also contributes as a time-dependent failure mechanism, contributing to the degradation effects of gate oxide breakdown. Correct connection of these devices to the appropriate voltage domains is a critical factor when long-term circuit reliability is required. [2] [3] [4] [5] Understanding device pin voltages in all modes of operation is critical for detecting potential EOS issues. The ability to identify device breakdown, recognize reverse breakdown issues in high-voltage areas, and detect maximum voltage across gate oxides are all part of a robust EOS detection strategy. However, verifying device operating voltage conditions in voltage-controlled designs is very complicated. Many design teams employ SPICE simulations and user-generated marker layers or text points to check for EOS, but this is an error-prone method because it requires the designer to manually determine how voltages propagate throughout the design, and manually mark the correct regions for high-voltage design rules. Markers are also extremely difficult to maintain as the design is changed. With consumer expectations for longer device operations at sustained performance levels, designing for reliability is no longer an optional product feature, but a necessary and integral part of a product s specifications. Designers need verification tools and techniques that go beyond the traditional triumvirate of design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) to provide thorough detection of and protection against EOS conditions. 2 [5]

LEVERAGING CALIBRE PERC FOR SUCCESSFUL EOS PREVENTION Preventing EOS events means IC designers must use new techniques to validate circuits that cross multiple power domains, and ensure that the voltages on pins are within the specified range that the device can tolerate. Calibre PERC is not just another point tool, but a full-featured reliability verification solution that supports designers throughout the design and sign-off process with a diverse range of capabilities and techniques that enable effective and efficient detection of EOS susceptibilities. Typically, EOS failures occur over time, making them difficult to find, since the time that elapses between the manufacture of the product and the actual failure can be significant. In place of time-consuming SPICE simulations to identify such errors, Calibre PERC uses static voltage propagation to assign the correct voltages to all of the design s internal nodes. The design team defines some or all of the input voltages, as well as the rules for propagating these voltages across different device types. Specific voltage potentials are identified within the design (typically at power nets and charge pumps), which are then automatically propagated throughout the whole design. Calibre PERC then determines if the voltage at each pin falls within the allowable range. Figure 2: Voltage-Misconnected Gates and Power Domains [1] Calibre PERC s ability to perform circuit topology-aware voltage propagation means designers can model voltage transition across spatial crossings (signal transition from one voltage island to another) to identify real EOS violations. The propagation algorithm runs in both vectored (circuit input states provided) and vectorless (only power/ground rails provided) modes. A quick, convenient way to conservatively search for EOS conditions is to employ a vectorless circuit evaluation, as shown in Figure 2. [1] The four first-stage conventional inverters are all high-voltage devices (e.g., 3.3v, designated by H), while the second-stage 2-input conventional NAND gates are low-voltage devices (e.g., 1.8v, designated by L). By querying each device, the user can attach a conditional filter and return a list of only those devices that have a gate node driven beyond 1.8v. Calibre PERC accomplishes this task in an efficient hierarchical manner by propagating the rail voltages across all devices (assuming that all devices are in the on state in vectorless mode). This results in the V+ and V- rail voltages being propagated throughout the network. Since exact voltages are not required for this investigation, the tool can find such over-voltage conditions much more quickly than a full circuit simulator. [1] In addition to checking for absolute value over-voltage conditions on gate and source pins, Calibre PERC can also check for misconnected bulk pins, and relative pin-to-pin EOS conditions such as damaging drain-to-source voltages. This capability is particularly useful for floating devices where any one pin can tolerate a given maximum voltage, but each pin on the device can only vary from that voltage by a given amount or percentage. With Calibre PERC, designers can easily establish a generic rule to identify the maximum voltage permitted, and then validate that each pin is within the tolerated range below the maximum for the device. Of course, debugging is a key component of any verification flow. Calibre PERC provides an integrated debugging solution that provides extensive coverage and is easy to use. Calibre PERC output can be customized for any design flow, while Calibre RVE provides a results viewing and debugging environment that can highlight results and geometries, and access connectivity information, to make debugging EOS errors easy, quick, and thorough (Figure 3). 3 [5]

Figure 3: Calibre PERC results can be easily and efficiently reviewed and debugged in Calibre RVE. With sophisticated reliability checking techniques, a unified rule deck, and integrated debugging environment, Calibre PERC helps designers eliminate the source of EOS failures without the use of manual markers or SPICE circuit simulation, while also enabling them to achieve the accurate and comprehensive verification necessary to ensure a repeatable and reliable design. To learn more about Calibre PERC s full range of capabilities, visit our website at: http://mentor.com/perc 4 [5]

REFERENCES [1] Hogan, M., Srinivasan, S., Medhat, D., Lu, Z., Hofmann, M., Using Static Voltage Analysis and Voltage-Aware DRC to Identify EOS and Oxide Breakdown Reliability Issues, Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013. [2] Abrishami, H., et al., NBTI-Aware Flip-Flop Characterization and Design, Great Lakes Symposium on VLSI (GLSVLSI), May 4 6, 2008. doi: 10.1145/1366110.1366121 [3] Paul, B.C.; Kunhyuk Kang; Kufluoglu, H.; Alam, M.A.; Roy, K., Impact of NBTI on the temporal performance degradation of digital circuits, Electron Device Letters, IEEE, vol.26, no.8, pp.560,562, Aug. 2005 doi: 10.1109/LED.2005.852523 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1468222&isnumber=31488 [4] Hong Luo; Yu Wang; Ku He; Rong Luo; Huazhong Yang; Yuan Xie, Modeling of PMOS NBTI Effect Considering Temperature Variation, Quality Electronic Design, 2007. ISQED 07. 8th International Symposium on, pp.139,144, 26-28 March 2007 doi: 10.1109/ISQED.2007.104 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4149025&isnumber=4148983 [5] Jin Qin; Xiaojun Li; Bernstein, J.B., SRAM stability analysis considering gate oxide SBD, NBTI and HCI, Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International, vol., no., pp.33,37, 15-18 Oct. 2007 doi: 10.1109/IRWS.2007.4469217 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4469217&isnumber=4469203 For the latest product information, call us or visit: w w w. m e n t o r. c o m 2013 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners. MGC 09-13 TECH11380

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