This document was created with FrameMaker 0 Using External RAM with PICCXX Devices TB00 Author: Introduction Rodger Richey Advanced Microcontroller and Technology Division This Technical Brief shows how to connect a PICCXX device to external memory. It also provides instructions and calculations to help determine which speeds of SRAM work with which frequency crystal. System Configuration Are you doing FFT s? Storing arrays of data? Typically, low speed designs would use EEPROM to hold the data that is being generated. On the other hand, high speed designs need to use static RAM because of the faster access times. External SRAM can easily be integrated with a PICCXX device to create the SRAM bank your design requires. Data storage and retrieval is accomplished through table read and table write instructions. All the equations for lead timing can also be applied to EPROMs. The first thing you need to know is how much RAM the system requires. Table shows how much external memory can be used with the PICCXX family members. The microcontroller is put into extended microcontroller mode which can access both the internal and external memory. Both the internal and external memory is -bits wide. TABLE : Device PICC PICC PICC INTERNAL/EXTERNAL MEMORY Internal External Internal External Internal External Size (Words) Address Range 0 0x0000-0x0FF 0x000-0xFFFF 0 0x0000-0x0FFF 0 0x000-0xFFFF 0x0000-0xFFF 0x000-0xFFFF The next step is to connect the external SRAM to the PICCXX. Appendix A shows the schematic for connecting two MTC (Kx) SRAM devices to a PICC. The MTC can be obtained from Micron Semiconductor. The only additional hardware required is two latches (ACTs or ACTs). Both chips are octal latches but the ACT has the inputs and the outputs on opposite sides of the chip which makes interfacing to the microcontroller easier. DS00A-page
READ TIMINGS Now that we know how to connect the hardware, the next step is to determine the speed grade of the SRAM. Let s first take a look at the read timings. Figure shows a combined timing diagram for the read cycle of a PICCX device and the MTC SRAM. FIGURE : PICCX/MTC READ CYCLE TIMING DIAGRAM Q Q Q Q Q Q OSC ALE OE TADZOEL TOE TOEL AD<:0> Addr out Data in Addr out WR '' TPD TADVALL TALLADI TACC TADVOEH TOEHADI '' A<:0> Addr Valid CE TPDGAL DQ Data Valid TLZOE TLZCE TAOE THZOE TACE The value of TACE shows which speed grade of SRAM is required for the read cycle. Figure has three key locations marked that help define TACE. Table summarizes these locations. TABLE : LOCATION MARKER DESCRIPTIONS FOR FIGURE Location Description Value Address Setup Time. This location marks the spot where the address becomes valid out of the PICCXX before ALE goes LOW. (Q cycle) 0. * TCY - 0 time in nanoseconds before the Q cycle (TADVALL) Propagation delay of the ACT. This is the spot where the address to the SRAM becomes valid. (Q cycle) time in nanoseconds before the Q cycle (TPD) Propagation delay of the address decoder. This spot is where the CE signal from the address decoder to the SRAM goes LOW. (Q cycle) TPDGAL time in nanoseconds before the Q cycle DS00A-page
TABLE : MEMORY INTERFACE READ REQUIREMENTS Sym Characteristic Min Typ Max Units TADVALL AD:AD0 (address) valid to ALE (address setup time) 0.Tcy - 0 ns TALLADI ALE to address out invalid (address hold time) * ns TADZOEL AD:AD0 hi-impedance to OE 0 ns TADVOEH Data in valid before OE (data setup time) ns TOEHADI OE to data in invalid (data hold time) 0 ns TOEL OE pulse width 0.Tcy - ns TOE Output enable access time (OE low to Data Valid) 0.TCY - ns TPD Propagation delay input to output ns TACC Address access time 0.Tcy - 0 ns TPDGAL Propagation delay input to combinatorial output. - ns TLZOE OE to output in Low - Z 0 ns TAOE OE access time - ns TLZCE CE to output in Low - Z ns TACE CE access time 0 - ns THZOE Output disable to output in High - Z - ns To determine TACE from Figure, the following equation can be used. Each part of the equation is related to a timing parameter or one of the marked locations in Figure. TACE = 0. * TCY - 0 - Address access time - TACC - Propagation delay of the ACT - TPD - Propagation delay of the address decoder Finally, lets find some example speed grades for various crystal frequencies. One thing to remember is that this is only the read timing speed grade. You must also calculate the write timing speed grade. As you can see the speed grade for the SRAM is dependent on the address decoder. Typically, programmable array logic devices such as a V or a V0 are used. The propagation delays of these devices can be anywhere from ns up to 0 ns. MHz (TCY = 00 ns) MHz (TCY = 0 ns) 0 MHz (TCY = 00 ns) MHz (TCY = 0 ns) TACE = 0. * 00-0 TACE = 0. * 0-0 TACE = 0. * 00-0 TACE = 0. * 0-0 TACE = TACE =. TACE = TACE = 0 TACE = TACE =. TACE = TACE = To reduce the total propagation delay of the ACT and the address decoder, the address/data lines and ALE from the PICCX can be routed to the address decoder. Now the address latches and the address decoding can be performed in parallel. DS00A-page
WRITE TIMINGS Now that you have determined the read timing speed grade, it is time to calculate the write timing speed grade of the SRAM for your design. Figure shows the combined timings for a write cycle of the PICCX devices and the MTC. Again, there are markings for some key locations which are described in Table. FIGURE : PICCX/MTC WRITE CYCLE TIMING DIAGRAM OSC Q Q Q Q Q Q ALE OE WR AD<:0> TALLADI TADVALL TWRL addr out data out addr out TPD TADVWRL TWRHADI A<:0> addr valid CE TPDGAL D<:0> data valid TDS TWP = TWRL TCW TAW TDH TABLE : LOCATION MARKER DESCRIPTIONS FOR FIGURE Location Description Value Address Setup Time. This location marks the spot where the address becomes valid out of the PICCXX before ALE goes LOW. (Q cycle) Propagation delay of the ACT. This is the spot where the address to the SRAM becomes valid. (Q cycle) Propagation delay of the address decoder. This spot is where the CE signal from the address decoder to the SRAM goes LOW. (Q cycle) Write pulse goes LOW. The SRAM specifies that the address at it s inputs must be valid at or before this point. (Q cycle) 0. * TCY - 0 time in nanoseconds before the Q cycle (TADVALL) time in nanoseconds before the Q cycle TPDGAL time in nanoseconds before the Q cycle DS00A-page
TABLE : MEMORY INTERFACE WRITE REQUIREMENTS Sym Characteristic Min Typ Max Units TADVALL AD<:0> (address) valid to ALE (address setup time) 0.Tcy - 0 ns TALLADI ALE to address out invalid (address hold time) 0 ns TADVWRL Data out valid to WR (data setup time) 0.Tcy - 0 ns TWRHADI WR to data out invalid (data hold time) 0.TCY ns TWRL WR pulse width 0.TCY ns TPD Propagation delay input to output ns TPDGAL Propagation delay input to combinatorial output. - ns TDS Data setup time - 0 ns TCW CE to end of write - ns TAW Address valid to end of write - ns TDH Data hold time 0 ns TWP WE pulse width Low - ns The critical timing specification for the write cycle is when the CE signal from the address decoder to the SRAM goes LOW. Typically the SRAM specifies this parameter (TAS for the MTC). The other important SRAM specifications to check against the PICCX are: TWP - Write enable LOW pulse width TDS - Data setup time, data valid before WE goes HIGH TDH - Data hold time, data valid after WE goes HIGH The following are some calculations for the write cycle of various speed grades. These calculations are used to determine if any of the above specifications are invalid. The Micron MTC specifies the following values for the above parameters: TAS - 0 ns min. for all speed grades TWP - ns min. for the ns speed grade TDS - 0 ns min. for the ns speed grade TDH - 0 ns min. for all speed grades The PICCX specifies the following values: TWP - 0. * TCY TWRL TDS - 0. * TCY - 0 + TWP min. TADVWRL TDH - 0. * TCY TWRHADI DS00A-page
MHz (TCY = 00 ns) MHz (TCY = 0 ns) 0 MHz (TCY = 00 ns) MHz (TCY = 0 ns) TADVALL = 0. * 00-0 TADVALL = 0. * 0-0 TADVALL = 0. * 0-0 TADVALL = 0. * 0-0 TAS = TADVALL TAS = TADVALL TAS = TADVALL TAS = TADVALL + TCY + TCY + TCY + Tcy TWRL = 0. * 00 TWRL = 0. * 0 TWRL = 0. * 0 TWRL = 0. * 0 TADVWRL = 0. * 00-0 + 0. * 00 TADVWRL = 0. * 0-0 + 0. * 0 TADVWRL = 0. * 0-0 + 0. * 0 TADVWRL = 0. * 0-0 + 0. * 0 TWRHADI = 0. * 00 TWRHADI = 0. * 0 TWRHADI = 0. * 0 TWRHADI = 0. * 0 TADVALL = TADVALL =. TADVALL = 0 TADVALL = 0 TAS = TAS =. TAS = 0 TAS = 0 + +. + 0 + 0 TWRL = TWRL =. TWRL = 0 TWRL = 0 TADVWRL = 0 TADVWRL =. TADVWRL = 0 TADVWRL = 0 TWRHADI = TWRHADI =. TWRHADI = 0 TWRHADI = 0 TADVALL = TADVALL =. TADVALL = 0 TADVALL = 0 TAS = TWRL > ns TADVWRL > ns TWRHADI > 0 ns Assuming that a V with propagation delay of ns is used for the address decoder, you can see that all crystal frequencies have a TAS greater than 0. The other parameters TADVWRL, TWRHADI, and TWRL all have at least ns of spare room. The parameters TADVWRL, TWRHADI, and TWRL were taken from a ns speed grade SRAM. Therefore, all the speed grades of the MTC can be used for the write cycle of a PICCX with an external oscillator frequency up to MHz. CONCLUSION TAS = TWRL > ns TADVWRL > ns TWRHADI > 0 ns TAS = TWRL > ns TADVWRL > ns TWRHADI > 0 ns TAS = TWRL > ns TADVWRL > ns TWRHADI > 0 ns So now that we have done the calculations, let s determine the proper SRAM speed grade for the various frequencies. The only assumption is that a ns V is used for address decoding. MHz can use up to a 00 ns SRAM MHz can use up to a ns SRAM 0 MHz can use up to a 0 ns SRAM MHz can use up to a 0 ns SRAM DS00A-page
APPENDIX A: PICCX EXTERNAL RAM SCHEMATIC C R 0. µf.k AD0 AD AD AD AD AD AD AD 0 0 U RC0/AD0 RC/AD RC/AD RC/AD RC/AD RC/AD RC/AD RC/AD Vss RB0/CAP RB/CAP RB/PWM RB/PWM RB/TCLK RB/TCLK RB RB OSC/CLKIN OSC/CLKOUT RD0/AD RD/AD RD/AD0 RD/AD RD/AD RD/AD RD/AD RD/AD MCLR/VPP VSS RE0/ALE RE/OE RE/WR TEST R/INT RA/T0CKI RA RA RA/RX/DT R/TX/CK 0 0 C Note Y C Note Note Note : The value of the crystal is dependent on your system requirements. : The value of capacitors C and C is dependent on the crystal. Address Decoder AD AD AD0 AD AD AD AD AD AD0 AD AD AD AD AD AD AD AD AD AD0 AD AD AD AD AD U D D D D D D D D Q Q Q Q Q Q Q Q C OC Vcc GND ACT 0 0 0. µf C U D D D D D D D D Q Q Q Q Q Q Q Q C OC Vcc GND ACT 0 0 C 0. µf A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 U A A A A A A A A A D D D D D D D D CE OE WE Vss Vcc MTC U A A A A A A A A A D D D D D D D D CE OE WE Vss Vcc MTC AD0 AD AD AD AD AD AD AD C 0. µf AD0 AD AD AD AD AD AD AD C 0. µf DS00A-page
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