19-1317; Rev 1; 12/97 Low-Power, Dual, 12-Bit oltage-output DACs General Description The / low-power, serial, voltage-output, dual 12-bit digital-to-analog converters (DACs) coume only 5µA from a single +5 () or +3 () supply. These devices feature Rail-to- Rail output swing and are available in space-saving 16-pin QSOP and DIP packages. Access to the inverting input allows for specific gain configuratio, remote seing, and high output current capability, making these devices ideally suited for industrial process controls. These devices are also well suited for digitally programmable (4 2mA) current loops. The 3-wire serial interface is SPI /QSPI and Microwire compatible. Each DAC has a doublebuffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously. Additional features include a programmable shutdown (2µA), hardware-shutdown lockout, a separate voltage reference for each DAC, power-on reset, and an activelow clear input (CL) that resets all registers and DACs to zero. The / provide a programmable logic output pin for added functionality, and a serialdata output pin for daisy chaining. Applicatio Industrial Process Control Digital Offset and Gain Adjustment Remote Industrial Controls Motion Control Digitally Programmable 4 2mA Current Loops Automatic Test Equipment Features 12-Bit Dual DAC with Configurable Output Amplifier Single-Supply Operation: +5 () +3 () Rail-to-Rail Output Swing Low Quiescent Current: 5µA (normal operation) 2µA (shutdown mode) Power-On Reset Clears DAC Outputs to Zero SPI/QSPI and Microwire Compatible Space-Saving 16-Pin QSOP Package Ordering Information PART ACPE BCPE ACEE BCEE TEMP. RANGE C to +7 C C to +7 C C to +7 C C to +7 C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP Ordering Information continued at end of data sheet. Pin Configuration appears at end of data sheet. INL () /2 /2 / Functional Diagram DOUT CL PDL DGND DD A 16-BIT SHIFT REGISTER SR CONTROL DECODE CONTROL LOGIC OUTPUT INPUT REG A INPUT REG B DAC REG A DAC REG B DAC A DAC B OUTA FBA OUTB FBB UPO B Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-8-998-88. For small orders, phone 48-737-76 ext. 3468.
/ ABSOLUTE MAXIMUM RATINGS DD to...-.3 to +6 DD to DGND...-.3 to +6 to DGND...±.3 FBA, FBB to...-.3 to ( DD +.3) _, to...-.3 to ( DD +.3) Digital Inputs (,,, CL, PDL) to DGND...-.3 to +6 Digital Outputs (DOUT, UPO) to DGND...-.3 to ( DD +.3) Maximum Current into Any Pin...±2mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate 1.5mW/ C above +7 C)...593mW QSOP (derate 8.3mW/ C above +7 C)...667mW CERDIP (derate 1.mW/ C above +7 C)...8mW Operating Temperature Ranges MAX5152_C_E/MAX5153_C_E... C to +7 C MAX5152_E_E/MAX5153_E_E...-4 C to +85 C MAX5152_MJE/MAX5153_MJE...-55 C to +125 C Storage Temperature Range...-65 C to +16 C Lead Temperature (soldering, 1sec)...+3 C ( DD = +5 %, A = B = 2.5, R L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C, output buffer connected in unity-gain configuration (Figure 9).) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error PARAMETER STATIC PERFORMANCE Gain-Error Tempco DD Power-Supply Rejection Ratio ERENCE INPUT SYMBOL N INL DNL OS TC OS PSRR A (Note 1) B Guaranteed monotonic Code = 1 Normalized to 2.5 Normalized to 2.5 4.5 DD 5.5 CONDITIONS MIN TYP MAX 12 3 3 /2 ±6 -.5 ±3 2 2 UNITS Bits m ppm/ C ppm/ C µ/ Reference Input Range DD - 1.4 Reference Input Resistance R Minimum with code 1554 hex 14 2 kω MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Input code = 1FFE hex, =.67p-p at 2.5 DC 6 khz Reference Feedthrough Input code = hex, = ( DD - 1.4p-p) at 1kHz -85 db Signal-to-Noise plus Distortion Ratio SINAD Input code = 1FFE hex, = 1p-p at 2.5 DC, f = 25kHz 82 db DIGITAL INPUTS Input High oltage IH CL, PDL,,, 3 Input Low oltage IL CL, PDL,,,.8 Input Hysteresis HYS 2 m Input Leakage Current I IN IN = to DD.1 µa Input Capacitance C IN 8 pf 2
ELECTRICAL CHARACTERISTI (continued) ( DD = +5 %, A = B = 2.5, R L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER DIGITAL OUTPUTS (DOUT, UPO) Output High oltage Output Low oltage DYNAMIC PERFORMANCE oltage Output Slew Rate Output Settling Time Output oltage Swing Current into FBA or FBB Time Required to Exit Shutdown Digital Feedthrough Digital Crosstalk POWER SUPPLIES Positive Supply oltage Power-Supply Current Power-Supply Current in Shutdown SYMBOL OH OL SR I FB DD I DD I DD(SHDN) I SOURCE = 2mA I SINK = 2mA To 1/2 of full-scale, STEP = 2.5 Rail-to-rail (Note 2) CONDITIONS = DD, f = 1kHz, = 5p-p (Note 3) (Note 3) MIN TYP MAX DD -.5.13.4.75 15 to DD ±.1 25 5 5 4.5 5.5.5.65 2 1 UNITS /µs µs µa µs n-s n-s ma µa / Reference Current in Shutdown µa TIMING CHARACTERISTI Clock Period t CP (Note 4) 1 Pulse Width High t CH 4 Pulse Width Low t CL 4 Fall to Rise Setup Time t S 4 Rise to Rise Hold Time t CHS Setup Time t DS 4 Hold Time t DH Rise to DOUT alid Propagation Delay t DO1 C LOAD = 2pF 8 Fall to DOUT alid Propagation Delay t DO2 C LOAD = 2pF 8 Rise to Fall Delay t 1 Rise to Rise Hold t 1 4 Pulse Width High t W 1 Note 1: Accuracy is specified from code 1 to code 495. Note 2: Accuracy is better than 1 for OUT greater than 6m and less than DD - 5m. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either DD or DGND, code = hex, R L =. Note 4: minimum clock period includes rise and fall times. 3
/ ELECTRICAL CHARACTERISTI ( DD = +2.7 to +3.6, A = B = 1.25, R L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C, output buffer connected in unity-gain configuration (Figure 9).) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error PARAMETER STATIC PERFORMANCE Gain-Error Tempco DD Power-Supply Rejection Ratio ERENCE INPUT ( ) Reference Input Range Reference Input Resistance MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth SYMBOL N INL DNL OS TC OS PSRR R A (Note 5) B Guaranteed monotonic Code = 2 Normalized to 1.25 Normalized to 1.25 2.7 DD 3.6 CONDITIONS Minimum with code 1554 hex Input code = 1FFE hex, (AC) =.67p-p at 1.25 DC MIN TYP MAX 12 6 6 14 2 6 ±2 ±6 -.5 ±4 2 32 DD - 1.4 UNITS Bits m ppm/ C ppm/ C µ/ kω khz Reference Feedthrough Input code = hex, = ( DD - 1.4) at 1kHz -92 db Signal-to-Noise plus Distortion Ratio SINAD Input code = 1FFE hex, = 1p-p at 1.25 DC, f = 15kHz 73 db DIGITAL INPUTS Input High oltage IH CL, PDL,,, 2.2 Input Low oltage IL CL, PDL,,,.8 Input Hysteresis HYS 2 m Input Leakage Current I IN IN = to DD ±.1 µa Input Capacitance C IN 8 pf DIGITAL OUTPUTS (DOUT, UPO) Output High oltage OH I SOURCE = 2mA DD -.5 Output Low oltage OL I SINK = 2mA.13.4 DYNAMIC PERFORMANCE oltage Output Slew Rate SR.75 /µs Output Settling Time To 1/2 of full-scale, STEP = 1.25 18 µs Output oltage Swing Rail-to-rail (Note 6) to DD Current into FBA or FBB I FB ±.1 µa Time Required to Exit Shutdown 25 µs Digital Feedthrough = DD, f = 1kHz, = 3p-p 5 n-s Digital Crosstalk 5 n-s 4
ELECTRICAL CHARACTERISTI (continued) ( DD = +2.7 to +3.6, A = B = 1.25, R L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER POWER SUPPLIES Positive Supply oltage Power-Supply Current Power-Supply Current in Shutdown Reference Current in Shutdown TIMING CHARACTERISTI Clock Period Pulse Width High Pulse Width Low Fall to Rise Setup Time Rise to Rise Hold Time Setup Time Hold Time Rise to DOUT alid Propagation Delay Fall to DOUT alid Propagation Delay Rise to Fall Delay Rise to Rise Hold Pulse Width High SYMBOL DD I DD I DD(SHDN) t CP t CH t CL t S t CHS t DS t DH t DO1 t DO2 t t 1 t W (Note 7) (Note 7) (Note 4) C LOAD = 2pF C LOAD = 2pF CONDITIONS MIN TYP MAX 2.7 3.6.5.6 1 4 4 4 5 1 4 1 1 8 12 12 UNITS ma µa µa / Note 5: Accuracy is specified from code 2 to code 495. Note 6: Accuracy is better than 1 for OUT greater than 6m and less than DD - 1m. Guaranteed by PSRR test at the end points. Note 7: Digital inputs are set to either DD or DGND, code = hex, R L =. 5
/ Typical Operating Characteristics ( DD = +5, R L = 1kΩ, C L = 1pF, FB_ connected to, T A = +25 C, unless otherwise noted.) RELATIE OUTPUT (db) -2-4 -6-8 -1-12 -14-16 -18-2 ERENCE OLTAGE INPUT FREQUENCY RESPONSE =.67p-p @ 2.5 DC 6 12 18 24 3 FREQUENCY (khz) TOC1 SUPPLY CURRENT (ma).6.55.5.45.4 R L = SUPPLY CURRENT vs. TEMPERATURE CODE = (HEX) -6-2 2 6 1 14 TEMPERATURE ( C) TOC2 THD + NOISE (db) -3-4 -5-6 -7-8 -9 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY = 1p-p @ 2.5 DC 1 1 FREQUENCY (khz) TOC3 FULL-SCALE ERROR () -.1 -.2 -.3 -.4 FULL-SCALE ERROR vs. RESISTIE LOAD = 2.5 TOC4 RELATIE OUTPUT (db) -5-6 -7-8 -9-1 -11-12 -13-14 ERENCE FEEDTHROUGH AT 1kHz = 3.6p-p @ 1.88 DC CODE = (HEX) -TOC5 POWER-DOWN CURRENT (µa) 3. 2.5 2. 1.5 1..5 POWER-DOWN CURRENT vs. TEMPERATURE TOC6 RELATIE OUTPUT (db) -.5-1 -2-3 -4-5 -6-7.1 1 1 1 1 R L (kω) OUTPUT FFT PLOT = 3.6p-p @ 1.8 DC f = 1kHz NOTE: RELATIE TO FULL SCALE -TOC7-15.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 FREQUENCY (khz) DYNAMIC-RESPONSE RISE TIME TOC8 5/div AC COUPLED 5m/div -55-35 -15 5 25 45 65 85 15 125 TEMPERATURE ( C) DYNAMIC-RESPONSE FALL TIME TOC9 5/div AC COUPLED 5m/div -8-9 -1.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 FREQUENCY (khz) 2µs/div 2µs/div 6
Typical Operating Characteristics (continued) ( DD = +3, R L = 1kΩ, C L = 1pF, FB_ connected to, T A = +25 C, unless otherwise noted.) RELATIE OUTPUT (db) -2-4 -6-8 -1-12 -14-16 -18-2 ERENCE OLTAGE INPUT FREQUENCY RESPONSE =.67p-p @ 1.25 DC 5 1 15 2 25 FREQUENCY (khz) TOC1 SUPPLY CURRENT (ma).6.55.5.45.4 R L = SUPPLY CURRENT vs. TEMPERATURE CODE = (HEX) -6-2 2 6 1 14 TEMPERATURE ( C) TOC11 THD + NOISE (db) -3-4 -5-6 -7-8 -9 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY = 1p-p @ 1 DC 1 1 FREQUENCY (khz) TOC12 / FULL-SCALE ERROR () -.1 -.2 -.3 -.4 -.5 -.6 FULL-SCALE ERROR vs. RESISTIE LOAD = 1.25.1 1 1 1 1 R L (kω) TOC13 RELATIE OUTPUT (db) -5-6 -7-8 -9-1 -11-12 -13-14 -15 ERENCE FEEDTHROUGH AT 1kHz = 1.6p-p @.88 DC CODE = (HEX).5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 FREQUENCY (khz) -TOC14 POWER-DOWN CURRENT (µa) 3. 2.5 2. 1.5 1..5 POWER-DOWN CURRENT vs. TEMPERATURE -55-35 -15 5 25 45 65 85 15 125 TEMPERATURE ( C) TOC15 RELATIE OUTPUT (db) -1-2 -3-4 -5-6 -7-8 OUTPUT FFT PLOT = 1.6p-p @.88 DC f = 1kHz NOTE: RELATIE TO FULL SCALE -TOC16 DYNAMIC-RESPONSE RISE TIME TOC17 2/div 5m/div DYNAMIC-RESPONSE FALL TIME TOC18 2/div 5m/div -9-1.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 FREQUENCY (khz) 2µs/div 2µs/div 7
/ Typical Operating Characteristics (continued) ( DD = +5 (), DD = +3 (), R L = 1kΩ, C L = 1pF, FB_ connected to, T A = T MIN to T MAX, unless otherwise noted.) SUPPLY CURRENT (ma).6.55.5.45.4.35 SUPPLY CURRENT vs. SUPPLY OLTAGE CODE = (HEX) TOC19 / SUPPLY CURRENT (ma).55.5.45.4.35 SUPPLY CURRENT vs. SUPPLY OLTAGE CODE = (HEX) TOC19a.3 4.5 4.75 5. 5.25 5.5 SUPPLY OLTAGE () MAJOR-CARRY TRANSITION.3 TOC2 2.7 3. 3.3 3.6 SUPPLY OLTAGE () 2/div 1m/div AC COUPLED ANALOG CROSSTALK TOC21 2µs/div TRANSITION FROM 1 (HEX) TO FFE (HEX) DIGITAL FEEDTHROUGH TOC22 OUTA 1/div 5/div OUTB 2µ/div AC COUPLED OUTA 5µ/div AC COUPLED 2µs/div 1µs/div 8
Pin Description PIN NAME FUNCTION 1 Analog Ground 2 OUTA DAC A Output oltage 3 FBA DAC A Output Amplifier Feedback Input. Inverting input of the output amplifier. 4 A Reference for DAC A 5 CL Active-Low Clear Input. Resets all registers to zero. DAC outputs go to. 6 Chip-Select Input 7 Serial Data Input 8 Serial Clock Input 9 DGND Digital Ground 1 DOUT Serial Data Output 11 UPO User-Programmable Output 12 PDL Power-Down Lockout. The device cannot be powered down when PDL is low. 13 B Reference Input for DAC B 14 FBB DAC B Output Amplifier Feedback Input. Inverting input of the output amplifier. 15 OUTB DAC B Output oltage 16 DD Positive Power Supply / Detailed Description The / dual, 12-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input comprised of an input register and a DAC register (see Functional Diagram). Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent fullscale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs. Reference Inputs The reference inputs accept both AC and DC values with a voltage range extending from to (DD - 1.4). Determine the output voltage using the following equation: OUT = x NB / 496 where NB is the numeric value of the DAC s binary input code ( to 495) and is the reference voltage. The reference input impedance ranges from 14kΩ (1554 hex) to several giga ohms (with an input code of hex). This reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 5pF with a full-scale input code. _ SHOWN FOR ALL 1s ON DAC R R R 2R 2R 2R 2R 2R D D9 D1 D11 Figure 1. Simplified DAC Circuit Diagram Output Amplifier The output amplifier s inverting input is available to the user, allowing force and see capability for remote seing and specific gain configuratio. The inverting input can be connected to the output to provide a unitygain buffered output. The output amplifiers have a typical slew rate of.75/µs and settle to 1/2 within 15µs, with a load of 1kΩ in parallel to 1pF. Loads less than 2kΩ degrade performance. FB 9
/ Table 1. Serial-Interface Programming Commands A C1 C 16-BIT SERIAL WORD D11...D MSB FUNCTION 1 12 bits of DAC data Load input register A; DAC register is unchanged. 1 1 12 bits of DAC data Load input register B; DAC register is unchanged. 1 12 bits of DAC data Load input register A; all DAC registers are updated. 1 1 12 bits of DAC data Load input register B; all DAC registers are updated. 1 1 12 bits of DAC data 1 xxxxxxxxxxxx 1 x xxxxxxxx 1 1 x xxxxxxxx Load all DAC registers from the shift register (start up both DACs with new data). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). 1 1 1 xxxxxxxxxxxx Shut down both DACs if PDL = 1. Update DAC register A from input register A (start up DAC A with data previously stored in input register A). Update DAC register B from input register B (start up DAC B with data previously stored in input register B). 1 1 x xxxxxxxx Shut down DAC A when PDL = 1. 1 1 1 x xxxxxxxx Shut down DAC B when PDL = 1. 1 x xxxxxxxx UPO goes low (default). 1 1 x xxxxxxxx UPO goes high. 1 1 xxxxxxxx Mode 1, DOUT clocked out on s rising edge. 1 xxxxxxxx Mode, DOUT clocked out on s falling edge (default). x xxxxxxxx No operation (NOP). S x = don t care Note: D11, D1, D9, and D8 become control bits when A, C1, and C =. S is a sub bit, always zero. Power-Down Mode The / feature a software-programmable shutdown mode that reduces the typical supply current to 2µA. The two DACs can be shut down independently or simultaneously by using the appropriate programming word. For itance, enter shutdown mode (for both DACs) by writing an input control word of 111XXXXXXXXXXXX (Table 1). In shutdown mode, the reference inputs and amplifier outputs become high impedance, and the serial interface remai active. Data in the input registers is saved, allowing the / to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting shutdown), wait 2µs for output stabilization. Serial Interface The / 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word coists of an address bit, two control bits, 12 bits of data (MSB to ), and one sub bit as shown in Figure 4. The address and control bits determine the respoe of the /, as outlined in Table 1. 1
Figure 2. Connectio for Microwire SK SO I/O MICROWIRE PORT The / s digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, Microwire), with low during this period. The address and control bits determine which register will be updated, and the state of the registers when exiting shutdown. The 3-bit address/control determines the following: registers to be updated clock edge on which data is clocked out via the serial data output (DOUT) state of the user-programmable logic output configuration of the device after shutdown / Figure 3. Connectio for SPI/QSPI MOSI SCK I/O CC SS SPI/QSPI PORT CPOL =, CPHA = The general timing diagram in Figure 5 illustrates how data is acquired. Driving low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With low, data at is clocked into the register on the rising edge of. As goes high, data is latched into the input and/or DAC registers depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 1MHz. Figure 6 depicts a more detailed timing diagram of the serial interface. Serial Data Output (DOUT) DOUT is the internal shift register s output. It allows for daisy-chaining and data readback. The / can be programmed to shift data out of DOUT on s falling edge (Mode ) or rising edge (Mode 1). Mode provides a lag of 16 clock cycles, which maintai compatibility with SPI/QSPI and Microwire interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode. MSB... Address Bits A 1 Address/2 Control Bits Figure 4. Serial-Data Format 16 Bits of Serial Data Control Bits C1, C MSB...DataBits... D11...D 12 Data Bits Sub Bit S User-Programmable Logic Output (UPO) UPO allows an external device to be controlled through the / serial interface (Table 1), thereby reducing the number of microcontroller I/O pi required. On power-up, UPO is low. Power-Down Lockout Input (PDL) PDL disables software shutdown when low. When in shutdown, traitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to asynchronously wake up the device. 11
/ Figure 5. Serial-Interface Timing Diagram A 1 C1 8 9 16 C D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D t O t S t CL t CH t CP S t H COMMAND EXECUTED t 1 t W t DS tdh Figure 6. Detailed Serial-Interface Timing Diagram DOUT DOUT DOUT TO OTHER SERIAL DEICES Figure 7. Daisy Chaining /s Daisy Chaining Devices Any number of /s can be daisy chained by connecting the DOUT pin of one device to the pin of the following device in the chain (Figure 7). Since the / s DOUT has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the digital output OH and OL specificatio in the Electrical Characteristics. Figure 8 shows an alternative method of connecting several /s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. More I/O lines are required in this configuration because a dedicated chip-select input () is required for each IC. 12
1 2 3 TO OTHER SERIAL DEICES / Figure 8. Multiple /s Sharing a Common Line Table 2. Unipolar Code Table (Gain = +1) _ +5/+3 DAC CONTENTS MSB ANALOG OUTPUT DAC DD FB_ 1111 1111 1111() 1 1() 1 () + 495 + 496 + 249 496 248 = 496 2 DGND 111 1111 1111() + 247 496 Figure 9. Unipolar Output Circuit 1() () + 1 496 Note: ( ) are for the sub bit. Applicatio Information Unipolar Output Figure 9 depicts the / configured for unity-gain, unipolar operation. Table 2 lists the unipolar output codes. To increase dynamic range, specific gain configuratio can be used as shown in Figure 1. Bipolar Output The / can be configured for a bipolar output, as shown in Figure 11. The output voltage is given by the equation: OUT = [((2 x NB) / 496) - 1] where NB represents the numeric value of the DAC s binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11 s circuit. 13
/ _ DAC DGND OUT = (1 + R1 ) ( N )( _) R2 496 +5/+3 DD Figure 1. Configurable Output Gain FB_ R2 R1 OUT _ DAC _ +5/+3 DGND DD Figure 11. Bipolar Output Circuit FB_ 1k 1k + - OUT Table 3. Bipolar Code Table DAC CONTENTS MSB 1111 1111 1111() ANALOG OUTPUT + 247 248 +5/ +3 AC 26k ERENCE INPUT +5/+3 MAX495 1 1() + 1 248 5mp-p 1k _ DD FB_ 1 () 111 1111 1111() - 1 248 DAC_ 1() () - - 247 248 248 = - 298 DGND Note: ( ) are for the sub bit. Figure 12. AC Reference Input Circuit Using an AC Reference In applicatio where the reference has an AC signal component, the / have multiplying capabilities within the reference input voltage range specificatio. Figure 12 shows a technique for applying a sinusoidal input _, where the AC signal is offset before being applied to the reference input. Harmonic Distortion and Noise The total harmonic distortion plus noise (THD+N) is typically less than -8dB at full scale with a 1p-p input swing at 5kHz. The typical -3dB frequency is 6kHz for both devices, as shown in the Typical Operating Characteristics. 14
Digital Calibration and Threshold Selection Figure 13 shows the / in a digital calibration application. With a bright value applied to the photodiode (on), the DAC is digitally ramped up until it trips the comparator. The microprocessor stores this high calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The microprocessor then programs the DAC to set an output voltage that is the midpoint of the two calibration values. Applicatio include tachometers, motion seing, automatic readers, and liquid clarity analysis. Digital Control of Gain and Offset The two DACs can be used to control the offset and gain for curve-fitting nonlinear functio, such as traducer linearization or analog compression/expaion applicatio. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14). µp _ DGND DAC _ +5/+3 DD Figure 13. Digital Calibration + PHOTODIODE FB_ + OUT - R / +5/+3 DD FBA IN CL CONTROL/ SHIFT REGISTER A DACA DACB B A B R1 R3 R2 R4 OUT DGND FBB OUT = [GAIN] - [OFFSET] = NA R2 R4 NB R4 [( IN 496)( R1+R2)( 1+ R3) ] [( 496)( R3) ] NA IS THE NUMERIC ALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC ALUE OF THE INPUT CODE FOR DACB. Figure 14. Digital Control of Gain and Offset 15
/ Digitally Programmable Current Source Figure 15 depicts a digitally programmable, unidirectional current source that can be used in industrial control applicatio. The output current is: IOUT = ( / R) (NB / 496) where NB is the DAC code and R is the see resistor. Power-Supply Coideratio On power-up, the input and DAC registers clear (resets to zero code). For rated performance, _ should be at least 1.4 below DD. Bypass the power supply with a 4.7µF capacitor in parallel with a.1µf capacitor to GND. Minimize lead lengths to reduce lead inductance. Grounding and Layout Coideratio Digital and AC traient signals on can create noise at the output. Connect to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. +5/+3 DD DGND _ DAC_ FB_ Figure 15. Digitally Programmable Current Source L 2N394 R I OUT Pin Configuration _Ordering Information (continued) TOP IEW OUTA FBA A CL 1 2 3 4 5 6 7 8 DIP/QSOP Chip Information 16 DD 15 OUTB 14 FBB 13 B 12 PDL 11 UPO 1 DOUT 9 DGND PART TEMP. RANGE AEPE -4 C to +85 C BEPE -4 C to +85 C AEEE -4 C to +85 C BEEE -4 C to +85 C BMJE -55 C to +125 C ACPE C to +7 C BCPE C to +7 C ACEE C to +7 C BCEE C to +7 C AEPE -4 C to +85 C BEPE -4 C to +85 C AEEE -4 C to +85 C BEEE -4 C to +85 C BMJE -55 C to +125 C *Contact factory for availability. PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP* 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP* INL () /2 /2 ±2 ±2 ±2 ±2 ±2 TRANSISTOR COUNT: 353 SUBSTRATE CONNECTED TO Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 16 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.