Effect of package parasitics and crosstalk on signal delay Francesc Moll and Miquel Roca moll@eel.upc.es miquel.roca@uib.es Electronic Eng. Dpt. Univ. Polit. Catalunya UPC Physics Department Univ. Illes Balears UIB
Outline Introduction Objectives Simulation experiment Results Conclusions
Introduction Device size reduction Switching speed increasing Interconnection length increase Mix devices with different driving capabilities in same IC Increases probability of simultaneous activity Increases number of pins per chip
Technological trends Roadmap from SEMATECH (2000) Year 1999 2001 2002 2005 2008 2011 2014 Technology (nm) 180 130 130 90 60 40 30 Gate oxide (nm) 1.9-2.5 1.5-1.9 2-3 1.0-1.5 < 1.5 < 1.5 < 1.5 Metal levels 6/7 7 7/8 8/9 9 9/10 10 Transistors/cm 2 (SRAM) 35M 70M 95M 234M 577M 1423M 3514M Chip Area (mm 2 ) (DRAM) 400 400 435 454 516 392 448 Memory (Bytes/chip) 1G 2G 4G 8G 20G 45G 104G Supply voltage (V) 1.5-1.8 1.2-1.5 1.2-1.5 0.8-1.1 0.6-0.9 0.5-0.6 0.3-0.6 Power consumption (W) 90 130 140 170 170 175 185 ft/fmax (GHz) 20/25 25/32 30/35 40/50 60/50 120/150 175/140 fclk (MHz) 1250 2100 2490 4150 7115 11050 14920 I/O serial (MHz) 1200 1600 1720 2155 2655 3190 3285 I/O paralel (MHz) 480 800 860 1035 1328 1595 1913 Number of pins ASIC 1400 2200 2600 3800 4600 5400 6000 Number of pins MPU 2304 3042 3042 3042 3840 4224 4410 Cost/pin (10-2 x $) 0.9-1.9 0.86-1.4 0.8-1.33 0.7-1.1 0.6-1.1 0.5-1 0.42-0.9
Introduction Technological trends implications More important parasitic interaction
Noise sources Interconnect noise Introduction Coupling between lines Signal reflections and ringing Power supply distribution Simultaneous switching noise Noise at package level Related to simultaneous switching noise
Objectives Investigate different contributions on delay variation simultaneous transitions on neighboring lines (crosstalk) package parasitics (mainly switching noise)
Advanced vs Retarded Crosstalk delay
Simulation experiment Circuit considered
Package : DIL24 model P1 P2 P3 P4 P12 P24 P23 P22 P21 P13 Resistance 25-95mΩ Capacitance 0.30-0.70pF Inductance 9-19nH Ind. Coupling K 0.015-0.65
Input and Output PADS Schema & Transistors aspect ratio P 25-18.75-18.75 P 22.5 N 8.5 N 15 P 22.5 N 12.5 P 62 N 40 P 192 N 120
Coupling structure I Six coupled chip lines length 1 mm minimum dimension Capacitance matrix from F.E.M. (Raphael (TMA)) SUBSTRATE
Coupling structure II two identical structures of six lines 2 chains of 10 inv (P 37.5, N 12.5) each set 10 Inv Quiet (reference delay) 10 inv P 37.5 N 12.5 10 inv Active (noisy delay) 10 inv
Results Hspice Simulations Technology 0.7 micron ATMEL Rise and Fall times 500ps Delay in reference set vs Delay in noisy set Dependence on Package
Cases Analyzed
Delay due to Package (without crosstalk)
Delay due to crosstalk (without package)
Difference delay due to crosstalk (with and without package)
Conclusions Crosstalk more important than Package in delay terms Package introduces noise in signals Future work Other packages Other circuits (core parts)