Instructor s Resource Manual to accompany DIGITAL FUNDAMENTALS Ninth Edition Thomas L. Floyd Upper Saddle River, New Jersey Columbus, Ohio
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CONTENTS PART : PROBLEM SOLUTIONS... CHAPTER Digital Concepts...2 CHAPTER 2 Number Systems, Operations, and Codes...7 CHAPTER 3 Logic Gates...24 CHAPTER 4 Boolean Algebra and Logic Simplification...35 CHAPTER 5 Combinational Logic Analysis...6 CHAPTER 6 Functions of Combinational Logic...92 CHAPTER 7 Latches, Flip-Flops, and Timers... CHAPTER 8 Counters...24 CHAPTER 9 Shift Registers...52 CHAPTER Memory and Storage...68 CHAPTER Programmable Logic and Software...78 CHAPTER 2 Introduction to Computers...88 CHAPTER 3 Introduction to Digital Signal Processing...94 CHAPTER 4 Integrated Circuit Technologies...22 PART 2: DIGITAL SYSTEM APPLICATION SOLUTIONS...29 CHAPTER 4...2 CHAPTER 5...23 CHAPTER 6...25 CHAPTER 7...27 CHAPTER 8...28 CHAPTER 9...22 CHAPTER...222 CHAPTER...224 PART 3: OVERVIEW OF IEEE STD.9-984...227 PART 4: LABORATORY SOLUTIONS FOR EPERIMENTS IN DIGITAL FUNDAMENTALS by David Buchla...253
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PART Problem Solutions
CHAPTER DIGITAL CONCEPTS Chapter Section - Digital and Analog Quantities. Digital data can be transmitted and stored more efficiently and reliably than analog data. Also, digital circuits are simpler to implement and there is a greater immunity to noisy environments. 2. Pressure is an analog quantity. Section -2 Binary Digits, Logic Levels, and Digital Waveforms 3. HIGH = ; LOW =. See Figure -. 4. A is a HIGH and a is a LOW: (a) HIGH, LOW, HIGH, HIGH, HIGH, LOW, HIGH (b) HIGH, HIGH, HIGH, LOW, HIGH, LOW, LOW, HIGH 2
5. See Figure -2. Chapter 6. T = 4 ms. See Figure -3. 7. f = = T 4 ms =.25 khz = 25 Hz 8. The waveform in Figure -6 is periodic because it repeats at a fixed interval. 9. t W = 2 ms; T = 4 ms tw 2 ms % duty cycle = = = 5% T 4 ms. See Figure -4.. Each bit time = μs Serial transfer time = (8 bits)( μs/bit) = 8 μs Parallel transfer time = bit time = μs Section -3 Basic Logic Operations 3
Chapter 2. An AND gate produces a HIGH output only when all of its inputs are HIGH. 3. AND gate. See Figure -5. 4. An OR gate produces a HIGH output when either or both inputs are HIGH. An exclusive-or gate produces a HIGH if one input is HIGH and the other LOW. Section -4 Overview of Basic Logic Functions 5. See Figure -6. 6. T = khz = μs Pulses counted = ms μs = 7. See Figure -7. 4
Section -5 Fixed-Function Integrated Circuits Chapter 8. Circuits with complexities of from to, equivalent gates are classified as large scale integration (LSI). 9. The pins of an SMT are soldered to the pads on the surface of a pc board, whereas the pins of a DIP feed through and are soldered to the opposite side. Pin spacing on SMTs is less than on DIPs and therefore SMT packages are physically smaller and require less surface area on a pc board. 2. See Figure -8. 5
Section -6 Introduction to Programmable Logic 2. The following do not describe PLDs: ABEL, CUPL Chapter 22. SPLD: Simple Programmable Logic Device CPLD: Complex Programmable Logic Device HDL: Hardware Description Language FPGA: Field-Programmable Gate Array GAL: Generic Array Logic 23. (a) Design entry: The step in a programmable logic design flow where a description of the circuit is entered in either schematic (graphic) form or in text form using an HDL. (b) Simulation: The step in a design flow where the entered design is simulated based on defined input waveforms. (c) Compilation: A program process that controls the design flow process and translates a design source code to object code for testing and downloading. (d) Download: The process in which the design is transferred from software to hardware. 24. Place and route or fitting is the process where the logic structures described by the netlist are mapped into the actual structure of the specific target device. This results in an output called a bitstream. Section -7 Test and Measurement Instruments 25. Amplitude = top of pulse minus base line V = 8 V V = 7 V 26. A flashing probe lamp indicates a continuous sequence of pulses (pulse train). Digital System Application 27. A system is a combination of logic elements and functions arranged and interconnected to perform specified tasks. 28. The binary number representing the total number of tablets is converted from parallel to serial form by the multiplexer and sent, one bit at a time, to the remote location where the demultiplexer converts the serial number back to parallel form for decoding and display. 29. A new number of tablets per bottle can be entered with the keypad. CHAPTER 2 NUMBER SYSTEMS, OPERATIONS, AND CODES 6
Section 2- Decimal Numbers. (a) 386 = 3 3 2 8 6 = 3 8 6 The digit 6 has a weight of = (b) 54,692 = 5 4 4 3 6 2 9 2 = 5, 4 6 9 2 The digit 6 has a weight of 2 = (c) 67,92 = 6 5 7 4 3 9 2 2 = 6, 7, 9 2 The digit 6 has a weight of 5 =, 2. (a) = (b) = 2 (c), = 4 (d),, = 6 3. (a) 47 = 4 2 7 = 4 7 = 4 7 (b) 9,356 = 9 3 3 2 5 6 = 9 3 5 6 = 9, 3 5 6 (c) 25, = 5 2 4 5 3 =, 2, 5 =, 2, 5, 4. The highest four-digit decimal number is 9999. Section 2-2 Binary Numbers 5. (a) = 2 2 = 2 = 3 (b) = 2 2 2 2 = 4 (c) = 2 2 2 2 = 4 2 = 7 (d) = 2 3 2 2 2 2 = 8 (e) = 2 3 2 2 2 2 = 8 = 9 (f) = 2 3 2 2 2 2 = 8 4 = 2 (g) = 2 3 2 2 2 2 = 8 2 = (h) = 2 3 2 2 2 2 = 8 4 2 = 5
6. (a) = 2 3 2 2 2 = 8 4 2 = 4 (b) = 2 3 2 = 8 2 = (c) = 2 4 2 3 2 2 = 6 8 4 = 28 (d) = 2 4 = 6 (e) = 2 4 2 2 2 = 6 4 = 2 (f) = 2 4 2 3 2 2 2 = 6 8 4 = 29 (g) = 2 4 2 2 2 2 = 6 4 2 = 23 (h) = 2 4 2 3 2 2 2 2 = 6 8 4 2 = 3 2 3 5 2 3 2 7. (a). = 2 5 2 4 2 2 2 2 2 = 32 6 2.5.25 = 5.75 (b). = 2 5 2 3 2 2 2 = 32 8 2.25 = 42.25 (c). = 2 6 2 2 2 2 2 3 = 64.5.25.25 = 65.875 (d). = 2 6 2 5 2 4 2 3 2 2 3 = 64 32 6 8.5.25 = 2.625 (e). = 2 6 2 4 2 3 2 2 2 2 = 64 6 8 4.5.25.325 = 92.65625 (f). = 2 6 2 5 2 4 2 2 4 = 64 32 6.625 = 3.625 (g). = 2 6 2 4 2 3 2 2 = 64 6 8 2.5.25 = 9.625 (h). = 2 6 2 5 2 4 2 3 2 2 2 2 2 2 2 3 2 4 2 5 = 64 32 6 8 4 2.5.25.25.625.325 = 27.96875 8. (a) 2 2 = 3 (b) 2 3 = 7 (c) 2 4 = 5 (d) 2 5 = 3 (e) 2 6 = 63 (f) 2 7 = 27 (g) 2 8 = 255 (h) 2 9 = 5 (i) 2 = 23 (j) 2 = 247 9. (a) (2 4 ) < 7 < (2 5 ); 5 bits (b) (2 5 ) < 35 < (2 6 ); 6 bits (c) (2 5 ) < 49 < (2 6 ); 6 bits (d) (2 6 ) < 68 < (2 7 ); 7 bits (e) (2 6 ) < 8 < (2 7 ); 7 bits (f) (2 6 ) < 4 < (2 7 ); 7 bits (g) (2 7 ) < 32 < (2 8 ); 8 bits (h) (2 7 ) < 25 < (2 8 ); 8 bits
. (a) through 7:,,,,,,, (b) 8 through 5:,,,,,,, (c) 6 through 3:,,,,,,,,,,,,,,, (d) 32 through 63:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (e) 64 through 75:,,,,,,,,,,, Section 2-3 Decimal-to-Binary Conversion. (a) = 8 2 = 2 3 2 = (b) 7 = 6 = 2 4 2 = (c) 24 = 6 8 = 2 4 2 3 = (d) 48 = 32 6 = 2 5 2 4 = (e) 6 = 32 6 8 4 = 2 5 2 4 2 3 2 2 2 = (f) 93 = 64 6 8 4 = 2 6 2 4 2 3 2 2 2 = (g) 25 = 64 32 6 8 4 = 2 6 2 5 2 4 2 3 2 2 2 = (h) 86 = 28 32 6 8 2 = 2 7 2 5 2 4 2 3 2 = 2. (a).32..25.625...7825 =. (b).246...25.625.325.5625 =. (c).98....625.325...39625 =.
3. (a) ( LSB) 5 = 7, R = 2 = 2 =, R 2 (b) 2 2 =, R = (LSB) 7 = 3, R = 2 (MSB) 3 =, R = 2 = (MSB) =, R 2 = 5, R = 2 =, R = 2 5 = 2, R = 2 2 =, R = 2 =, R = 2 (MSB) (LSB) (d) 34 = 7, R = 2 (e) 2 4 = 2, R = (LSB) (MSB) (LSB) 7 = 8, R = 2 8 = 4, R = 2 4 = 2, R = 2 2 =, R = 2 =, R = 2 (g) 2 65 = 32, R = 32 = 6, R = 2 6 = 8, R = 2 8 = 4, R = 2 4 = 2, R = 2 2 =, R = 2 = 5, R = 2 5 = 2, R = 2 2 =, R = 2 =, R = 2 (MSB) (h) 2 73 = 36, R = (LSB) 36 = 8, 2 R = 8 = 9, 2 R = 9 2 = 4, R = 4 2 = 2, R = 2 2 =, R =
2 =, R = (MSB) (c) 28 2 = 4, R = (LSB) 4 2 = 7, R = 7 2 = 3, R = 3 2 =, R = 2 =, R = (MSB) (f) 59 = 29, 2 R = (LSB) 29 2 = 4, R = 4 2 = 7, R = 7 2 = 3, R = 3 2 =, R = 2 =, R = (MSB)
4. (a).98 2 =.96 (MSB) (b).347 2 =.694 (MSB).96 2 =.92.694 2 =.388.92 2 =.84.388 2 =.776.84 2 =.68.776 2 =.552.68 2 =.36.552 2 =.4.36 2 =.72.4 2 =.28 continue if more accuracy is desired.28 2 =.46. continue if more accuracy is desired. (c).928 2 =.856 (MSB).856 2 =.62.62 2 =.2224.2224 2 =.4448.4448 2 =.8896.8896 2 =.7792.7792 2 =.5584 continue if more accuracy is desired. Section 2-4 Binary Arithmetic 5. (a) (b) (c) (d) (e) (f) 6. (a) (b) (c) (d) (e) (f)
7. (a) (e) (b) (f) (c) (d) 8. (a) = (b) = (c) = Section 2-5 s and 2 s Complements of Binary Numbers 9. (a) The s complement of is. (b) The s complement of is. (c) The s complement of is. (d) The s complement of is. (e) The s complement of is. (f) The s complement of is. 2. Take the s complement and add : (a) = (b) = (c) = (d) = (e) = (f) = (g) = (h) = Section 2-6 Signed Numbers 2. (a) Magnitude of 29 = (b) Magnitude of 85 = 29 = 85 = (c) Magnitude of = 23 = (d) Magnitude of = 23 = 22. (a) Magnitude of 34 = (b) Magnitude of 57 = 34 = 57 = (c) Magnitude of 99 = (d) Magnitude of 5 = 99 = 5 = 23. (a) Magnitude of 2 = (b) Magnitude of 68 =
2 = 68 = (c) Magnitude of = (d) Magnitude of 25 = = 25 = 24. (a) = 25 (b) = 6 (c) = 63 25. (a) = () = 2 (b) = () = 6 (c) = () = 64 26. (a) = () = 3 (b) = () = 6 (c) = () = 65 27. (a) sign =. 2 4 exponent = 27 4 4 = Mantissa = (b) sign =. 2 exponent = 27 = 38 = Mantissa = 28. (a) Sign = Exponent = = 29 27 = 2 Mantissa =. 2 2 =.. = 5.5258789 (b) Sign = Exponent = = 24 27 = 77 Mantissa =.. 2 77 Section 2-7 Arithmetic Operations with Signed Numbers 29. (a) 33 = 5 = (c) 46 = 46 = 25 = (b) 56 = 27 = 27 = (d) = = 84 = 84 =
3. (a) (b) 3. (a) (b) 32. (a) (b) 33. Changing to 2 s complement with sign: 34. = 68 = 2, remainder of 8 25 Section 2-8 Hexadecimal Numbers 35. (a) 38 6 = (b) 59 6 = (c) A4 6 = (d) 5C8 6 = (e) 4 6 = (f) FB7 6 = (g) 8A9D 6 = 36. (a) = E 6 (b) = 2 6 (c) = 7 6 (d) = A6 6 (e) = 3F 6 (f) = 982 6 37. (a) 23 6 = 2 6 3 6 = 32 3 = 35 (b) 92 6 = 9 6 2 6 = 44 2 = 46 (c) A 6 = 6 6 = 6 = 26 (d) 8D 6 = 8 6 3 6 = 28 3 = 4 (e) F3 6 = 5 6 3 6 = 24 3 = 243 (f) EB 6 = 4 6 6 = 224 = 235 (g) 5C2 6 = 5 6 2 2 6 2 6 = 28 92 2 = 474 (h) 7 6 = 7 6 2 = 792 38. (a) 8 6 =, remainder = 8
(c) (e) C 6 (LSD) (LSD) hexadecimal number = 8 6 33 = 2, remainder = (LSD) 6 2 =, remainder = 2 6 hexadecimal number = 2 6 284 = 7, remainder = 2 = 6 7 6 =, remainder = 6 =, remainder = hexadecimal number = C 6 (g) 49 = 25, remainder = 3 6 25 = 5, remainder = = B6 6 5 =, remainder = 5 = F6 6 hexadecimal number = FB3 6 (b) (d) 4 =, remainder = 4 = E6 6 hexadecimal number = E 6 52 = 3, remainder = 4 (LSD) 6 3 =, remainder = 3 6 hexadecimal number = 34 6 289 (f) = 8, remainder = = 6 A 6 (LSD) 8 =, remainder = 4 6 =, remainder = = 6 B6 hexadecimal number = B4A 6 (h) (LSD) 65 = 46, remainder = 4 6 46 = 25, remainder = 6 6 25 =, remainder = 9 6 =, remainder = 6 hexadecimal number = 964 6 39. (a) 37 6 29 6 = 6 6 (b) A 6 6B 6 = B 6 (c) FF 6 BB 6 = BA 6 4. (a) 5 6 4 6 = 6 (b) C8 6 3A 6 = 8E 6 (c) FD 6 88 6 = 75 6
Section 2-9 Octal Numbers 4. (a) 2 8 = 8 2 8 = 8 2 = (b) 27 8 = 2 8 7 8 = 6 7 = 23 (c) 56 8 = 5 8 6 8 = 4 6 = 46 (d) 64 8 = 6 8 4 8 = 48 4 = 52 (e) 3 8 = 8 2 3 8 = 64 3 = 67 (f) 557 8 = 5 8 2 5 8 7 8 = 32 4 7 = 367 (g) 63 8 = 8 2 6 8 3 8 = 64 48 3 = 5 (h) 24 8 = 8 3 2 8 4 8 = 52 6 4 = 532 (i) 7765 8 = 7 8 3 7 8 2 6 8 5 8 = 3584 448 48 5 = 485 42. (a) (LSD) 5 =, remainder = 7 8 =, remainder = 8 octal number = 7 8 (d) (LSD) octal number = 33 8 7 = 8, remainder = 6 8 8 =, remainder = 8 (c) (LSD) 46 = 5, remainder = 6 8 =, remainder = 8 octal number = 6 8 5 =, remainder = 5 8 octal number = 56 8 (f) (LSD) 42 = 7, remainder = 6 8 7 = 2, remainder = 8 (LSD) (e) = 2, remainder = 4 8 2 =, remainder = 2 8 octal number = 26 8 2 8 =, remainder = 4 8 =, remainder = octal number = 44 8 (h) (LSD) 435 = 54, remainder = 3 8 54 = 6, remainder = 6 8 (g) (LSD) 29 = 27, remainder = 3 8 6 =, remainder = 6 8 octal number = 663 8 27 = 3, remainder = 3 8 3 =, remainder = 3 8 octal number = 333 8 (b) 27 = 3, remainder = 3 (LSD) 8 3 =, remainder = 3 8
43. (a) 3 = 8 (b) 57 8 = (c) 8 = (d) 32 8 = (e) 54 8 = (f) 4653 8 = (g) 327 8 = (h) 456 8 = (i) 23 8 = 44. (a) = 7 8 (b) = 2 8 (c) = 67 8 (d) = 52 8 (e) = 4 8 (f) = 36 8 (g) = 543 8 (h) = 263 8 (i) = 7757 8 Section 2- Binary Coded Decimal (BCD) 45. (a) = (b) 3 = (c) 8 = (d) 2 = (e) 25 = (f) 36 = (g) 44 = (h) 57 = (i) 69 = (j) 98 = (k) 25 = (l) 56 = 46. (a) = 2 4 bits binary, 8 bits BCD (b) 3 = 2 4 bits binary, 8 bits BCD (c) 8 = 2 5 bits binary, 8 bits BCD (d) 2 = 2 5 bits binary, 8 bits BCD (e) 25 = 2 5 bits binary, 8 bits BCD (f) 36 = 2 6 bits binary, 8 bits BCD (g) 44 = 2 6 bits binary, 8 bits BCD (h) 57 = 2 6 bits binary, 8 bits BCD (i) 69 = 2 7 bits binary, 8 bits BCD (j) 98 = 7 bits binary, 8 bits BCD 2 (k) 25 = 7 bits binary, 2 ibts BCD 2 (l) 56 = 2 8 bits binary, 2 bits BCD
47. (a) 4 = (b) 28 = (c) 32 = (d) 5 = (e) 86 = (f) 2 = (g) 359 = (h) 547 = (i) 5 = 48. (a) = (b) = 6 (c) = 9 (d) = 8 (e) = 9 (f) = 32 (g) = 45 (h) = 98 (i) = 87 49. (a) = 8 (b) = 237 (c) = 346 (d) = 42 (e) = 754 (f) = 8 (g) = 978 (h) = 683 (i) = 98 (j) = 6667 5. (a) (d) (g) (b) (e) (h) (c) (f)
5. (a) (c) (e) (g) (b) inval id inval id (d) inval id inval id (f) inval id inval id (h) inval id inval id
52. (a) 4 3 (c) 6 4 (e) 28 23 (g) 3 Section 2- Digital Codes (b) 5 2 (d) 7 2 (f) 65 58 (h) 295 57 53. The Gray code makes only one bit change at a time when going from one number in the sequence to the next number. Gray for 2 = Gray for 2 = 54. (a) Binary (b) Binary Gray Gray (c) Binary Gray 55. (a) Gray (b) Gray Binary Binary (c) Gray Binary 56. (a) (b) 3 (c) 6 (d) (e) 8 (f) 29 (g) 56 (h) 75 (i) 7 57. (a) CAN (b) J (c) = (d) # (e) > (f) B
58. H e l l o. # H o w # a r e # y o u? 59. 48 65 6C 6C 6F 2E 2 48 6F 77 2 6 72 65 2 79 6F 75 3F 6. 3 INPUT A, B 3 33 6 3 6 SP 2 6 I 49 6 N 4E 6 P 5 6 U 55 6 T 54 6 SP 2 6 A 4 6, 2C 6 B 42 6 Section 2-2 Error Detection and Correction Codes 6. Code (b) has five s, so it is in error. 62. Codes (a) and (c) are in error because they have an even number of s. 63. (a) (b) (c)
64. d = 4 2 p d p 2 3 = 4 3 = 8 p = 3 parity = even Bit Designation Bit Position Binary Position Number P P 2 D 3 P 3 4 D 2 5 D 3 6 Data Bits (D n ) Parity Bits (P n ) P checks bit positions, 3, 5, and 7. P = P 2 checks bit positions 2, 3, 6, and 7. P 2 = P 3 checks bit positions 3, 5, 6, and 7. P 3 = The combined code is. 65. d = 5 2 p d p 2 4 = 5 4 = p = 4 parity = odd Bit Designation Bit Position Binary Position Number P P 2 D 3 P 3 4 D 2 5 D 3 6 D 4 7 D 4 7 P 4 8 Data Bits (D n ) Parity Bits (P n ) P checks bit positions, 3, 5, 7, and 9. P = P 2 checks bit positions 2, 3, 6, and 7. P 2 = P 3 checks bit positions 4, 5, 6, and 7. P 3 = P 4 checks bit positions 8 and 9. P 4 = The combined code is. D 5 9
66. (a) Even parity P checks, 3, 5, 7 P 2 checks 2, 3, 6, 7 P 3 checks 4, 5, 6, 7 P P 2 D P 3 D 2 D 3 D 4 Check result ( good, bad) (LSB) The error position code is. The corrected code is. (b) Even parity P checks, 3, 5, 7 P 2 checks 2, 3, 6, 7 P 3 checks 4, 5, 6, 7 P P 2 D P 3 D 2 D 3 D 4 Check result ( good, bad) (LSB) 67. (a) Odd parity The error position code is. The corrected code is. P checks, 3, 5, 7, 9 P 2 checks 2, 3, 6, 7 P 3 checks 4, 5, 6, 7 P 4 checks 8, 9 P P 2 D P 3 D 2 D 3 D 4 P 4 D 5 Check result ( good, bad) (LSB). (b) The error position code is. The corrected code is Odd parity P checks, 3, 5, 7, 9 P 2 checks 2, 3, 6, 7 P 3 checks 4, 5, 6, 7 P 4 checks 8, 9 P P 2 D P 3 D 2 D 3 D 4 P 4 D 5 Check result ( good, bad) (LSB). The error position code is. The corrected code is
CHAPTER 3 LOGIC GATES Section 3- The Inverter. See Figure 3-. 2. B: LOW, C: HIGH, D: LOW, E: HIGH, F: LOW Section 3-2 The AND Gate 3. See Figure 3-2. 4. See Figure 3-3.
5. See Figure 3-4. 6. See Figure 3-5. Section 3-3 The OR Gate 7. See Figure 3-6. A B
8. See Figure 3-7. A B C 9. See Figure 3-8.. See Figure 3-9.
Section 3-4 The NAND Gate. See Figure 3-. 2. See Figure 3-. 3. See Figure 3-2.
4. See Figure 3-3. Section 3-5 The NOR Gate 5. See Figure 3-4. 6. See Figure 3-5.
7. See Figure 3-6. 8. See Figure 3-7. Section 3-6 The Exclusive-OR and Exclusive-NOR Gates 9. The output of the OR gate is HIGH only when one input is HIGH. The output of the OR gate is HIGH any time one or more inputs are HIGH. OR = A B AB OR = A B 2. See Figure 3-8. 2. See Figure 3-9. 22. See Figure 3-2.
Section 3-7 Programmable Logic 23. = A B 2 = A B 3 = A B 24. = A BC Row : blow Row 2: blow Row 3: blow 2 = AB C Row 4: blow Row 5: blow Row 6: blow A, A, B, B, and 3 = A BC Row 7: blow Row 8: blow Row 9: blow A, B, B, C, and C column fuses A, A, B, C, and C column fuses A, A, B, B, and C column fuses A, B, B, C, and C column fuses A, A, B, C, and C column fuses C column fuses A, B, B, C, and C column fuses A, A, B, C, and C column fuses A, A, B, B, and C column fuses Section 3-8 Fixed-Function Logic 25. The power dissipation of CMOS increases with frequency.
ICCH ICCL.6 ma 4.4 ma 26. (a) P = VCC = 5.5 V 2 = 6.5 mw 2 (b) V OH(min) = 2.7 V (c) t PLH = T PHL = 5 ns (d) V OL =.4 V (max) (e) @ V CC = 2 V, t PHL = t PLH = 75 ns; @ V CC = 6 V, t PHL = t PLH = 3 ns 27. See Figure 3-2. 28. Gate A can be operated at the highest frequency because it has shorter propagation delay times than Gate B. 29. P D = V CC I C = (5 V)(4 ma) = 2 mw 3. I CCH = 4 ma; P D = (5 V)(4 ma) = 2 mw Section 3-9 Troubleshooting 3. (a) NAND gate OK (b) AND gate faulty (c) NAND gate faulty (d) NOR gate OK (e) OR gate faulty (f) OR gate OK 32. (a) NAND gate faulty. Input A open. (b) NOR gate faulty. Input B shorted to ground. (c) NAND gate OK (d) OR gate faulty. Input A open. 33. (a) The gate does not respond to pulses on either input when the other input is HIGH. It is unlikely that both inputs are open. The most probable fault is that the output is stuck in the LOW state (shorted to ground, perhaps) although it could be open. (b) Pin 4 input or pin 6 output internally open. 34. The timer input to the AND gate is open. Check for 3-second HIGH level on this input when ignition is turned on. 35. An open seat-belt input to the AND gate will act like a constant HIGH just as if the seat belt were unbuckled.
36. Two possibilities: An input stuck LOW or the output stuck HIGH. Special Design Problems 37. See Figure 3-22. FIGURE 3-22 38. See Figure 3-23. 39. Add an inverter to the Enable input line of the AND gate as shown in Figure 3-24.
4. See Figure 3-25. 4. See Figure 3-26. FIGURE 3-42. See Figure 3-27. FIGURE 3-
43. See Figure 3-28. FIGURE 3- Multisim Troubleshooting Practice 44. Input A shorted to output. 45. Inputs shorted together. 46. No fault. 47. Output open.
CHAPTER 4 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION Section 4- Boolean Operations and Expressions. = A B C D This is an OR configuration. 2. Y = ABCDE 3. = A B C 4. (a) = (b) = (c) = (d) = (e) = (f) = = 5. (a) AB = when A =, B = (b) A BC = when A =, B =, C = (c) A B = when A =, B = (d) A B C = when A =, B =, C = (e) A B C = when A =, B =, C = (f) A B = when A =, B = (g) A BC = when A =, B =, C = 6. (a) = (A B)C B A B C A B (A B)C (b) = ( A B) C A B C A B (c) = A BC AB A B C A BC AB
(d) = (A B)( A B) A B A B A B (e) = (A BC) ( B C) A B C A BC B C Section 4-2 Laws and Rules of Boolean Algebra 7. (a) Commutative law of addition (b) Commutative law of multiplication (c) Distributive law 8. Refer to Table 4- in the textbook. (a) Rule 9: A = A (b) Rule 8: A A = (applied to st and 3rd terms) (c) Rule 5: A A = A (d) Rule 6: A A = (e) Rule : A AB = A (f) Rule : A AB = A B (applied to st and 3rd terms) Section 4-3 DeMorgan s Theorems 9. (a) A B = AB = AB (b) (c) (d) (e) A B = A B = A B A B C = A BC ABC = A B C A ( B C) = A ( B C) = A BC (f) AB CD = A B C D (g) AB CD = ( AB)( CD) = ( A B)( C D) (h) ( A B)( C D) = A B C D = A B C D
. (a) A B( C D) = AB ( C D) = A B CD (b) AB ( CD EF) = AB ( CD EF) = A B ( CD)( EF) = A B ( C D)( E F ) (c) ( A B C D) ABCD = A BCD A B C D (d) ( A B C D)( ABCD) = ( ABCD)( A B C D) = A BCD A B C D = A B C D ABCD (e) AB ( CD EF)( AB CD) = AB ( CD EF) ( AB CD) = AB ( CD)( EF) ( AB)( CD) = AB ( C D)( E F ) ABCD. (a) ( ABC )( EFG) ( HIJ)( KLM ) = ABC EFG HIJ KLM = ABC EFG HIJ KLM = ( ABC)( EFG)( HIJ)( KLM ) = ( A B C)( E F G)( H I J )( K L M ) (b) ( A BC CD) BC = A( BC)( CD) BC = A( BC)( CD) BC = A BC( C D) BC = ABC ABCD BC = ABC( D) BC = A BC BC (c) ( A B)( C D)( E F)( G H ) = ( A B)( C D)( E F)( G H ) = ABC DEFGH
Section 4-4 Boolean Analysis of Logic Circuits 2. (a) AB = (b) A = (c) A B = (d) A B C = 3. See Figure 4-. 4. See Figure 4-2.
5. See Figure 4-3. FIGURE 4-3 6. (a) = A B A B (b) = AB A B (c) = AB BC (d) = (A B)C A B C A B C (e) = ( A B)( B C) A B C A B B C Section 4-5 Simplification Using Boolean Algebra 7. (a) A(A B) = AA BB = A AB = A( B) = A (b) A( A AB) = AA AAB = AB = AB (c) BC BC = C( B B) = C() = C (d) A ( A AB) = AA AAB = A ()B = A = A
(e) A BC ABC ABC = ABC AC ( B B) = ABC AC () = A BC AC = C( A AB) = C( A B) = A C BC 8. (a) ( A B)( A C) = AA AC AB BC = A AC AB BC = A ( C B) BC = A() BC = A BC (b) A B ABC ABCD ABCDE = AB( C CD CDE) = AB( ) = A B (c) AB ABC A = AB ( A B) C A = AB AC BC A A ( B ) AC BC = A AC BC = A C BC = A C( B) = A C (d) ( A A)( AB ABC) = AAB AABC AAB AABC = AB ABC = AB( C) = AB (e) AB ( A B) C AB = AB AC BC AB = AB ( A B) C = AB ABC = AB C 9. (a) BD B( D E) D( D F) = BD BD BE DD DF = BD BE DF = BD BE DF (b) A BC ( A B C) ABCD = ABC ABC ABCD = ABC ABCD = A B( C CD) = AB( C D) = A BC ABD (c) ( B BC)( B BC )( B D) = B( C)( B C)( B D) = B ( B C)( B D) = ( BB BC)( B D) = ( B BC)( B D) = B( C)(B D) = B(B D) = BB BD = B BD = B( D) = B (d) ABCD AB( CD) ( AB) CD = ABCD AB( C D) ( A B) CD = ABCD ABC ABD ACD BCD = CD ( AB A B) ABC ABD = CD( B A B) ABC ABD = CD ( A) ABC ABD = CD ABC ABD = CD AB( CD) = CD AB (e) ABC [ AB C( BC AC)] = ABABC ABCC( BC AC) = ABC (BC AC) = ABC
2. First develop the Boolean expression for the output of each gate network and simplify. (a) See Figure 4-4. = A BC A( CD B) = ABC ACD AB = B( A AC ) = B ( A C) ACD = A B BC AC D ACD (b) See Figure 4-5. = A B ACD ABC = AB( C) ACD = A B AC D (c) See Figure 4-6. = A B BC D No further simplification is possible. (d) See Figure 4-7.
= A B AC D No further simplification is possible. Section 4-6 Standard Forms of Boolean Expressions 2. (a) ( A B)( C B) = AC BC BB AB = AC BC AB (b) ( A BC ) C = AC BCC = AC BC (c) (A C)(AB AC) = AAB AAC ABC ACC = AB AC ABC ACC = (AB AC)( C) = AB AC 22. (a) AB CD( AB CD) = AB ABCD CDCD = AB ABCD CD = AB ( AB ) CD = AB CD (b) AB ( BC BD) = ABBC ABBD = ABD = ABD (c) A B[ AC ( B C) D] = A ABC ( B C) BD = A ABC BD BCD = A( BC) BD BCD = A BD( C) = A BD 23. (a) The domain is A, B, C The standard SOP is: (b) The domain is A, B, C The standard SOP is: (c) The domain is A, B, C The standard SOP is: A BC ABC ABC ABC ABC ABC ABC ABC ABC ABC 24. (a) AB CD = ABCD ABC D ABCD ABCD ABCD ABCD ABCD (b) ABD = ABCD ABCD (c) A BD = A BCD ABCD ABC D ABCD ABCD ABCD ABC D ABCD ABCD ABCD 25. (a) A BC ABC ABC ABC : (b) ABC ABC ABC : (c) ABC ABC ABC : 26. (a) ABCD ABC D ABCD ABCD ABCD ABCD ABCD : (b) ABCD ABCD : (c) A BCD ABCD ABC D ABCD ABCD ABCD ABC D ABCD ABCD ABCD : 27. (a) ( A B C)( A B C)( A B C)( A B C) (b) ( A B C)( A B C)( A B C)( A B C)( A B C) (c) ( A B C)( A B C)( A B C)( A B C)( A B C) 28. (a) ( A B C D)( A B C D)( A B C D)( A B C D)( A B C D)
) )( )( )( ( D C B A D C B A D C B A D C B A (b) ) )( )( )( ( D C B A D C B A D C B A D C B A ( )( )( )( )( ) A B C D A B C D A B C D A B C D A B C D ) )( )( )( )( ( D C B A D C B A D C B A D C B A D C B A (c) ) )( )( )( ( D C B A D C B A D C B A D C B A ) )( ( D C B A D C B A Section 4-7 Boolean Expressions and Truth Tables 29. (a) A B C (b) Y Z Q
3. (a) A B C D (b) W Y Z Q 3. (a) C AB ABC ABC ABC ABC ABC AC ABC B A = (b) YZ WZ YZ W YZ W YZ W YZ W YZ = Z W Y W Y Z W Y Z YZ W WYZ WY Z W YZ W YZ Y Z W A B C W Y Z Q
32. (a) A B C (b) A B C D 33. (a) A B C (b) A B C D 34. (a) = ABC ABC ABC BC A = ) )( )( )( ( C B A C B A C B A C B A (b) = ABC ABC C AB = ) )( )( )( )( ( C B A C B A C B A C B A C B A (c) = D ABC ABCD ABC D ABCD ABCD ABCD BC D A = ) )( )( )( )( ( D C B A D C B A D C B A D C B A D C B A ) )( )( )( ( D C B A D C B A D C B A D C B A (d) = ABCD ABCD ABCD ABCD ABCD ABCD BCD A = ) )( )( )( )( ( D C B A D C B A D C B A D C B A D C B A ) )( )( )( ( D C B A D C B A D C B A D C B A Section 4-8 The Karnaugh Map 35. See Figure 4-8.
36. See Figure 4-9. 37. See Figure 4-. Section 4-9 Karnaugh Map SOP Minimization 38. See Figure 4-. 39. See Figure 4-2.
= DF E F 4. (a) AB ABC ABC = AB( C C) ABC ABC = ABC ABC ABC ABC = ABC ABC ABC (b) (c) A BC = A( B B)( C C) ( A A) BC = ( AB AB)( C C) ( A A) BC = ABC ABC ABC ABC ABC ABC = ABC ABC ABC ABC ABC A BCD AC D BCD ABC D = A BCD A( B B) CD ( A A) BCD ABCD = = A BCD ABC D ABCD = ABCD ABCD ABC D (d) A B ABCD CD BCD ABCD = A B( C C)( D D) ABCD ( A A)( B B) CD ( A A) BCD ABCD = A BCD ABCD ABC D ABCD ABCD ABCD ABCD ABCD A BCD ABCD ABCD ABCD = A BCD ABCD ABC D ABCD ABCD ABCD ABCD ABCD ABCD = A BCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABC D 4. See Figure 4-3. 42. See Figure 4-4.
43. Plot the s from Figure 4-62 in the text on the map as shown in Figure 4-5 and simplify. 44. Plot the s from Figure 4-63 in the text on the map as shown in Figure 4-6 and simplify. 45. See Figure 4-7.
Section 4- Karnaugh Map POS Minimization 46. See Figure 4-8. 47. See Figure 4-9.
48. See Figure 4-2. 49. See Figure 4-2. 5. See Figure 4-22. = AC BC
Section 4- Five-Variable Karnaugh Maps 5. See Figure 4-23. 52. See Figure 4-24.
Section 4-2 VHDL 53. entity AND_OR is port (A, B, C, D, E, F, G, H, I: in bit; : out bit); end entity AND_OR; architecture Logic of AND_OR is begin <= (A and B and C) or (D and E and F) or (G and H and I); end architecture Logic; 54. The VHDL program: entity SOP is port (A, B, C: in bit; : out bit); end entity SOP; architecture Logic of SOP is begin Y <= (A and not B and C) or (not A and not B and C) or (A and not B and not C) or (not A and B and C); end architecture Logic; Digital System Application 55. An LED display is more suitable for low-light conditions because LEDs emit light and LCDs do not. 56. The codes,,,,, and correspond to nondecimal digit values and are not used in the BCD code. 57. The standard SOP expression for segment b is: b = D CBA DCBA DCB A DCBA DCBA DCBA DCBA DCBA This expression is minimized in Figure 4-25. There are 6 fewer gates and one fewer inverters as a result of minimization. 58. The standard SOP expression FIGURE for 4- segment c is: 25 c = D CBA DCBA DCBA DCBA DCB A DCB A DCBA DCBA DCBA This expression is minimized in Figure 4-26. There are 9 fewer gates and 3 fewer inverters as a result of minimization.
FIGURE 4-26 The standard SOP expression for segment d is: d = D CBA DCB A DCBA DCBA DCB A DCB A DCBA This expression is minimized in Figure 4-27. There are 3 fewer gates and fewer inverters as a result of minimization. FIGURE 4-27 The standard SOP expression for segment e is: e = D CBA DCB A DCB A DCB A This expression is minimized in Figure 4-28. There are 2 fewer gates and 2 fewer inverters as a result of minimization. FIGURE 4-28
The standard SOP expression for segment f is: f = D CBA DCB A DCBA DCB A DCB A DCBA This expression is minimized in Figure 4-29. There are 3 fewer gates and 2 fewer inverters as a result of minimization. FIGURE 4-29 The standard SOP expression for segment g is: g = D CB A DCBA DCBA DCBA DCB A DCB A DCBA This expression is minimized in Figure 4-3. There are 4 fewer gates and fewer inverters as a result of minimization. FIGURE 4-4- 3 3 Special Design Problems 59. Connect the OR gate output for each segment to an inverter and then use the inverter output to drive the segment.
6. See Figure 4-3. The POS implementation requires one 3-input OR gate, one 4-input OR gate, one 2-input AND gate, and 2 inverters. The SOP implementation (see Figure 4-55 in text) requires two 2-input AND gates, one 4-input OR gate, and 2 inverters. FIGURE 4-3 6. See Figure 4-32. The POS implementation of segment b requires two 3- input OR gates, one 2-input AND gate, and 3 inverters. FIGURE 4-32 See Figure 4-33. The POS implementation of segment c requires one 3-input OR gate, and inverter. FIGURE 4-33 See Figure 4-34. THE POS implementation of segment d requires one 4- input OR gate, two 3-input OR gates, one 3-input AND gate, and 3 inverters.
FIGURE 4-34 See Figure 4-35. The POS implementation of segment e requires one 2- input OR gate, one 2-input AND gate, and 2 inverters. FIGURE 4- See Figure 4-36. The POS 35 implementation of segment f requires two 2- input OR gates, one 3-input OR gate, one 3-input AND gate, and 2 inverters. FIGURE 4-36
See Figure 4-37. The POS implementation of segment g requires two 3- input OR gates, one 2-input AND gate, and 3 inverters. FIGURE 4-37 62. For the POS implementation for the 7-segment decoding logic: 4 inverters: 744 4 2-input AND gates: 748 2 3-input AND gates: 74 9 3-input OR gates: 5 7432s 2 4-input OR gates: 2 7432s 3 2-input OR gates: 7432 Total ICs for the POS: one 744, one 748s, one 74, and eight 7432s Multisim Troubleshooting Practice 63. Input A inverter output open. 64. Input A of segment e OR gate open. 65. Segment b OR gate output open.
CHAPTER 5 COMBINATIONAL LOGIC ANALYSIS Section 5- Basic Combinational Logic Circuits. See Figure 5-. 2. (a) = A B A AC (b) = A B ACD DBD 3. (a) = ABB (b) = AB B (c) = A B (d) = (A B) AB (e) = ABC (f) = ( A B)( B C) 4. See Figure 5-2 for the circuit corresponding to each expression. (a) = (A B)(C D) = AC AD BC BD (b) = AB C CD = ( ABC )( CD) = ( A B) CCD = ACD BCD (c) = (AB C)D E = ABD CD E (d) = ( A B)( BC) D = ( A B)( BC) D = A B BC D = A B D (e) = ( AB C) D E = ( AB C) D E = ABD CD E (f) = ( AB CD)( EF GH) = ( AB CD)( EF GH) = ( AB CD) ( EF GH) = ( AB )( CD) ( EF)( GH ) = ( A B)( C D) ( E F)( G H ) = AC BC AD BD EG FG EH F H
5. (a) = ABB A B (d) = (A B) AB A B (b) = AB B A B (e) = ABC A B C (c) = B A A B (f) = ) )( ( C B B A A B C
6. (a) = (A B)(C D) A B C D (b) = CD C AB A B C D (c) = (AB C)D E A B C D E A B C D E (d) = D BC B A ) )( ( A B C D
(e) = E D C AB ) ( A B C D E A B C D E (f) = ) )( ( GH EF CD AB A B C D E F G H I For all other entries =. = don t care An abbreviated table is shown because there are 256 combinations. 7. = ) )( ( ) )( ( B A B A AB AB AB B A = = Section 5-2 Implementing Combinational Logic 8. See Figure 5-3.
9. See Figure 5-4.
. See Figure 5-5.. = A BC ABC ABC ABC ABC See Figure 5-6.
2. = A BC D ABCD ABCD ABCD ABCD ABCD ABCD ABCD See Figure 5-7. FIGURE 5-7 3. = AB ABC = AB( C) = AB Since C is a don t care variable, the output depends only on A and B as shown by the two-variable truth table above which is implemented with the AND gate in Figure 5-8. 4. = ( AB )( B C) C = ( AB)( B C) C = ( AB)( B C) C = ( A B)( BC) C = ( A BC BC) C = ABC BC = BC( A ) = BC See Figure 5-9. The output is dependent only on B and C. The value of A does not matter. The NOR gate behaves as a negative-and.
5. (a) = AB BC No simplification. See Figure 5-. = AB BC (b) = AB ( C) = AB AC No simplification. Equation can be expressed in another form, as indicated in Figure 5-. (c) = AB AB = A( B B) = A A direct connection from input to output. No gates required. (d) = ABC B( EF G) = A B C BEF BG = A C BEF B G = A C B EF G See Figure 5-2. (e) = A(BC(A B C D)) = ABCA ABCB ABCC ABCD = ABC ABC ABC ABCD = ABC ABC( D) = ABC ABC = ABC See Figure 5-3.
(f) = B ( CDE EFG)( AB C) = ( BCDE BEFG)( A B C) = A BC DE ABEFG BC DE BC EFG = BC DE( A ) ABEFG BCEFG = BC DE ABEFG BC EFG See Figure 5-4. 6. (a) = A B CD ( A B)( ACD BE) = A B CD AB( ACD B E) = A B CD AB ABE = A( B B) CD ABE = A ABE CD = A( BE) CD = A CD See Figure 5-5. (b) = AB CD DEF AF = ABCD DEF A F = A BC D F DE See Figure 5-6.
(c) = A ( B C( D E)) = A( B CD CE) = A B ACD ACE See Figure 5-7. 7. The SOP expressions are developed as follows and the resulting circuits are shown in Figure 5-8. (a) = (A B)(C D) = AC AD BC BD (b) = AB C CD = ( ABC )( CD) = ( A B) CCD = A CD BCD (c) = (AB C)D E = ABD CD E (d) = ( A B)( BC) D= ( A B)( BC) D= A B BC D = A B( C) D = A B D (e) = ( AB C) D E = ( AB C) D E = ABD CD E (f) = ( AB CD)( EF GH ) = ( AB CD)( EF GH ) = ( AB CD) ( EF GHG) = ( AB)( CD) ( EF)( GH ) = ( A B)( C D) ( E F)( G H ) = AC BC AD BD EG FG EH FH
Section 5-3 The Universal Property of NAND and NOR Gates 8. See Figure 5-9. 9. = ( AB )( B C) C See Figure 5-2. = ( AB)( B C) C 2. See Figure 5-2.
2. See Figure 5-22. Section 5-4 Combinational Logic Using NAND and NOR Gates 22. (a) = ABC See Figure 5-23. (b) = ABC See Figure 5-24. (c) = A B See Figure 5-25. (d) = A B C See Figure 5-26.
(e) = AB CD See Figure 5-27. (f) = (A B)(C D) See Figure 5-28. (g) = AB [ C( DE AB) BCE] See Figure 5-29. See Figure 5-29.
23. (a) = ABC See Figure 5-3. (b) = ABC See Figure 5-3. (c) A B See Figure 5-32. (d) = A B C See Figure 5-33. (e) = AB CD See Figure 5-34. (f) = (A B)(C D) See Figure 5-35. (g) = AB [ C( DE AB) BCE] See Figure 5-36.
24. (a) = AB See Figure 5-37. (b) = A B See Figure 5-38. (c) = AB C See Figure 5-39. (d) = ABC D See Figure 5-4.
(e) = A B C See Figure 5-4. (f) = ABCD See Figure 5-42. (g) = A(CD B) = ACD AB See Figure 5-43. (h) = AB(C DEF) CE(A B F) = ABC ABDEF CEA CEB CEF See Figure 5-44.
25. (a) = AB BC See Figure 5-45. (b) = A ( B C) = AB AC See Figure 5-46. (c) = A B AB See Figure 5-47. (d) = ABC B( EF G) = A B C BEF BG See Figure 5-48.
(e) = A[BC(A B C D)] = ABCA ABCB ABCC ABCD = ABC ABC ABC ABCD ABC( D) = ABC See Figure 5-49. (f) = B ( CDE EFG)( AB C) = B( CDE EFG)( A B C) = B ( ACDE AEFG BCDE BEFG CDE CEFG) = A BEFG BBEFG BC DE BC EFG = A BEFG BC DE BC EFG See Figure 5-5. Section 5-5 Logic Circuit Operation with Pulse Waveform Inputs 26. = A B B = ABB = The output is always LOW. 27. = ( AB)B = A B B = A B See Figure 5-5.
28. is HIGH when ABC are all HIGH or when A is HIGH and B is LOW and C is LOW or when A is HIGH and B is LOW and C is HIGH. = ABC ABC ABC See Figure 5-52. 29. is HIGH when A is HIGH, B is LOW, and C is LOW. We do not know if is HIGH when all inputs are HIGH. = A BC See Figure 5-53.
3. See Figure 5-54. 3. The output pulse is sufficiently wide. It is greater than 25 ns. A maximum is not specified. See Figure 5-55.
Section 5-6 Combinational Logic with VHDL 32. entity Circuit5_5b is port (A, B, C, D: in bit; : out bit); end entity Circuit5_5b; architecture LogicFunction of Circuit5_5b is begin <= not(not A and B) or (not A and C and D) or (D and B and not D); end architecture LogicFunction; 33.(e) entity Circuit5_52e is port (A, B, C: in bit; : out bit); end entity Circuit5_52e; architecture LogicFunction of Circuit5_52e is begin <= (not A and B) or B or (B and not C) or (not A and not C) or (B and not C) or not C; end architecture LogicFunction; (f) entity Circuit5_52f is port (A, B, C: in bit; : out bit); end entity Circuit5_52f; architecture LogicFunction of Circuit5_52f is begin <= (A or B) and (not B or C); end architecture Logic Function; 34. See Figure 5-56 for input/output, gate, and signal labeling. IN IN2 IN3 IN4 A G GOUT A B G2 A B G3 G2OUT A G4OUT B G4 G3OUT FIGURE 5-58 A B G5 G5OUT A G6 OUT --Program for the logic circuit in Figure 5-56 (textbook Figure 5-53(d)) entity (Circuit5_53d is port (IN, IN2, IN3, IN4: in bit; OUT: out bit); end entity Circuit5_53d; architecture LogicOperation of Circuit5_53d is --Component declaration for inverter component Inverter is port (A: in bit; : out bit); end component Inverter; --Component declaration for NOR gate component NORgate is port (A, B: in bit; : out bit); end component NOR gate; --Component declaration for NAND gate component NANDgate is port (A, B: in bit; : out bit); end component NANDgate; signal GOUT, G2OUT, G3OUT, G4OUT, G5OUT: bit; begin G: Inverter port map (A => IN, => GOUT);
G2: NORgate port map (A => GOUT, B => IN2, => G2OUT); G3: NAND gate port map (A => IN2, B => IN3, => G3OUT); G4: NANDgate port map (A => G2OUT, B => G3OUT, => G4OUT); G5: NORgate port map (A => G4OUT, B => IN4, => G5OUT); G6: Inverter port map (A => G5OUT, => OUT); end architecture LogicOperation; 35. See Figure 5-57 for input/output, gate, and signal labeling. IN IN2 IN3 IN4 IN5 IN6 IN7 IN8 A B G A B G2 A B G3 A B G4 GOUT G2OUT G3OUT G4OUT A B G5 A B G6 G5OUT G6OUT A B G7 OUT FIGURE 5-59 --Program for the logic circuit in Figure 5-57 (textbook Figure 5-53(f)) entity Circuit5_53f is port (IN, IN2, IN3, IN4, IN5, IN6, IN7, IN8: in bit; OUT: out bit); end entity Circuit5_53f; architecture LogicFunction of Circuit5_53f is --Component declaration for NAND gate component NANDgate is port (A, B: in bit; : out bit); end component NANDgate; signal GOUT, G2OUT, G3OUT, G4OUT, G5OUT, G6OUT: bit; begin G: NANDgate port map (A => IN, B => IN2, => GOUT); G2: NANDgate port map (A => IN3, B => IN4, => G2OUT); G3: NANDgate port map (A => IN5, B => IN6, => G3OUT); G4: NANDgate port map (A => IN7, B => IN8, => G4OUT); G5: NANDgate port map (A => GOUT, B => G2OUT, => G5OUT); G6: NANDgate port map (A => G3OUT, B => G4OUT, => G6OUT); G7: NANDgate port map (A => G5OUT, B => G6OUT, => OUT); end architecture LogicFunction; 36. = A BC ABC ABC ABC ABC This is the SOP expression for the function in Table 5-8 of the textbook. The following program applies the data flow approach for this logic function. --Program for Table5_8 SOP logic entity Table5_8 is port (A, B, C: in bit; : out bit); end entity Table5_8; architecture LogicOperation of Table5_8 is begin <= (not A and not B and not C) or (not A and B and not C) or (A and not B and not C) or (A and B and not C) or (A and B and C); end architecture LogicOperation;
37. --Program for textbook Figure5_64 data flow approach entity Fig5_64 is port (A, B, C, D, E: in bit; : out bit); end entity Fig5_64; architecture DataFlow of Fig5_64 is begin <= (A and B and C) or (D and not E) end architecture DataFlow; See Figure 5-58 for the circuit in textbook Figure 5-64 modified for the structural approach. IN IN2 IN3 IN4 IN5 A GOUT B G A INVOUT INV A G2OUT B G2 A B G3OUT G3 A B G4 OUT FIGURE 5-58 --Program for textbook Figure5_64 structural approach entity Fig5_64 is port (IN, IN2, IN3, IN4, IN5: in bit; OUT: out bit); end entity Fig5_64; architecture Structure of Fig5_64 is --Component declaration for AND gate component AND_gate is port (A, B: in bit; : out bit); end component AND_gate; --Component declaration for OR gate component OR_gate is port (A, B: in bit; : out bit); end component OR_gate; --Component declaration for Inverter component Inverter is port (A: in bit; : out bit); end component Inverter; signal GOUT, G2OUT, G3OUT, INVOUT: bit; begin G: AND_gate port map (A => IN, B => IN2, => GOUT); G2: AND_gate port map (A => GOUT, B => IN3, => G2OUT); INV: Inverter port map (A => IN5, => INVOUT); G3: AND_gate port map (A => IN4, B => INVOUT, => G3OUT); G4: OR_gate port map (A => G2OUT, B => G3OUT, => OUT); end architecture Structure; 38. --Program for textbook Figure5_68 data flow approach entity Fig5_68 is port (A, B, C, D, E: in bit; : out bit); end entity Fig5_68; architecture DataFlow of Fig5_68 is begin <= (not A or not B or C) and E or (C or not D) and E; end architecture DataFlow; See Figure 5-59 for the circuit in textbook Figure 5-68 labeled for the structural approach.
IN IN2 IN3 IN4 IN5 A INV A G3OUT B C G3 INVOUT A B G5OUT G5 A B G2 A B G4 G2OUT G4OUT A B G OUT FIGURE 5-6 G3OUT); --Program for textbook Fig5_68 structural approach entity Fig5_68 is port (IN, IN2, IN3, IN4, IN5: in bit; OUT: out bit); end entity Fig5_68; architecture Structure of Fig5_68 is --Component declaration for 3-input NAND gate component NAND_gate3 is port (A, B, C: in bit; : out bit); end component NAND_gate3; --Component declaration for 2-input NAND gate component NAND_gate2 is port (A, B: in bit; : out bit); end component NAND_gate2; --Component declaration for Inverter component Inverter is port (A: in bit; : out bit); end component Inverter; signal G2OUT, G3OUT, G4OUT, G5OUT, INVOUT: bit; begin G: NAND_gate2 port map (A => G2OUT, B => G4OUT, => OUT); G2: NAND_gate2 port map (A => G3OUT, B => IN5, => G2OUT); INV: Inverter port map (A => IN3, => INVOUT); G3: NAND_gate3 port map (A => IN, B => IN2, C => INVOUT, => G4: NAND_gate2 port map (A => IN5, B => G5OUT, => G4OUT); G5: NAND_gate2 port map (A => INVOUT, B => IN4, => G5OUT); end architecture Structure; 39. From the VHDL program, the logic expression is stated as a Boolean expression as follows: = ( AB AC AD BC BD DC) = (( A B)( A C)( A D)( B C)( B D)( D C)) = ( A B)( A C)( A D)( B C)( B D)( D C) The truth table is: A B C D
4. --Program for textbook Figure5_62 data flow approach entity Fig5_62 is port (A, A2, B, B2: in bit; : out bit); end entity Fig5_62; architecture LogicCircuit of Fig5_62 is begin <= (A and A2) or (A2 and not B) or (not B and not B2) or (not B2 and A); end architecture LogicCircuit;
4. The AND gates are numbered top to bottom G, G2, G3, G4. The OR gate is G5 and the inverters are, top to bottom. G6 and G7. Change A, A 2, B, B 2 to IN, IN2, IN3, IN4 respectively. Change to OUT. entity Circuit5_62 is port (IN, IN2, IN3, (IN4: in bit; OUT: out bit); end entity Circuit 5_62; architecture Logic of Circuit 5_62 is component AND_gate is port (A, B: in bit; : out bit); end component AND_gate; component OR_gate is port (A, B, C, D: in bit; : out bit); end component OR_gate; component Inverter is port (A: in bit; : out bit); end component Inverter; signal GOUT, G2OUT, G3OUT, G4OUT, G5OUT, G6OUT, G7OUT: bit; begin G: AND_gate port map (A => IN, B => IN2, => GOUT); G2: AND_gate port map (A => IN2, B => G6OUT, => G2OUT); G3: AND_gate port map (A => G6OUT, B => G7OUT, => G3OUT); G4: AND_gate port map (A => G7OUT, B => IN, => G4OUT); G5: OR_gate port map (A => GOUT, B => G2OUT, => G3OUT, D => G4OUT, => OUT); G6: Inverter port map (A => IN3, => G6OUT); G7: Inverter port map (A => IN4, => G7OUT); end architecture Logic; Section 5-7 Troubleshooting 42. = AB CD = ABCD is HIGH only when ABCD are all HIGH. This does not occur in the waveforms, so should remain LOW. The output is incorrect. 43. = ABC DE Since is the same as the G 3 output, either G or G 2 has failed with its output stuck LOW. 44. = AB CD EF does not go HIGH when C and D are HIGH. G 2 has failed with the output open or stuck HIGH or the corresponding input to G 4 is open.
45. See Figure 5-6. Driving gate Load gates 4 3 2 9 8 4 3 2 9 8 2 2 3 4 Load gate 5 6 7 FIGURE 5-2 3 4 5 6 7 46. = A B CD EF = ( AB)( CD)( EF) = (A B)(C D)(E F) Since does not go HIGH when C or D is HIGH, the output of gate G 2 must be stuck LOW. 47. (a) = ( A B C) E ( C D) E = AE BE CE CE DE = A E BE CE DE See Figure 5-6. E FIGURE 5- (b) = E E( D C) = E( D C) = E Waveform is the same as waveform E, in Figure 5-6. Since this is the correct waveform, the open output of gate G 3 does not show up for this particular set of input waveforms.
(c) = E E( A B C) = E( A B C) = E Again waveform is the same as waveform E. As strange as it may seem, the shorted input to G 5 does not affect the output for this particular set of input waveforms. Conclusion: the two faults are not indicated in the output waveform for these particular inputs. 48. TP = A B CD The output of the C D gate is stuck LOW. See Figure 5-62. FIGURE 5- FIGURE 5- Digital System Application 49. See Figure 5-63. FIGURE 5-63 5. See Figure 5-64. 5. See Figure 5-65. FIGURE 5-64
Special Design Problems FIGURE 5-65 52. A 3 A 2 A A
See Figure 5-66. FIGURE 5-66 53. Let = Lamp on A = Front door switch on A = Front door switch off B = Back door switch on B = Back door switch off = A B AB. This is an OR operation. See Figure 5-67. FIGURE 5-67 54. V CHEM = T H TC LH. See Figure 5-68. FIGURE 5-68
55. See Figure 5-69. FIGURE 5-69 Multisim Troubleshooting Practice 56. Pin B of G open. 57. Pin C of OR gate open. 58. Inverter input open. 59. No fault.
CHAPTER 6 FUNCTIONS OF COMBINATIONAL LOGIC Section 6- Basic Adders. (a) OR (upper) output =, Sum output =, AND (upper) output =, AND (lower) output =, Carry output = (b) OR (upper) output =, Sum output =, AND (upper) output =, AND (lower) output =, Carry output = (c) OR (upper) output =, Sum output =, AND (upper) output =, AND (lower) output =, Carry output = 2. (a) A =, B =, C in = (b) A =, B =, C in = or A =, B =, C in = or A =, B =, C in = (c) A =, B =, C in = (d) A =, B =, C in = or A =, B =, C in = or A =, B =, C in = 3. (a) Σ =, C out = (b) Σ =, C out = (c) Σ =, C out = (d) Σ =, C out = Section 6-2 Parallel Binary Adders 4. See Figure 6-. FIGURE 6-
5. See Figure 6-2. FIGURE 6-6. See Figure 6-3. 7. FIGURE 6- A 4 A 3 A 2 A B 4 B 3 B 2 B Σ 5 Σ 4 Σ 3 Σ 2 Σ Σ = Σ 2 = Σ 3 = Σ 4 = Σ 5 =
8. Σ outputs should be C out Σ 4 Σ 3 Σ 2 Σ =. The Σ 3 output (pin 2) is HIGH and should be LOW. See Figure 6-4. FIGURE 6- Section 6-3 Ripple Carry Versus Look-Ahead Carry Adders 9. t p(tot) = 4 ns 6(25 ns) 35 ns = 225 ns. Full-adder 5: C in5 = C out 4 C out5 = C g5 C p5 C g4 C p5 C p4 C g3 C p5 C p4 C p3 C g2 C p5 C p4 C p3 C g2 C g C p5 C p4 C p3 C p2 C p C in The logic to be added to text Figure 6-8 is shown in Figure 6-5. Section 6-4 Comparators FIGURE 6-5. The A = B output is HIGH when A = B and A = B. See Figure 6-6.
FIGURE 6-2. See Figure 6-7. FIGURE 6-3. (a) A > B:, A = B:, A < B: (b) A > B:, A = B:, A < B: (c) A > B:, A = B:, A < B: Section 6-5 Decoders 4. (a) A 3 A 2 A A = (b) A 3 A 2 A A = (c) A 3 A 2 A A = (d) A 3 A 2 A A =
5. See Figure 6-8. FIGURE 6-6. Change the AND gates to NAND gates in Figure 6-8. 7. = A 3 A2 A A A3 A2 A A A3 A2 A A A3 A2 A A See Figure 6-9. FIGURE 6-
8. Y = A 2A A A2 A A A2 A A See Figure 6-. 9. See Figure 6-. FIGURE 6- FIGURE 6-2. 6 9 4 4 4 8 Section 6-6 Encoders 2. A, A, and A 3 are HIGH. A 3 A 2 A A =, which is an invalid BCD code. 22. Pin 2 is for decimal 5, pin 5 is for decimal 8, and pin 2 is for decimal 2. The highest priority input is pin 5. The completed outputs are: A 3 A2 A A =, which is binary 8 (). Section 6-7 Code Converters 23. (a) 2 = BCD = 2
(b) 8 = BCD = 2 (c) 3 = BCD = 2 (d) 26 = BCD = 2 (e) 33 = BCD = 2 24. (a) binary (b) binary gray gray (c) binary (d) binary gray gray See Figure 6-2. FIGURE 6-25. (a) gray (b) gray binary binary (c) gray (d) gray binary binary See Figure 6-3.
FIGURE 6- Section 6-8 Multiplexers (Data Selectors) 26. S S = selects, D, therefore Y =. 27. See Figure 6-4. 28. See Figure 6-5. FIGURE 6- FIGURE 6-
Section 6-9 Demultiplexers 29. See Figure 6-6. Section 6- Parity Generators/Checkers 3. See Figure 6-7. FIGURE 6- FIGURE 6-
3. See Figure 6-8. FIGURE 6- Section 6- Troubleshooting 32. The outputs given in the problem are incorrect. By observation of these incorrect waveforms, we can conclude that the outputs of the device are not open or shorted because both waveforms are changing. Observe that at the beginning of the timing diagram all inputs are but the sum is. This indicates that an input is stuck HIGH. Start by assuming that C in is stuck HIGH. This results in Σ and C out output waveforms that match the waveforms given in the problem, indicating that C in is indeed stuck HIGH, perhaps shorted to V CC. See Figure 6-9 for the correct output waveforms. FIGURE 6-33. (a) OK (b) Segment g burned out; output G open (c) Segment b output stuck LOW 34. Step : Verify that the supply voltage is applied. Step 2: Go through the key sequence and verify the output code in Table. Key A 3 A 2 A A None
2 3 4 5 6 7 8 9 TABLE Step 3: Check for proper priority operation by repeating the key sequence in Table except that for each key closure, hold that key down and depress each lower-valued key as specified in Table 2. Hold down keys 2 3 4 5 6 7 8 9 Depress keys one at A 3 A 2 A A a time, 2,, 3, 2,, 4, 3, 2,, 5, 4, 3, 2,, 6, 5, 4, 3, 2,, 7, 6, 5, 4, 3, 2,, 8, 7, 6, 5, 4, 3, 2,, TABLE 2 35. (a) Open A input acts as a HIGH. All binary values corresponding to a BCD number having a s value of,, 4, 5, 8, or 9 will be off by 2. This will first be seen for a BCD value of. (b) Open C out of top adder. All values not normally involving a carry out will be off by 32. This will first be seen for a BCD (c) value of. The Σ 4 output of top adder is shorted to ground. Same binary values above 5 will be short by 6. The first BCD value to indicate this will be. (d) Σ 3 of bottom adder is shorted to ground. Every other set of 6 value starting with 6 will be short 6. The first BCD value to indicate this will be. 36. (a) The Y output of the 74LS39 is stuck HIGH or open; B cathode open. (b) No power; EN input to the 74LS39 is open. (c) The f output of the 74LS48 is stuck HIGH. (d) The frequency of the data select input is too low. 37.. Place a LOW on pin 7 (Enable). 2. Apply a HIGH to D and a LOW to D through D 7. 3. Go through the binary sequence on the select inputs and check Y and Y according to Table 3. S 2 S S Y Y
TABLE 3 4. Repeat the binary sequence of select inputs for each set of data inputs listed in Table 4. A HIGH on the Y output should occur only for the corresponding combinations of select inputs shown. D D D 2 D 3 D 4 D 5 D 6 D 7 Y Y S 2 S S L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H TABLE 4 38. The Σ EVEN output of the 74LS28 should be HIGH and the output of the error gate should be HIGH because of the error condition. Possible faults are:. Σ EVEN output of the 74LS28 stuck LOW. 2. Error gate faulty. 3. The ODD input to the 74LS28 is open thus acting as a HIGH. 4. The inverter going to the ODD input of the 74LS28 has an open output or the output is stuck HIGH. 39. Apply a HIGH in turn to each Data input, D through D 7 with LOWs on all the other inputs. For each HIGH applied to a data input, sequence through all eight binary combinations of select inputs (S 2 S S ) and check for a HIGH on the corresponding data output and LOWs on all the other data outputs. One possible approach to implementation is to decode the S 2 S S inputs and generate an inhibit pulse during any given bit time as determined by the settings of seven switches. The inhibit pulse effectively changes a LOW on the Y serial data line to a HIGH during the selected bit time(s), thus producing a bit error. A basic diagram of this approach is shown in Figure 6-2.
FIGURE 6-2 Digital System Application 4. See Figure 6-2. FIGURE 6-
4. See Figure 6-22. Special Design Problems FIGURE 6-42. See Figure 6-23. FIGURE 6-
43. Σ = A BCin ABC in ABC in ABCin C out = ABC in See Figure 6-24. ABC ABC ABC in in in FIGURE 6-
44. Y = A 3 A2 A A A3 A2 A A A3 A2 A A A3 A2 A A A3 A2 A A A 3 A2 A A A3 A2 A A A3 A2 A A A3 A2 A A See Figure 6-25. 74LS5 FIGURE 6-45. See Figure 6-26. FIGURE 6-
46. See Figure 6-27. FIGURE 6-47. See Figure 6-28. FIGURE 6-28 FIGURE 6-
48. See Figure 6-29. FIGURE 6-
49. See Figure 6-3. 74LS47 FIGURE 6-5. See Figure 6-3. FIGURE 6- Multisim Troubleshooting Practice 5. LSB adder carry output open. 52. Pins 4 and 5 shorted together. 53. Pin 2 of upper 7448 open. 54. Pin 3 of upper 745 open. CHAPTER 7 LATCHES, FLIP-FLOPS, and TIMERS Section 7- Latches. See Figure 7-.
FIGURE 7-2. See Figure 7-2. FIGURE 7-2 3. See Figure 7-3. FIGURE 7-3
4. See Figure 7-4. FIGURE 7-4 5. See Figure 7-5. FIGURE 7-5 6. See Figure 7-6. FIGURE 7-6
7. See Figure 7-7. FIGURE 7-7 Section 7-2 Edge-Triggered Flip-Flops 8. See Figure 7-8. 9. See Figure 7-9. FIGURE 7-8 FIGURE 7-9
. See Figure 7-. FIGURE 7-. See Figure 7-. FIGURE 7-2. See Figure 7-2. FIGURE 7-3. See Figure 7-3. FIGURE 7-4. See Figure 7-4.
FIGURE 7-5. See Figure 7-5. FIGURE 7-6. J: K: Q: 7. See Figure 7-6. FIGURE 7-
8. See Figure 7-7. FIGURE 7- Section 7-3 Flip-Flop Operating Characteristics 9. The direct current and dc supply voltage 2. t PLH (Clock to Q): Time from triggering edge of clock to the LOW-to-HIGH transition of the Q output. t PHL (Clock to Q): Time from triggering edge of clock to the HIGH-to-LOW transition of the Q output. t PLH ( PRE to Q): Time from assertion of the Preset input to the LOW-to-HIGH transition of the Q output. t PHL ( CLR to Q): Time from assertion of the clear input to the HIGH-to-LOW transition of the Q output. 2. T min = 3 ns 37 ns = 67 ns f max = = 4.9 MHz T min
22. See Figure 7-8. FIGURE 7- FIGURE 7-23. I T = 5( ma) = 5 ma P T = (5 V)(5 ma) = 75 mw 24. See Figure 7-9. Section 7-4 Flip-Flop Applications 25. See Figure 7-2. FIGURE 7-26. See Figure 7-2. Section 7-5 One-Shots FIGURE 7-27. t W =.7RC ET =.7(3.3 kω)(2 pf) = 4.62 μs 28. R = t W RC 5 ns.7 =.32, pf ET.7 =.56 kω Section 7-6 The 555 Timer 29. See Figure 7-22.
FIGURE 7-22 3. f =.7( R 2 R ) C = = 44.6 khz.7( Ω 22 Ω)(.μ F) 2 2 3. T = = = 5 μs f 2 khz For a duty cycle of 75%: t H = 37.5 μs and t L = 2.5 μs t R R 2 = H 37.5 μs = = 26,786 Ω.7C.7(.2 μf) t L 2.5 μs R 2 = = = 8,929 Ω (use 9. kω).7c.7(.2 μf) R = 26,786 Ω R 2 = 26,786 Ω 8,929 Ω = 7,857 Ω (use 8 kω)
Section 7-7 Troubleshooting 32. The flip-flop in Figure 7-9 of the text has an internally open J input. 33. The wire from pin 6 to pin and the ground wire are reversed. Pin 7 should be at ground and pin 6 connected to pin. 34. See Figure 7-23. FIGURE 7-35. Since none of the flip-flops change, the problem must be a fault that affects all of them. The two functions common to all the flip-flops are the clock (CLK) and clear ( CLR) inputs. One of these lines must be shorted to ground because a LOW on either one will prevent the flip-flops from changing state. Most likely, the CLR line is shorted to ground because if the clock line were shorted chances are that all of the flip-flops would not have ended up reset when the power was turned on unless an initial LOW was applied to the CLR at power on. 36. Small differences in the switching times of flip-flop A and flip-flop B due to propagation delay cause the glitches as shown in the expanded timing diagram in Figure 7-24. The delays are exaggerated greatly for purposes of illustration. Glitches are eliminated by strobing the output with the clock pulse. FIGURE 7-24
37. (a) See Figure 7-25. FIGURE 7- (b) K B open acts as a HIGH and the operation is normal. The timing diagram is the same as Figure 7-25. (c) See Figure 7-26. FIGURE 7-26 (d) remains LOW if Q B = ( Q B = ). follows Q A if Q B = ( Q B = ). (e) See Figure 7-27. 38. t W =.7RC ET FIGURE 7- One-shot A: t W =.7(.22 μf)( kω) = 5.4 ms One-shot B: t W =.7(. μf)( kω) = 7 ms The pulse width of one shot A is apparently not controlled by the external components and the one-shot is producing its minimum pulse width of about 4 ns. An open pin would cause this problem. See Figure 7-28.
FIGURE 7- Digital System Application 39. For the 4 s timer let C = μf 4 s R = = 3.63 MΩ (use 3.9 MΩ) (.)(μf) For the 25 s timer let C = 2.2 μf 25 s R = =.3 MΩ (use MΩ) (.)(2.2μF) See Figure 7-29. Special Design Problems FIGURE 7-4. See Figure 7-3. FIGURE 7-
4. See Figure 7-3 for one possibility. FIGURE 7-42. Changes required for the system to incorporate a 5 s left turn signal on main:. Change the 2-bit gray code sequence to a 3-bit sequence. 2. Add decoding logic to the State Decoder to decode the turn signal state. 3. Change the Output Logic to incorporate the turn signal output. 4. Change the Trigger Logic to incorporate a trigger output for the turn signal timer. 5. Add a 5 second timer. See Figure 7-32. FIGURE 7- Multisim Troubleshooting Practice 43. Q output of U open. 44. K input of U2 open. 45. SET input of U open.
46. No fault. 47. K input of U2 open.
CHAPTER 8 COUNTERS Section 8- Asynchronous Counter Operation. See Figure 8-. FIGURE 8-2. See Figure 8-2. FIGURE 8-2 3. t p(max) = 3(8 ns) = 24 ns Worst-case delay occurs when all flip-flops change state from to or from to.
4. See Figure 8-3. FIGURE 8-3 Section 8-2 Synchronous Counter Operation 5. 8 ns, the time it takes one flip-flop to change state. 6. See Figure 8-4. FIGURE 8-4
7. Each flip-flop is initially reset. CLK J K J K J 2 K 2 J 3 K 3 Q Q Q 2 Q 3 2 3 4 5 6 7 8 9 8. See Figure 8-5. 9. See Figure 8-6. FIGURE 8-5 FIGURE 8-6
. See Figure 8-7. FIGURE 8-7. See Figure 8-8. CLK SR CEP CET PE Q Q Q 2 Q 3 TC FIGURE 8-8
Section 8-3 Up/Down Synchronous Counters 2. See Figure 8-9. 3. See Figure 8-. FIGURE 8-9 FIGURE 8- Section 8-4 Design of Synchronous Counters 4. Initially At CLK At CLK 2 At CLK 3 At CLK 4 At CLK 5 At CLK 6 Q 2 Q Q D 2 D D The sequence is to to to to to and back to, etc. 5. Initially After CLK After CLK 2 After CLK 3 After CLK 4 FF3 FF2 FF FF Q 3 Q 2 Q Q Tog Tog Tog Tog NC NC NC Tog NC NC Tog Tog NC Tog Tog Tog Tog Tog Tog Tog Tog Tog Tog Tog
After CLK 5 Tog = toggle, NC = no change them. The counter locks up in the and states, alternating between 6. NET-STATE TABLE Present Next State State Q Q Q Q TRANSITION TABLE Output State Transitions (Present state to next state) to to to to Flip-Flop Inputs Q Q J K J K to to to to See Figure 8-.
FIGURE 8-7. NET-STATE TABLE Present State Next State Q 2 Q Q Q 2 Q Q TRANSITION TABLE Output State Transitions (Present state to next state) to to to to to to to Flip-flop Inputs Q 2 Q Q J 2 K 2 J K J K to to to to to to to to to to to to to to See Figure 8-2.
FIGURE 8-8. NET-STATE TABLE Present State Next State Q 3 Q 2 Q Q Q 3 Q 2 Q Q
TRANSITION TABLE Output State Transition (Present State to next state) to to to to to to to to to to Flip-flop Inputs Q 3 Q 2 Q Q J 3 K 3 J 2 K 2 J K J K to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to Binary states for,, 2, 3, 4, and 5 are unallowed and can be represented by don t cares. See Figure 8-3. Counter implementation is straightforward from input expressions. 9. NET-STATE TABLE FIGURE 8- Present State Next State Y = (Up) Y = (Down) Q 3 Q 2 Q Q Q 3 Q 2 Q Q Q 3 Q 2 Q Q
TRANSITION TABLE Output State Transitions (Present State to next state) to to to to to to to to to to to to Y Flip-flop Inputs Q 3 Q 2 Q Q J 3 K 3 J 2 K 2 J K J K to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to See Figure 8-4.
FIGURE 8- Section 8-5 Cascaded Counters 2. (a) Modulus = 4 8 2 = 64 khz f = 4 25 Hz f 2 = 8 3.25 Hz f 3 = 2 = 25 Hz = 3.25 Hz = 5.625 Hz
(b) Modulus = 2 = 2 f = khz khz f 2 = = khz = khz khz f 3 = = Hz f 4 = Hz 2 = 5 Hz (c) Modulus = 3 6 8 = 44 2MHz f = 3 = 7 MHz 7 MHz f 2 = 6 =.67 MHz.67 MHz f 3 = 8 = 45.875 khz 45.875 khz f 4 = = 4.588 khz 4.588 khz f 5 = =.459 khz (d) Modulus = 2 4 6 8 6 = 644 2. See Figure 8-5. 39.4 khz f = 2 9.7 khz f 2 = 4 4.925 khz f 3 = 6 82.683 f 4 = 8 2.6 Hz f 5 = 6 = 9.7 khz = 4.925 khz = 82.83 Hz = 2.6 Hz = 6.4 Hz FIGURE 8-
22. See Figure 8-6. FIGURE 8-
Section 8-6 Counter Decoding 23. See Figure 8-7. FIGURE 8-24. See Figure 8-8. FIGURE 8-8
25. The states with an asterisk are the transition states that produce glitches on the decoder outputs. The glitches are indicated on the waveforms in Figure 8-8 (Problem 8-24) by short vertical lines. Initial CLK CLK 2 * CLK 3 CLK 4 * * CLK 5 CLK 6 * CLK 7 CLK 8 * * * CLK 9 CLK * CLK CLK 2 * * CLK 3 CLK 4 * CLK 5 CLK 6 * * * 26. See Figure 8-9. FIGURE 8-9
27. See Figure 8-2. FIGURE 8-2 28. There is a possibility of a glitch on decode 2 at the positivegoing edge of CLK 4 if the propagation delay of FF is less than FF or FF2. 2 There is a possibility of a glitch on decode 7 at the positivegoing edge of CLK 4 if the propagation delay of FF2 is less than FF and FF. 3 There is a possibility of a glitch on decode 7 at the positivegoing edge of CLK 6 if the propagation delay of FF is less than FF. See the timing diagram in Figure 8-2 which is expanded to show the delays. Any glitches can be prevented by using CLK as an input to both decode gates. FIGURE 8-2 Section 8-7 Counter Applications 29. For the digital clock in Figure 8-5 of the text reset to 2::, the binary state of each counter after 62 6-Hz pulses are: Hours, tens: Hours, units: Minutes, tens:
Minutes, units: Seconds, tens: Seconds, units: 3. For the digital clock, the counter output frequencies are: Divide-by-6 input counter: 6 Hz = Hz 6 Seconds counter: Hz = 6.7 mhz 6 Minutes counter: 6.7 mhz = 278 μhz 6 Hours counter: 278 μhz = 23. μhz 2 3. 53 37 26 = 64 32. See Figure 8-22. FIGURE 8-22
Section 8-9 Troubleshooting 33. (a) Q and Q will not change due to the clock shorted to ground at FF. 23. (b) Q being open does not affect normal operation. See Figure 8- (c) See Figure 8-24. FIGURE 8-23 FIGURE 8-24 (d) (e) Normal operation because an open J input acts as a HIGH. A shorted K input will pull all J and K inputs LOW and the counter will not change from its initial state. 34. (a) Q and Q will not change from initial states. (b) See Figure 8-25. FIGURE 8-25
(c) See Figure 8-26. FIGURE 8-26 (d) Normal operation. See Figure 8-27. FIGURE 8-27 (e) Both J and K of FF are pulled LOW if K is grounded, producing a no-change condition. Q also grounded. See Figure 8-28. FIGURE 8-28 35. First, determine the correct waveforms and observe that Q is correct but Q and Q 2 are incorrect in Figure 8-87 in the text. See Figure 8-29. Since Q goes HIGH and stays HIGH, FF must be in the SET state (J =, K = ). There must be a wiring error at the J and K inputs to FF; K must be connected to ground rather than to the J input. 36. Since Q 2 toggles on each clock pulse, its J and K inputs must be constantly HIGH. The most FIGURE probable 8-29 fault is that the AND gate s output is open. 37. If the Q input to the AND gate is open, the JK inputs to FF2 are as shown in Figure 8-3. FIGURE 8-3
38. Number of states = 4, 5 MHz f out = = 25 Hz 4, 76.2939 Hz is not correct. The faulty division factor is 5 MHz = 65,536 76.2939 Hz Obviously, the counter is going through all of its states. This means that the 63C 6 on its parallel inputs is not being loaded. Possible faults are: Inverter output is stuck HIGH or open. RCO output of last counter is stuck LOW. 39. Stage Open Loaded Count 63C 63C2 2 63C4 3 63C8 2 63D 2 63E 2 2 63C 2 3 63C 3 63C 3 63C 3 2 67C 3 3 6BC 4 73C 4 63C 4 2 63C 4 3 E3C f out 25.6 Hz 25.2 Hz 25.25 Hz 25.5 Hz 25. Hz 25.2 Hz 25 Hz 25 Hz 25 Hz 25 Hz 256.568 Hz 263.49 Hz 278.52 Hz 25 Hz 25 Hz.383 khz 4. The flip-flop output is stuck HIGH or open. The least significant BCD/7-segment input is open. See Figure 8-3.
FIGURE 8-3 4. Th DIV 6 is the tens of minutes counter. Q open causes a continuous apparent HIGH output to the decode 6 gate and to the BCD/7-segment decoder/driver. The apparent counter sequence is shown in the table. Actual State of Ctr. 2 3 4 Apparent state Q 3 Q 2 Q Q The decode 6 gate interprets count 4 as a 6 () and clears the counter back to (actually ). Thus, the apparent (not actual) sequence is as shown in the table. 42. There are several possible causes of the malfunction. First check power to all units. Other possible faults are listed below. Sensor Latch Action: Disconnect entrance sensor and pulse sensor input. Observation: Latch should SET. Conclusion: If latch does not SET, replace it. NOR gate Action: Pulse sensor input. Observation: Pulse on gate output. Conclusion: If there is no pulse, replace gate. Counter Action: Pulse sensor input. Observation: Counter should advance. Conclusion: If counter does not advance, replace it. Output Interface Action: Pulse sensor input until terminal count is reached. Observation: FULL indication and gate lowered Conclusion: No FULL indication or if gate does not lower, replace interface. Sensor/Cable Action: Try to activate sensor. Observation: If all previous checks are OK, sensor or cable is faulty. Conclusion: Replace sensor or cable. Digital System Application 43. The expressions for the D and the D flip-flop inputs in the
sequential logic portion of the system were developed for the System Assignment Activities and 2. Figure 8-32 shows the NAND implementation. D = Q Q T V Q T V D = Q L S Q TL QT S L S 44. See Figure 8-33. FIGURE 8-32 FIGURE 8-33 45. The time interval for the green light can be increased from 25 s to 6 s by increasing the value of either the resistor or the capacitor value by 6 s 25 s Special Design Problems 46. See Figure 8-34. = 2.4 times 74LS6 74LS6 74LS6 FIGURE 8-34 47. 65,536 3, = 35,536 Preset the counter to 35,536 so that it counts from 35,536 up to 65,536 on each full cycle, thus producing a sequence of 3, states
(modulus 3,). 35,536 = 2 = 8AD 6 See Figure 8-35. FIGURE 9- FIGURE 8-35 48. 65,536 5, = 5,536 Preset the counter to 5,536 so that it counts from 5,536 up to 65,536 on each full cycle, thus producing a sequence of 5, states (modulus 5,). 5,536 = 2 = 3CB 6
See Figure 8-36. 74HC6 74HC6 74HC6 74HC6 FIGURE 8-36 49. The approach is to preset the hours and minutes counters independently, each with a fast or slow preset mode. The seconds counter is not preset. One possible implementation is shown in Figure 8-37. FIGURE 8-37
5. See Figure 8-38. FIGURE 8-38 5. See Figure 8-39. FIGURE 8-39 52. See Figure 8-4.
FIGURE 8-4 53. NET-STATE TABLE Present State Next State Q 3 Q 2 Q Q Q 3 Q 2 Q Q TRANSITION TABLE Output State Transitions Flip-flop Inputs Q 3 Q 2 Q Q J 3 K 3 J 2 K 2 J K J K to to to to to to to to to to to to to to to to to to to to to to to to See Figure 8-4.
FIGURE 8-4
54. See Figure 8-42. FIGURE 8-42 Multisim Troubleshooting Practice 55. Q output of U3 open. 56. SET input of U open. 57. Pin A of G3 open. 58. No fault. 59. Pin 9 open.
CHAPTER 9 SHIFT REGISTERS Section 9- Basic Shift Register Functions. Shift registers store binary data in a series of flip-flops or other storage elements. 2. byte = 8 bits; 2 bytes = 6 bits Section 9-2 Serial In/Serial Out Shift Registers 3. See Figure 9-. FIGURE 9-4. See Figure 9-2. FIGURE 9-2
5. Initia lly CLK CLK 2 CLK 3 CLK 4 CLK 5 CLK 6 CLK 7 CLK 8 CLK 9 CLK CLK CLK 2 6. See Figure 9-3. FIGURE 9-3 7. See Figure 9-4. FIGURE 9-4 8. See Figure 9-5. FIGURE 9-5 Section 9-3 Serial In/Parallel Out Shift Registers 9. See Figure 9-6.
FIGURE 9-6. See Figure 9-7. FIGURE 9-7. See Figure 9-8. FIGURE 9-8
Section 9-4 Parallel In/Serial Out Shift Registers 2. See Figure 9-9. FIGURE 9-9 3. See Figure 9-. 4. See Figure 9-. FIGURE 9- FIGURE 9-5. See Figure 9-2. FIGURE 9-2
Section 9-5 Parallel In/Parallel Out Shift Registers 6. See Figure 9-3. FIGURE 9-3
7. See Figure 9-4. FIGURE 9-4 8. See Figure 9-5. FIGURE 9-5
Section 9-6 Bidirectional Shift Registers 9. Initially (76) CLK CLK 2 CLK 3 CLK 4 CLK 5 CLK 6 CLK 7 CLK 8 CLK 9 CLK CLK Shift left Shift right Shift right Shift right Shift left Shift left Shift right Shift left Shift right Shift left Shift left 2. Initially (76) CLK CLK 2 CLK 3 CLK 4 CLK 5 CLK 6 CLK 7 CLK 8 CLK 9 CLK CLK CLK 2 Shift right Shift right Shift right Shift left Shift left Shift left Shift right Shift left Shift left Shift left Shift right Shift right 2. See Figure 9-6. FIGURE 9-6
22. See Figure 9-7. Section 9-7 Shift Register Counters 23. (a) 2n = 6 (b) 2n = n = 3 n = 5 FIGURE 9-7 (c) 2n = 4 (d) 2n = 6 n = 7 n = 8 24. 2n = 8; n = 9 flip-flops Q Q Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 See Figure 9-8. FIGURE 9-8
25. See Figure 9-9. FIGURE 9-9 26. A 5-bit ring counter with stages 3, 7, and 2 SET and the remaining stages RESET. See Figure 9-2. FIGURE 9-2
Section 9-8 Shift Register Applications 27. See Figure 9-2. 74HC9 5 74HC9 5 74HC9 5 74HC9 5 FIGURE 9-2 28. The power-on LOAD input provides a momentary LOW to parallel load the ring counter when power is turned on. 29. An incorrect code may be produced. Section 9- Troubleshooting 3. Q 2 goes HIGH on the first clock pulse indicating that the D input is open. See Figure 9-22. FIGURE 9-22
3. Since the LSB flip-flop works during serial shift, the problem is most likely in gate G3. An open D 3 input at G3 will cause the observed waveform. See Figure 9-23. FIGURE 9-23 32. It takes a LOW on the RIGHT/LEFT input to shift data left. An open inverter input will keep the inverter output LOW thus disabling all of the shift-left control gates G5, G6, G7, and G8. 33. (a) No clock at switch closure due to faulty NAND gate or one-shot; open clock input to key code register; open SH/ LD input to key code register. (b) The diode in the third row is open; Q 2 output of ring counter is open. (c) (d) The NAND (negative-or) gate input connected to the first column is shorted to ground or open, preventing a switch closure transition. The 2 input to the column encoder is open. 34.. Number the switches in the matrix according to the following format: 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 5 52 53 54 55 56 57 58 59 6 6 62 63 64
2. Depress switches one at a time and observe the key code output according to the following Table. Switch number Key Code Register Q Q Q 2 Q 3 Q 4 Q 5 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 5 52 53 54 55 56 57 58 59
6 6 62 63 64 TABLE 35. (a) Contents of Data Output Register remain constant. (b) Contents of both registers do not change. (c) Third stage output of Data Output Register remains HIGH. (d) Clock generator is disabled after each pulse by the flipflop being continuously SET and then RESET. Digital System Application 36. The purpose of the Security Code logic is to accept a 4-digit code, compare it with a stored code, and if the codes match, to disarm the system for entry. 37. The states of shift registers A and C after two correct key closures are: Shift Register A: Shift Register C: 38. The states of shift registers A and B after each key closure when entering 7645 are: After key 7 is pressed: Shift register A contains Shift register B contains After key 6 is pressed: Shift register A contains Shift register B contains After key 4 is pressed: Shift register A contains Shift register B contains After key 5 (an incorrect entry) is pressed: Shift register A contains Shift register B contains
Special Design Problems 39. See Figure 9-24. FIGURE 9-24
4. Figure 9-25 shows only the 74LS64, 74LS99, and 74LS63 portions of the circuit that require modification for 6-bit conversion. FIGURE 9-25 4. See Figure 9-26 for one possible implementation. 74LS9 74LS9 FIGURE 9-26 42. One possible approach is shown in Figure 9-27.
FIGURE 9-27 43. See Figure 9-28. FIGURE 9-28 44. Register A requires 8 bits and can be implemented with one 7499. Register B requires 6 bits and can be implemented with two 7499s. Multisim Troubleshooting Practice 45. CLK input of U3 open. 46. No fault. 47. Pin 4 open. 48. No fault. 49. CLK input of U6 open. CHAPTER MEMORY AND STORAGE Section - Basics of Semiconductor Memory. (a) ROM: no read/write control (b) RAM 2. They are random access memories because any address can be accessed at any time. You do not have to go through all the preceding addresses to get to a specific address. 3. Address bus provides for transfer of address code to memory for accessing any memory location in any order for a read or a write operation. Data bus provides for transfer of data between the microprocessor and memory or input/output devices. 4. (a) A 6 = 2 = (b) 3F 6 = 2 = 63 (c) CD 6 = 2 = 25 Section -2 Random-Access Memories (RAMs)
5. ROW ROW ROW 2 ROW 3 BIT BIT BIT 2 BIT 3 6. See Figure -. FIGURE - 7. 64k 8 = 52 28 8 = 52 rows 28 8-bit columns 8. See Figure -2. FIGURE -2