Energy Efficient Full-adder using GDI Technique

Energy Efficient Full-adder using GDI Technique Balakrishna.Batta¹, Manohar.Choragudi², Mahesh Varma.D³ ¹P.G Student, Kakinada Institute of Engineering and technology, korangi, JNTUK, A.P, INDIA ²Assistant professor, Kakinada Institute of Engineering and technology, korangi, JNTUK,A.P, INDIA ³ Assistant professor, Kakinada institute of engineering and technology, korangi, JNTUK,A.P, INDIA ¹balakrishnabatta@gmail.com,²manohar.choragudi@gmail.com,³maheshvarma@gmail.com Abstract A full-adder is one of the essential component in digital circuit design, many improvements have been made to reduce the architecture of a fulladder. The proposed method aims on GDI(Gate Diffusion Input).GDI is a novel technique for low power digital circuits design in an embedded system this techniques allows reduction in power consumption, propagation delay, and transistor count of the digital circuit. This technique can be used to reduce the number of transistors compared to conventional, CPL and DPL cmos design the performance of GDI is compared with cmos and different other design technologies for several digital circuts. Index Terms CMOS, SR-CPL, DPL, GDI, PDP I. INTRODUCTION Most of the vlsi applications, such as DSP, image and video processiong and microprocessors extensively use logic gates and arthimetic circuits AND, OR Addition, subtraction and multiplication are examples of the most commonly used operations by this circuits. One bit full adder cell is the extensively used in arthimetic circuits thus, enhancing their performance is critical for enhancing the over all module performance recently building low power vlsi systems has emerged as highly in demand because of the fast growing technologies in mobile communaction and computation so designers are forced with more constraints: high speed, high throughput, small sillocon area and at the same time low power consumption The gole of this paper is designing a high speed low power full adder cell with the GDI technique. This technique was recently developed and proposes an efficient alternative for logic design in standard CMOS technologys. II. REVIEW OF PREVIOUS FULL-ADDER CELLS Many papers have been published regarding the optimization of full-adders, trying different options for the logic style (standard CMOS) differential cascade voltage switch (DCVS), complementary pass-transistor logic (CPL), dual pass transistor logic (DPL) and the logic structure are used to build the adder module. The internal logic structure shown in fig 1 has been adopted as the standard configuration in most of the enhancement developed for the 1-bit full-adder module. In this configuration the adder module is formed by three main logic blocks a XOR/XNOR gate to obtain XOR and XNOR from Block 1 and XOR blocks or multiplexers to obtain SUM(So), CARRY(Co) out puts from BLOCK 2 and BLOCK 3. Fig 1: Block diagram of full adder cell A comparative study to determine the best implementation for Block 1 was presented in and an important conclusion was pointed out in that work the major problem regarding the propagation delay for a full adder built with the logic structure shown in fig 1 is that it is necessary to obtain an www.ijrcct.org chiefeditor@ijrcct.org Page 350

intermediate signal and its complement which are used to drive the other blocks to generate the final output sum and carry. Thus the overall propagation delay and, in most of the cases, the power consumption of the fulladder depends on the delay and the voltage swing of the output signal of Block 1 and its complemented generated within the cell. It is necessary to develop a new logic structure that does not required the generation of intermediate signals to control the selection or transmission of other signals located on the critical path. applied in complementary form. i.e : every input signal and its inverse must be provided. The circuit also produces complimentary output, to be used by subsequent CPL CPL Schematic: Exclusive OR and Exclusive-NOR, denoted by and _ respectively, are binary operations that perform the following Boolean Functions- A B = A B + A B and A_B = AB + AB There are standard topologies of implementation for the full-adder cells which are used as the basis of comparison in this paper. Some of the standard implementations are as follows: CMOS logic styles have been used to implement the lowpower 1-bit adder cells. 1. The Conventional CMOS full adder (CMOS) consisted of 28 transistors and is based on the regular CMOS structure (pull -up and pulldown networks). Fig 2: Schematic of CPL Full adder cell CPL Layout: 2. The Complementary pass-transistor logic (CPL) full adder having 32 transistors and using the CPL gates. 3. The ratioed style full adder based on Pseudo logic. 4. DCVSL full adder based on Cascode Voltage Switch logic (CVSL) style. 5. The transmission-gate CMOS adder (TG - CMOS) and transmission function adder (TFA) are based on transmission gates logic. 6. The new (TG -Pseudo) full adder is based on transmission gate and pseudo logic. Complementary Pass-Transistor Logic (CPL): The complexity of full CMOS pass gate logic can be reduced dramatically by adopting another circuit called CPL. The main idea behind CPL is to use a purely NMOS pass transistor network for the logic operations. All the inputs are DPL : The other new full-adder have been designed using the logic styles DPL, and the new logic structure presented in Fig.13. Fig.15 presents a full-adder designed using a DPL logic style to build the XOR/XNOR gates, and a pass-transistor based multiplexer to obtain the So output. In Fig. 15, the SR-CPL logic style was used to build these XOR/XNOR gates. In both cases, the AND/OR gates have been built using a powerless and groundless pass-transistor configuration, www.ijrcct.org chiefeditor@ijrcct.org Page 351

respectively, and a pass-transistor based multiplexer to get the Co output. DPL Schematic: Fig 3: Schematic of DPL Full adder cell DPL Layout: which is very flexible for digital circuits. Besides, it is also power efficient without huge amount of transistor count.although GDI has the above advantages, it still has some difficulties that are needed to be solved. The major problem of a GDI cell is that it requires twin-well CMOS or silicon on insulator (SOI) process to realize. Thus, it will be more expensive to realize a GDI chip. However, if only standard pwell CMOS process can be used, the GDI scheme will face the problem of lacking driving capability which makes it difficult to realize a feasible chip. In this paper, a modified GDI scheme is proposed to adopt the general CMOS process. In addition, four 10-T based full adder are proposed using the modified GDI scheme. According to our verification, one of the four proposed adders is better than the prior 10-T based full adder design. Hence, the proposed adder can be seen as a better alternative. The basic GDI cell is shown in below. while the truth table is shown below. It should be noted that the source of the PMOS in a GDI cell is not connected to VDD while the source of the NMOS in a GDI cell is not connected to GND. This feature gives the GDI cell two extra input pins to use which makes the GDI design more flexible than an usual CMOS design. However, this feature is also the major cause of its disadvantage: special CMOS process required. To be more specific, the GDI scheme requires twin-well CMOS or silicon on insulator (SOI) process to implement which is of course more expensive than the standard p-well CMOS process. BASIC GDI CELL: III : PROPOSED SYSTEM GDI: Gate diffusion input is a novel technique for low power digital circuit design in an embedded system. This technique allows reduction in power consumption, delay and area of the circuit. This technique can be used to reduce the number of transistors compared to conventional cmos design. Recently, a novel design called Gate-Diffusion Input (GDI) is proposed by Morgenshtein et. al.. It is a genius design Fig 4: GDI basic cell Some modifications in the standard CMOS inverter derives the basic GDI cell, where the source of NMOS and PMOS are fed by input signals. www.ijrcct.org chiefeditor@ijrcct.org Page 352

GDI cell consists of three input terminals G, P and N. The various functions that can be implemented with basic GDI cell, which consists of only two transistors is as shown in below. cell. TABLE I:Various functions of GDI basic GDI xor full adder: The main advantage of GDI is large number of functions can implemented using basic GDI cell From it can be seen that large number of functions can be implemented using the basic GDI cell. MUX design is the most complex design that can be implemented with GDI, which requires only 2 transistors, which requires 8-12 transistors with the traditional CMOS or PTL design. Many functions can be implemented efficiently by GDI by means of transistor count shows the comparison between GDI and the static CMOS design in terms of transistors count. It can be seen from table that using GDI technique AND, OR, Function1, Function2, XOR, XNOR can be implemented more efficiently. However to implement NAND, NOR it requires 4 transistors as that in Static CMOS design. NAND and NOR the universal logic gates, any Boolean Function can be implemented using these gates, are most very efficient and popular with static design style. Function1 and Function2 are universal set for GDI, and consists of only two transistors, compared to NAND and NOR. These functions can be used synthesize other functions more effectively than NAND and NOR gates [2]. Gdi xor layout: Fig 5:GDI XOR Full adder cell. TABLE II:Various functions of GDI basic www.ijrcct.org chiefeditor@ijrcct.org Page 353

GDI xnor full adder: Fig 6: Schematic of XNOR Full adder Gdi xnor layout: b.power: c.delay: d.pdp(power delay product): IV. SIMULATION RESULTS a.area: www.ijrcct.org chiefeditor@ijrcct.org Page 354

V. CONCLUSION GDI technique is implemented for Basic Logic Gates. Comparisons are made among GDI, standard CMOS and some pass transistor logics CPL and DPL. The analysis shows that the GDI technique is novel and an effective technique for reducing power consumption, delay, power delay product (PDP) area and the Transistor count which will effectively reduce the size of the chip. GDI will allow high density of Fabrication as now a day s chip area is very important parameter. With respect to chip area, power consumption and transistor count, GDI technique is significantly advantageous over CPL and DPL. Circuits: A Design Methodology, 14 th ASIC/SOC Conference, Washington D.C., USA, September 2001. [2] A. M. Shams, T. K. Darwish and M. A. Bayoumi, Performance Analysis of Low-Power 1-Bit CMOS Full- Adder Cells, IEEE Trans. on VLSI Systems, vol. 10, Feb. 2002. [3] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits. Reading, Addison-Wesley, pp. 136-137. [4] N. Zhuang and H. Wu, A New Design of the CMOS Full- Adder, IEEE J. Solid-State Circuits, pp. 840-844, May 1992. [5] A. M. Shams and M. A. Bayoumi, A Novel High Performance CMOS 1-Bit Full-Adder Cell, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, pp. 478-481, May 2000. [6] E. Abu Shama, A. Elechouemi, S. Sayed and M. Bayoumi, An Efficient Low Power Basic Cell for Adders, Proc. 38 th Midwest Symposium on Circuits and Systems, pp. 306-309, 1996. [7] A. A. Fayed and M. A. Bayoumi, A Low Power 10 Transistor Full-Adder Cell for Embedded Architectures, IEEE International Symposium on Circuits and Systems, pp. 226-229, 2001. [8] Lu Junming, Shu Yan, Lin Zhenghui and Wang Ling, A Novel 10 Transistor low Power high Speed Full-Adder cell, Proc. of the 6 th International Conference on Solid- State and Integrated Circuit Technology, pp. 1155-1158, 2001. [9] Hanho Lee and G. E. Sobelman, A New Low Voltage Full- Adder Circuit, Proc. of the 7 th Great Lakes Symposium on VLSI, 1997. Authors profile: TABLE 3: Comparsion of CPL,DPL,GDIXOR and GDIXNOR ACKNOWLEDGEMENT I am very thankful to KIET college for providing a good lab facility. We simulate the results on MICROWIND, DECH and TANNER TOOLS. REFERENCES ¹BALAKRISHNA.BATTA Received his B.Tech degree in Electronics and Communication Engineering from QIS college of engineering and technology, affiliated to JNTUK, ONGOLE, ANDHRA PRADESH, INDIA in the year 2010 and pursuing M.Tech(VLSISD) in Kakinada institute of Engineering and Technology, affiliated to JNTUK, KORANGI, KAKINADA, ANDHRAPRADESH, INDIA Areas of interest layout designing and digital communication. [1] A. Morgenshtein, A. Fish, I. A. Wagner, Gate Diffusion Input (GDI) A Novel Power Efficient Method for Digital www.ijrcct.org chiefeditor@ijrcct.org Page 355

²MANOHAR.CH He completed his B.Tech in Kakinada institute of engineering and technology, affiliated to JNTUH, Korangi, Kakinada, Andhra pradesh, INDIA, and he completed his masters degree program in DECS in gudalavalleru college of Engineering and Technology, affiliated to JNTUK, currently working as assistant professor in KIET college, Korangi, Kakinada, Andhra pradesh, INDIA. Areas of intrest EMTL and Digital Electronics. ³D.Mahesh varma completed hism.sc in Electronics from DNR college of Education, Bhimavaram, India in 2005.And M.Tech in VLSI Design from Sathyabama University, Chennai, India in 2008. Currently he is working as a Assistant Professor in Kakinada Institute of Engineering and Technology from four years. His research areas include low power VLSI, LAYOUT design, leakage reduction, sensor networks, energy-efficient circuits, memory design, and sub-threshold operation. www.ijrcct.org chiefeditor@ijrcct.org Page 356