a FEATURES True Single Supply Operation Output Swings Rail-to-Rail Input Voltage Range Extends Below Ground Single Supply Capability from V to V Dual Supply Capability from. V to 8 V Excellent Load Drive Capacitive Load Drive Up to pf Minimum Output Current of ma Excellent AC Performance for Low Power 8 A Max Quiescent Current Unity Gain Bandwidth:.8 MHz Slew Rate of. V/ s Excellent DC Performance 8 V Max Input Offset Voltage V/ C Typ Offset Voltage Drift pa Max Input Bias Current Low Noise nv/ Hz @ khz APPLICATIONS Battery-Powered Precision Instrumentation Photodiode Preamps Active Filters - to -Bit Data Acquisition Systems Medical Instrumentation Low Power References and Regulators PRODUCT DESCRIPTION The AD8 is a precision, low power FET input op amp that can operate from a single supply of. V to V, or dual supplies of ±. V to ± 8 V. It has true single supply capability with an input voltage range extending below the negative rail, NULL IN +IN V S Single Supply, Rail to Rail Low Power FET-Input Op Amp AD8 FUNCTIONAL BLOCK DIAGRAM AD8 TOP VIEW (Not to Scale) 8 NC V OUT NULL allowing the AD8 to accommodate input signals below ground in the single supply mode. Output voltage swing extends to within mv of each rail providing the maximum output dynamic range. Offset voltage of 8 µv max, offset voltage drift of µv/ C, typical input bias currents below pa and low input voltage noise provide dc precision with source impedances up to a Gigaohm..8 MHz unity gain bandwidth, 9 db THD at khz and V/µs slew rate are provided for a low supply current of 8 µa. The AD8 drives up to pf of direct capacitive load and provides a minimum output current of ma. This allows the amplifier to handle a wide range of load conditions. This combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single supply user. The AD8 is available in two performance grades. The A and B grades are rated over the industrial temperature range of C to +8 C. The AD8 is offered in two varieties of 8-lead package: plastic DIP, and surface mount (SOIC). NC IN +IN V S NC = NO CONNECT AD8 TOP VIEW (Not to Scale) 8 NC V OUT NC NUMBER OF UNITS 8 9 INPUT BIAS CURRENT pa Figure. Typical Distribution of Input Bias Current Figure. Gain of Amplifier; V S =,, V IN =.V Sine Centered at. Volts REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 8/9- www.analog.com Fax: 8/-8 Analog Devices, Inc.,
AD8 SPECIFICATIONS (V S =, V @ T A = C, V CM = V, V OUT =. V unless otherwise noted.) AD8A AD8B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset..8.. mv Max Offset over Temperature....9 mv Offset Drift µv/ C Input Bias Current V O = V to V pa at T MAX... na Input Offset Current pa at T MAX.. na Open-Loop Gain V O =. V to V T MIN to T MAX R L = kω V/mV V/mV T MIN to T MAX R L = kω 8 8 V/mV 8 8 V/mV T MIN to T MAX R L = kω V/mV V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz µv p-p f = Hz nv/ Hz f = Hz nv/ Hz f = khz nv/ Hz f = khz nv/ Hz Input Current Noise. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kω to. V f = khz V O =. V to. V 9 9 db DYNAMIC PERFORMANCE Unity Gain Frequency.8.8 MHz Full Power Response V O p-p =. V khz Slew Rate V/µs Settling Time to.% V O =. V to. V.. µs to.%.8.8 µs INPUT CHARACTERISTICS Common-Mode Voltage Range. +. + V T MIN to T MAX. +. + V CMRR V CM = V to V 8 8 db T MIN to T MAX db Input Impedance Differential.. Ω pf Common Mode.8.8 Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage V OL V EE I SINK = µa mv T MIN to T MAX mv V CC V OH I SOURCE = µa mv T MIN to T MAX mv V OL V EE I SINK = ma mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = ma 8 8 mv T MIN to T MAX mv V OL V EE I SINK = ma mv T MIN to T MAX mv V CC V OH I SOURCE = ma 8 8 mv T MIN to T MAX 9 9 mv Operating Output Current ma T MIN to T MAX ma Short-Circuit Current ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current T MIN to T MAX 8 8 µa Power Supply Rejection V S + = V to V 8 8 db T MIN to T MAX db REV. C
SPECIFICATIONS (V S =, V @ T A = C, V CM = V, V OUT =. V unless otherwise noted.) REV. C AD8 AD8A AD8B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset..8.. mv Max Offset over Temperature... mv Offset Drift µv/ C Input Bias Current V O = V to V pa at T MAX... na Input Offset Current pa at T MAX.. na Open-Loop Gain V O = V to V R L = kω V/mV T MIN to T MAX V/mV R L = kω 8 8 V/mV T MIN to T MAX 8 8 V/mV R L = kω V/mV T MIN to T MAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz µv p-p f = Hz nv/ Hz f = Hz nv/ Hz f = khz nv/ Hz f = khz nv/ Hz Input Current Noise. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kω f = khz V O = ±. V 9 9 db DYNAMIC PERFORMANCE Unity Gain Frequency.9.8 MHz Full Power Response V O p-p = 9 V khz Slew Rate V/µs Settling Time to.% V O = V to ±. V.. µs to.%.8.8 µs INPUT CHARACTERISTICS Common-Mode Voltage Range. +. + V T MIN to T MAX. +. + V CMRR V CM = V to + V 8 8 db T MIN to T MAX db Input Impedance Differential.. Ω pf Common Mode.8.8 Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage V OL V EE I SINK = µa mv T MIN to T MAX mv V CC V OH I SOURCE = µa mv T MIN to T MAX mv V OL V EE I SINK = ma mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = ma 8 8 mv T MIN to T MAX mv V OL V EE I SINK = ma mv T MIN to T MAX mv V CC V OH I SOURCE = ma 8 8 mv T MIN to T MAX 9 9 mv Operating Output Current ma T MIN to T MAX ma Short-Circuit Current ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current T MIN to T MAX 8 8 µa Power Supply Rejection V S + = V to V 8 8 db T MIN to T MAX db
AD8 SPECIFICATIONS (V S = V @ T A = C, V CM = V, V OUT = V unless otherwise noted.) AD8A AD8B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset... mv Max Offset over Temperature.. mv Offset Drift µv/ C Input Bias Current V CM = V pa V CM = V pa at T MAX V CM = V... na Input Offset Current pa at T MAX.. na Open-Loop Gain V O = + V to V R L = kω V/mV T MIN to T MAX V/mV R L = kω V/mV T MIN to T MAX V/mV R L = kω V/mV T MIN to T MAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz µv p-p f = Hz nv/ Hz f = Hz nv/ Hz f = khz nv/ Hz f = khz nv/ Hz Input Current Noise. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kω f = khz V O = ± V 8 8 db DYNAMIC PERFORMANCE Unity Gain Frequency.9.9 MHz Full Power Response V O p-p = V khz Slew Rate V/µs Settling Time to.% V O = V to ± V.. µs to.%.. µs INPUT CHARACTERISTICS Common-Mode Voltage Range. +. + V T MIN to T MAX. +. + V CMRR V CM = V to V 8 9 db T MIN to T MAX db Input Impedance Differential.. Ω pf Common Mode.8.8 Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage V OL V EE I SINK = µa mv T MIN to T MAX mv V CC V OH I SOURCE = µa mv T MIN to T MAX mv V OL V EE I SINK = ma mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = ma 8 8 mv T MIN to T MAX mv V OL V EE I SINK = ma mv T MIN to T MAX mv V CC V OH I SOURCE = ma 8 8 mv T MIN to T MAX 9 9 mv Operating Output Current ma T MIN to T MAX ma Short-Circuit Current ma Capacitive Load Drive POWER SUPPLY Quiescent Current T MIN to T MAX 9 9 µa Power Supply Rejection V S + = V to V 8 8 db T MIN to T MAX db REV. C
AD8 NOTES This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+ V S V) to. Common-mode error voltage is typically less than mv with the common-mode voltage set at volt below the positive supply. V OL V EE is defined as the difference between the lowest possible output voltage (V OL ) and the minus voltage supply rail (V EE ). V CC V OH is defined as the difference between the highest possible output voltage (V OH ) and the positive supply voltage (V CC ). Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Supply Voltage................................ ±8 V Internal Power Dissipation Plastic DIP (N).............................. W SOIC (R)................................... W Input Voltage.............. ( +. V) to ( V + V S ) Output Short Circuit Duration................ Indefinite Differential Input Voltage....................... ± V Storage Temperature Range (N)......... C to + C Storage Temperature Range (R)......... C to + C Operating Temperature Range AD8A/B......................... C to +8 C Lead Temperature Range (Soldering sec)........................... C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8-Lead Plastic DIP Package: θ JA = 9 C/W 8-Lead SOIC Package: θ JA = C/W ORDERING GUIDE Temperature Package Package Model Range Description Options AD8AN C to +8 C 8-Lead Plastic Mini-DIP N-8 AD8BN* C to +8 C 8-Lead Plastic Mini-DIP N-8 AD8AR C to +8 C 8-Lead SOIC R-8 AD8BR C to +8 C 8-Lead SOIC R-8 *Not for new design, obsolete April. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. C
AD8 Typical Performance Characteristics V S = V, V NUMBER OF UNITS INPUT BIAS CURRENT pa V S = V V S = V, +V AND V....... OFFSET VOLTAGE mv TPC. Typical Distribution of Offset Voltage (8 Units)... COMMON-MODE VOLTAGE V TPC. Input Bias Current vs. Common-Mode Voltage; V S = + V, V and V S = ± V 8 k V S = V V S = V % IN BIN 8 INPUT BIAS CURRENT pa 8 OFFSET VOLTAGE DRIFT V/ C TPC. Typical Distribution of Offset Voltage Drift ( Units) 8. 8 8 COMMON-MODE VOLTAGE V TPC. Input Bias Current vs. Common-Mode Voltage; V S = ± V NUMBER OF UNITS INPUT BIAS CURRENT pa TPC. Typical Distribution of Input Bias Current ( Units) 8 9 INPUT BIAS CURRENT pa k k k. 8 TEMPERATURE C TPC. Input Bias Current vs. Temperature; V S = V, V CM = REV. C
AD8 M OPEN-LOOP GAIN V/V M k V S = V, V V S = V INPUT VOLTAGE V POS RAIL R L = k POS RAIL R L = k POS RAIL NEG RAIL NEG RAIL k k k k LOAD RESISTANCE TPC. Open-Loop Gain vs. Load Resistance R L = k NEG RAIL 8 OUTPUT VOLTAGE FROM VOLTAGE RAILS mv TPC. Input Error Voltage with Output Voltage within mv of Either Supply Rail for Various Resistive Loads; V S = ± V M k OPEN-LOOP GAIN V/V M k R L = k R L = k R L = V S = V V S = V, V V S = V V S = V, V V S = V INPUT VOLTAGE NOISE nv/ Hz V S = V, V k 8 TEMPERATURE C TPC 8. Open-Loop Gain vs. Temperature k k FREQUENCY Hz TPC. Input Voltage Noise vs. Frequency R L = k A CL = INPUT VOLTAGE V R L = k R L = k THD db 8 9 V S = V; V OUT = V p-p V S = V; V OUT = 9V p-p 8 R L = 8 OUTPUT VOLTAGE V TPC 9. Input Error Voltage vs. Output Voltage for Resistive Loads V S = V, V; V OUT =.V p-p k k k FREQUENCY Hz TPC. Total Harmonic Distortion vs. Frequency REV. C
AD8 9 OPEN-LOOP GAIN db 8 R L = k C L = pf GAIN PHASE 8 PHASE MARGIN IN DEGREES COMMON-MODE REJECTION db 8 V S = V, V V S = V k k k M M FREQUENCY Hz TPC. Open-Loop Gain and Phase Margin vs. Frequency k k k M M FREQUENCY Hz TPC. Common-Mode Rejection vs. Frequency k OUTPUT IMPEDANCE. A CL = + V S = V COMMON-MODE ERROR VOLTAGE mv C NEGATIVE RAIL + C + C C POSITIVE RAIL + C. k k k M M FREQUENCY Hz COMMON-MODE VOLTAGE FROM SUPPLY RAILS V TPC. Output Impedance vs. Frequency TPC. Absolute Common-Mode Error vs. Common-Mode Voltage from Supply Rails (V S V CM ) OUTPUT SWING FROM TO Volts 8 8 % %.%.% ERROR OUTPUT SATURATION VOLTAGE mv V S V OH V OL V S...... SETTLING TIME s TPC. Output Swing and Error vs. Settling Time... LOAD CURRENT ma TPC 8. Output Saturation Voltage vs. Load Current 8 REV. C
AD8 I SOURCE = ma OUTPUT SATURATION VOLTAGE mv I SINK = ma I SOURCE = ma I SINK = ma I SOURCE = A I SINK = A POWER SUPPLY REJECTION db 9 8 +PSRR PSRR 8 TEMPERATURE C TPC 9. Output Saturation Voltage vs. Temperature k k k M M FREQUENCY Hz TPC. Power Supply Rejection vs. Frequency 8 SHORT CIRCUIT CURRENT LIMIT ma V S = V, V V S = V, V V S = V V S = V OUT + + OUTPUT VOLTAGE V V S = V, V V S = V R = k 8 TEMPERATURE C k k M M FREQUENCY Hz TPC. Short Circuit Current Limit vs. Temperature TPC. Large Signal Frequency Response QUIESCENT CURRENT A 8 T = + C T = + C T = C 8 TOTAL SUPPLY VOLTAGE V TPC. Quiescent Current vs. Supply Voltage vs. Temperature 8 REV. C 9
AD8. F V IN AD8. F R L pf V OUT V S Figure. Unity Gain Follower Figure. Large Signal Response Unity Gain Follower; V S = ± V, R L = kω Figure. V, khz Sine Input; Unity Gain Follower; R L = Ω, V S = ± V Figure. Small Signal Response Unity Gain Follower; V S = ± V, R L = kω GND GND Figure. V S = V, V; Unity Gain Follower Response to V to V Step Figure 8. V S = V, V; Unity Gain Follower Response to V to V Step REV. C
AD8. F V IN AD8 R L pf V OUT GND Figure 9. Unity Gain Follower Figure. V S = V, V; Unity Gain Follower Response to mv Step Centered mv above Ground V IN k k V OUT. F AD8 R L pf GND Figure. Gain of Two Inverter Figure. V S = V, V; Gain-of-Two Inverter Response to mv Step, Centered mv below Ground GND Figure. V S = V, V; Gain-of-Two Inverter Response to. V Step Centered. V below Ground REV. C
AD8 APPLICATION NOTES Input Characteristics In the AD8, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input commonmode voltage extends from. V below V S to V less than. Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figures and 8) and increased common-mode voltage error as illustrated in TPC. The AD8 does not exhibit phase reversal for input voltages up to and including. Figure a shows the response of an AD8 voltage follower to a V to V ( ) square wave input. The input and output are superimposed. The output polarity tracks the input polarity up to no phase reversal. The reduced bandwidth above a V input causes the rounding of the output wave form. For input voltages greater than, a resistor in series with the AD8 s plus input will prevent phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure b. Since the input stage uses n-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than. V, the input current will reverse direction as internal device junctions become forward biased. This is illustrated in TPC. GND GND V IN R P (a) (b) +V AD8 V OUT Figure. (a) Response with R P = ; V IN from to Figure. (b) V IN = to + mv V OUT = to R P = 9.9 kω A current limiting resistor should be used in series with the input of the AD8 if there is a possibility of the input voltage exceeding the positive supply by more than mv, or if an input voltage will be applied to the AD8 when ± V S =. The amplifier will be damaged if left in that condition for more than seconds. A kω resistor allows the amplifier to withstand up to volts of continuous overvoltage, and increases the input voltage noise by a negligible amount. Input voltages less than V S are a completely different story. The amplifier can safely withstand input voltages V below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than V. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. The AD8 is designed for nv/ Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to TPC ). This noise performance, along with the AD8 s low input current and current noise means that the AD8 contributes negligible noise for applications with source resistances greater than kω and signal bandwidths greater than khz. This is illustrated in Figure. INPUT VOLTAGE NOISE V RMS k k k. k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. RESISTOR JOHNSON NOISE k M M M SOURCE IMPEDANCE khz AMPLIFIER-GENERATED NOISE G Hz Figure. Total Noise vs. Source Impedance Output Characteristics The AD8 s unique bipolar rail-to-rail output stage swings within mv of the minus supply and mv of the positive supply with no external resistive load. The AD8 s approximate output saturation resistance is Ω sourcing and Ω sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing ma, the saturation voltage to the positive supply rail will be mv, when sinking ma, the saturation voltage to the minus rail will be mv. The amplifier s open-loop gain characteristic will change as a function of resistive load, as shown in TPCs through. For load resistances over kω, the AD8 s input error voltage is virtually unchanged until the output voltage is driven to 8 mv of either supply. If the AD8 s output is driven hard against the output saturation voltage, it will recover within µs of the input returning to the amplifier s linear operating region. G REV. C
AD8 Direct capacitive load will interact with the amplifier s effective output impedance to form an additional pole in the amplifier s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figure shows the AD8 s pulse response as a unity gain follower driving pf. This amount of overshoot indicates approximately degrees of phase margin the system is stable, but is nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. Figure is a plot of capacitive load that will result in a degree phase margin versus noise gain for the AD8. Noise gain is the inverse of the feedback attenu ation factor provided by the feedback network in use. Figure 8 shows a possible configuration for extending capacitance load drive capability for a unity gain follower. With these component values, the circuit will drive, pf with a % overshoot. V IN. F AD8. F V S pf k V OUT Figure 8. Extending Unity Gain Follower Capacitive Load Capability Beyond pf OFFSET VOLTAGE ADJUSTMENT The AD8 s offset voltage is low, so external offset voltage nulling is not usually required. Figure 9 shows the recommended technique for AD8 s packaged in plastic DIPs. Adjusting offset voltage in this manner will change the offset voltage temperature drift by µv/ C for every millivolt of induced offset. The null pins are not functional for AD8s in the SO-8 R package. Figure. Small Signal Response of AD8 as Unity Gain Follower Driving pf Capacitive Load AD8 k NOISE GAIN + R F R I k k k k CAPACITIVE LOAD FOR PHASE MARGIN pf R I Figure. Capacitive Load Tolerance vs. Noise Gain R F V S Figure 9. Offset Null APPLICATIONS Single Supply Half-Wave and Full-Wave Rectifiers An AD8 configured as a unity gain follower and operated with a single supply can be used as a simple half-wave rectifier. The AD8 s inputs maintain picoamp level input currents even when driven well below the minus supply. The rectifier puts that behavior to good use, maintaining an input impedance of over Ω for input voltages from volt from the positive supply to volts below the negative supply. The full and half-wave rectifier shown in Figure operates as follows: when V IN is above ground, R is bootstrapped through the unity gain follower A and the loop of amplifier A. This forces the inputs of A to be equal, thus no current flows through R or R, and the circuit output tracks the input. When V IN is below ground, the output of A is forced to ground. The noninverting input of amplifier A sees the ground level output of A, therefore, A operates as a unity gain inverter. The output at node C is then a full-wave rectified version of the input. Node B is a buffered half-wave rectified version of the input. Input voltages up to ±8 volts can be rectified, depending on the voltage supply used. REV. C
AD8 A V IN R k. F A AD8 R k. F A AD8 C FULL-WAVE RECTIFIED OUTPUT B HALF-WAVE RECTIFIED OUTPUT Low Power Three-Pole Sallen Key Low-Pass Filter The AD8 s high input impedance makes it a good selection for active filters. High value resistors can be used to construct low frequency filters with capacitors much less than µf. The AD8 s picoamp level input currents contribute minimal dc errors. Figure shows an example, a Hz three-pole Sallen Key Filter. The high value used for R minimizes interaction with signal source resistance. Pole placement in this version of the filter minimizes the Q associated with the two-pole section of the filter. This eliminates any peaking of the noise contribution of resistors R, R, and R, thus minimizing the inherent output voltage noise of the filter. C. F A R k R k R k. F B C V IN C. F C. F AD8 V S. F V OUT Figure. Single Supply Half- and Full-Wave Rectifier. V Low Dropout, Low Power Reference The rail-to-rail performance of the AD8 can be used to provide low dropout performance for low power reference circuits powered with a single low voltage supply. Figure shows a. V reference using the AD8 and the AD8, a low power. V bandgap reference. R and R set up the required gain of.8 to develop the. V output. R and C form a low-pass RC filter to reduce the noise contribution of the AD8. V C. F U AD8.V mv R k U AD8 C. F FILM R 8k (k ) R k (k ).V OUTPUT.V OUTPUT C F/V REF COMMON FILTER GAIN RESPONSE db 8 9. k FREQUENCY Hz Figure. Hz Sallen Key Low-Pass Filter Figure. Single Supply. V Low Dropout Reference With a ma load, this reference maintains the. V output with a supply voltage down to. V. The amplitude of the recovery transient for a ma to ma step change in load current is under mv, and settles out in a few microseconds. Output voltage noise is less than µv rms in a khz noise bandwidth. REV. C
AD8 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Mini-DIP Package (N-8).9 (9.9) MAX 8.. (.) (.8) PIN.. (.9.). (.8) MIN. (.) BSC.8. (..8). (.8) NOM.. (.89.).8. (..) SEATING PLANE. (.) REF.. (.8.8). (.8) SOIC Package (R-8). (.99). (.8) PIN. (.). (.) SEATING PLANE 8.9 (.).89 (.8). (.) BSC. (.).8 (.9).9 (.8). (.). (.9).9 (.9). (.) CHAMF.9 (.8). (.) 8.98 (.8). (.9).9 (.9). (.).8 (.) REV. C
AD8 Revision History Location Page Data Sheet changed from REV. B to REV. C. Edits to FEATURES..................................................................................... Edits to PRODUCT DESCRIPTION........................................................................ Delete SPECIFICATIONS for AD8A- V.................................................................. Edits to ORDERING GUIDE.............................................................................. Edits to TYPICAL PERFORMANCE CHARACTERISTICS..................................................... 8 C8 /(C) PRINTED IN U.S.A.