Data Sheet Dual 3 MHz, ma Buck Regulators with wo 3 ma LDOs FEAURES Main input voltage range:.3 V to 5.5 V wo ma buck regulators and two 3 ma LDOs -lead, mm mm LFCSP or 8-lead SSOP package Regulator accuracy: ±.8% Factory programmable or external adjustable x 3 MHz buck operation with forced PWM and auto PWM/PSM modes BUCK/BUCK: output voltage range from.8 V to 3.8 V LDO/LDO: output voltage range from.8 V to 5. V LDO/LDO: input supply voltage from.7 V to 5.5 V LDO/LDO: high PSRR and low output noise APPLICAIONS Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices GENERAL DESCRIPION he combines two high performance buck regulators and two low dropout (LDO) regulators. It is available in either a -lead mm mm LFCSP or a 8-lead SSOP package. regulators operate in PWM mode when the load is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. able. Family Models Model Channels Maximum Current ADP53 Buck, LDO 8 ma, 3 ma ADP5 Buck, LDO. A, 3 ma Buck, LDOs. A, 3 ma ADP537 Buck, LDOs 8 ma, 3 ma ADP533 Buck, LDOs with 8 ma, EN pins 3 ma Package LFCSP (CP--) LFCSP (CP--) LFCSP (CP--), SSOP (RE-8-) LFCSP (CP--) WLCSP (CB-6-8) he two bucks operate out of phase to reduce the input capacitor requirement. he low quiescent current, low dropout voltage, and wide input voltage range of the LDOs extend the battery life of portable devices. he LDOs maintain power supply rejection greater than 6 db for frequencies as high as khz while operating with a low headroom voltage. he high switching frequency of the buck regulators enables tiny Regulators in the are activated through dedicated multilayer external components and minimizes the board space. enable pins. he default output voltages can be externally set in When the pin is set to high, the buck regulators operate in the adjustable version, or factory programmable to a wide range forced PWM mode. When the pin is set to low, the buck of preset values in the fixed voltage version. YPICAL APPLICAION CIRCUI.3V O 5.5V C AVIN.µF C.7µF ON OFF C.7µF AVIN VIN EN VIN EN HOUSEKEEPING BUCK EN BUCK EN SW FB PGND SW FB PGND L µh R R PWM L µh R3 R V OU A ma C5 µf PSM/PWM V OU A ma C6 µf.7v O 5.5V C3 µf ON OFF C µf EN3 VIN3 EN VIN EN3 EN LDO (ANALOG) LDO (DIGIAL) AGND 3 FB3 FB R5 R6 R7 R8 C7 µf C8 µf V OU3 A 3mA V OU A 3mA 973- Figure. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. rademarks and registered trademarks are the property of their respective owners. One echnology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. el: 78.39.7 3 Analog Devices, Inc. All rights reserved. echnical Support www.analog.com
ABLE OF CONENS Features... Applications... General Description... ypical Application Circuit... Revision History... 3 Specifications... General Specifications... BUCK and BUCK Specifications... 5 LDO and LDO Specifications... 5 Input and Output Capacitor, Recommended Specifications.. 6 Absolute Maximum Ratings... 7 hermal Resistance... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 ypical Performance Characteristics... 9 Data Sheet heory of Operation... 6 Power Management Unit... 6 BUCK and BUCK... 8 LDO and LDO... 9 Applications Information... Buck External Component Selection... LDO External Component Selection... Power Dissipation and hermal Considerations... 3 Buck Regulator Power Dissipation... 3 Junction emperature... PCB Layout Guidelines... 5 ypical Application Schematics... 6 Bill of Materials... 6 Outline Dimensions... 7 Ordering Guide... 8 Rev. E Page of 8
Data Sheet REVISION HISORY 5/3 Rev. D to Rev. E Added able ; Renumbered Sequentially... Changes to Figure... Changes to NC Pin Description... 8 Changes to Figure 9... 9 Changes to Figure 5... Changes to Figure 53 and Figure 5... 6 /3 Rev. C to Rev. D Changes to Ordering Guide... 8 / Rev. B to Rev. C Changes to Ordering Guide... 8 7/ Rev. A to Rev. B Added 8-Lead SSOP Package hroughout... Changes to Output Voltage Accuracy Parameter, Added SSOP SW On Resistance Specifications, Changes to Voltage Feedback Minimum and Maximum Values, and Changes to Active Pull- Down Conditions; able... 5 Changes to Output Voltage Accuracy Parameter and Voltage Feedback Minimum and Maximum Values in able 3; Changes to able... 6 Added hermal Resistance Values for SSOP Package, able 6.. 7 Added Figure 3 and SSOP Pins to able 7... 8 Changes to Figure 7, Figure 8, and Figure 9... 9 Changes to Figure... Changes to Figure 8 Caption... Changes to Figure 3 and Figure 3... 3 Changes to Figure 35 and Figure 39 Caption... Changes to Undervoltage Lockout Section... 7 Changes to able 8... Changes to able 9 and able... Changes to Equation 9 and Following Paragraph... 3 Added UG-39 to PCB Layout Guidelines Section... 5 Changes to able... 6 Updated Outline Dimensions... 7 Changes to Ordering Guide... 8 / Rev. to Rev. A Change to Features Section... Changes to General Description Section... Changes to Figure... Change to able, Low UVLO Input Voltage Falling Parameter, Symbol Column... 3 Change to able, Output Voltage Accuracy Parameter, est Conditions/Comment Column... Change to able, Line Regulation Parameter, Symbols Column... Change to able, Load Regulation Parameter, Symbols Column... Changes to able, Reversed the RPFE and RNFE Symbols for the SW On Resistance Parameter and Changes to yp and Max Columns... Changes to able 3, Output Accuracy Parameter, est Conditions/Comments Column... Changes to able 3, Line Regulation Parameter, Symbols Column and est Conditions/Comments Column... Change to able 3, Changes to Dropout Voltage Parameter and Added Specification to Dropout Voltage Parameter... 5 Change to able 3, Endnote 3... 5 Change to able, BUCK, BUCK Output Capacitor Parameter, Min Column Value... 5 Change to able, Endnote... 5 Changes to Absolute Maximum Ratings, able 5... 6 Changes to able 7, Pin Function Descriptions... 7 Changes to PC Section... 8 Moved Power Dissipation and hermal Considerations Section... Change to Equation 5 Where Statement... Change to Equation 6... Change to Undervoltage Lockout Section... 6 Changes to Figure 6... 6 Change to Figure 7... 7 Changes to LDO/LDO Section... 8 Changes to Output Capacitor Section and able 8... 9 Change to VRIPPLE Equation, able 9, and Figure 5... Changes to Input and Output Capacitor Properties Section... Changes to Equation 3... Changes to Junction emperature Section... 3 Changes to LDO Regulator Power Dissipation Section... 3 Changes to Figure 5 and Figure 53... 5 Moved Bill of Materials Section... 5 Changes to Ordering Guide... 6 6/ Revision : Initial Version Rev. E Page 3 of 8
Data Sheet SPECIFICAIONS GENERAL SPECIFICAIONS VAVIN = VIN = VIN =.3 V to 5.5 V; VIN3 = VIN =.7 V to 5.5 V; J = C to +5 C for minimum/maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. able. Parameter Symbol est Conditions/Comments Min yp Max Unit INPU VOLAGE RANGE VAVIN, VIN, VIN.3 5.5 V HERMAL SHUDOWN hreshold SSD J rising 5 C Hysteresis SSD-HYS C SAR-UP IME BUCK, LDO, LDO tsar 5 µs BUCK tsar 3 µs EN, EN, EN3, EN, INPUS Input Logic High VIH. V Input Logic Low VIL. V Input Leakage Current VI-LEAKAGE.5 µa INPU CURREN All Channels Enabled ISBY-NOSW No load, no buck switching 8 75 µa All Channels Disabled ISHUDOWN J = C to +85 C.3 µa VIN UNDERVOLAGE LOCKOU High UVLO Input Voltage Rising UVLOVINRISE 3.9 V High UVLO Input Voltage Falling UVLOVINFALL 3. V Low UVLO Input Voltage Rising UVLOVINRISE.75 V Low UVLO Input Voltage Falling UVLOVINFALL.95 V Start-up time is defined as the time from EN = EN = EN3 = EN from V to VAVIN to,, 3, and reaching 9% of their nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the ypical Performance Characteristics section for more information. Rev. E Page of 8
Data Sheet BUCK AND BUCK SPECIFICAIONS VAVIN = VIN = VIN =.3 V to 5.5 V; J = C to +5 C for minimum/maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. able 3. Parameter Symbol est Conditions/Comments Min yp Max Unit OUPU CHARACERISICS Output Voltage Accuracy Δ/, PWM mode; ILOAD = ILOAD = ma.8 +.8 % Line Regulation Load Regulation Δ/ (Δ/)/ΔVIN, (Δ/)/ΔVIN (Δ/)/ΔIOU, (Δ/)/ΔIOU PWM mode.5 %/V ILOAD = ma to ma, PWM mode. %/A VOLAGE FEEDBACK VFB, VFB Models with adjustable outputs.9.5.59 V OPERAING SUPPLY CURREN = ground BUCK Only IIN ILOAD = ma, device not switching, all μa other channels disabled BUCK Only IIN ILOAD = ma, device not switching, all 55 μa other channels disabled BUCK and BUCK IIN ILOAD = ILOAD = ma, device not switching, 67 μa LDO channels disabled PSM CURREN HRESHOLD IPSM PSM to PWM operation ma SW CHARACERISICS SW On Resistance RNFE VIN = VIN = 3.6 V; LFCSP package 55 mω RPFE VIN = VIN = 3.6 V; LFCSP package 5 3 mω RNFE VIN = VIN = 5.5 V; LFCSP package 37 mω RPFE VIN = VIN = 5.5 V; LFCSP package 6 3 mω RNFE VIN = VIN = 3.6 V; SSOP package 56 37 mω RPFE VIN = VIN = 3.6 V; SSOP package 9 7 mω RNFE VIN = VIN = 5.5 V; SSOP package 37 mω RPFE VIN = VIN = 5.5 V; SSOP package 5 mω Current Limit ILIMI, ILIMI pfe switch peak current limit 6 95 3 ma ACIVE PULL-DOWN RPDWN-B VIN= VIN = 3.6 V; Channel disabled 75 Ω OSCILLAOR FREQUENCY fsw.5 3. 3.5 MHz All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO AND LDO SPECIFICAIONS VIN3 = (3 +.5 V) or.7 V (whichever is greater) to 5.5 V, VIN = ( +.5 V) or.7 V (whichever is greater) to 5.5 V; CIN = COU = µf; J = C to +5 C for minimum/maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. able. Parameter Symbol est Conditions/Comments Min yp Max Unit INPU VOLAGE RANGE VIN3, VIN.7 5.5 V OPERAING SUPPLY CURREN Bias Current per LDO IVIN3BIAS/IVINBIAS IOU3 = IOU = µa 3 µa IOU3 = IOU = ma 6 µa IOU3 = IOU = 3 ma 65 5 µa otal System Input Current IIN Includes all current into AVIN, VIN, VIN, VIN3, and VIN LDO or LDO Only IOU3 = IOU = µa, all other channels disabled 53 µa LDO and LDO Only IOU3 = IOU = µa, buck channels disabled 7 µa Rev. E Page 5 of 8
Data Sheet Parameter Symbol est Conditions/Comments Min yp Max Unit OUPU CHARACERISICS Output Voltage Accuracy Line Regulation Load Regulation 3 Δ3/3, Δ/ (Δ3/3)/ΔVIN3, (Δ/)/ΔVIN (Δ3/3)/ΔIOU3, (Δ/)/ΔIOU µa < IOU3 < 3 ma, µa < IOU < 3 ma.8 +.8 % IOU3 = IOU = ma.3 +.3 %/V IOU3 = IOU = ma to 3 ma..3 %/ma VOLAGE FEEDBACK VFB3, VFB.9.5.59 V DROPOU VOLAGE VDROPOU 3 = = 5. V, IOU3 = IOU = 3 ma 5 mv 3 = = 3.3 V, IOU3 = IOU = 3 ma 75 mv 3 = =.5 V, IOU3 = IOU = 3 ma mv 3 = =.8 V, IOU3 = IOU = 3 ma 8 mv CURREN-LIMI HRESHOLD 5 ILIMI3, ILIMI 335 6 ma ACIVE PULL-DOWN RPDWN-L Channel disabled 6 Ω OUPU NOISE Regulator LDO NOISELDO Hz to khz, VIN3 = 5 V, 3 =.8 V µv rms Regulator LDO NOISELDO Hz to khz, VIN = 5 V, =. V 6 µv rms POWER SUPPLY REJECION PSRR RAIO Regulator LDO khz, VIN3 = 3.3 V, 3 =.8 V, IOU3 = ma 6 db khz, VIN3 = 3.3 V, 3 =.8 V, IOU3 = ma 6 db MHz, VIN3 = 3.3 V, 3 =.8 V, IOU3 = ma 63 db Regulator LDO khz, VIN =.8 V, =. V, IOU = ma 5 db khz, VIN =.8 V, =. V, IOU = ma 57 db MHz, VIN =.8 V, =. V, IOU = ma 6 db All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). his is the input current into VIN3/VIN, which is not delivered to the output load. 3 Based on an endpoint calculation using ma and 3 ma loads. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. his applies only to output voltages above.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 9% of the specified typical value. For example, the current limit for a 3. V output voltage is defined as the current that causes the output voltage to drop to 9% of 3. V, or.7 V. INPU AND OUPU CAPACIOR, RECOMMENDED SPECIFICAIONS A = C to +5 C, unless otherwise specified. able 5. Parameter Symbol Min yp Max Unit NOMINAL INPU AND OUPU CAPACIOR RAINGS BUCK, BUCK Input Capacitor Ratings CMIN, CMIN.7 µf BUCK, BUCK Output Capacitor Ratings CMIN, CMIN µf LDO, LDO Input and Output Capacitor Ratings CMIN3, CMIN. µf CAPACIOR ESR RESR. Ω he minimum input and output capacitance should be greater than. µf over the full range of operating conditions. he full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics. Rev. E Page 6 of 8
Data Sheet ABSOLUE MAXIMUM RAINGS able 6. Parameter Rating AVIN to AGND.3 V to +6 V VIN, VIN to AVIN.3 V to +.3 V PGND, PGND to AGND.3 V to +.3 V VIN3, VIN,,, FB, FB,.3 V to (AVIN +.3 V) FB3, FB, EN, EN, EN3, EN, to AGND 3 to AGND.3 V to (VIN3 +.3 V) to AGND.3 V to (VIN +.3 V) SW to PGND.3 V to (VIN +.3 V) SW to PGND.3 V to (VIN +.3 V) Storage emperature Range 65 C to +5 C Operating Junction emperature C to +5 C Range Soldering Conditions JEDEC J-SD- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For detailed information on power dissipation, see the Power Dissipation and hermal Considerations section. HERMAL RESISANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. able 7. hermal Resistance Package ype θja θjc Unit -Lead,.5 mm pitch LFCSP 35 3 C/W 8-Lead SSOP 36 5 C/W ESD CAUION Rev. E Page 7 of 8
7 8 9 3 9 Data Sheet PIN CONFIGURAION AND FUNCION DESCRIPIONS FB EN VIN SW PGND NC 3 5 6 VIN EN3 VIN3 3 FB3 PIN INDICAOR OP VIEW (Not to Scale) EN FB FB EN 8 AGND 7 AVIN 6 VIN 5 SW PGND 3 NOES. NC = NO INERNALLY CONNECED.. I IS RECOMMENDED HA HE EXPOSED PAD BE SOLDERED O HE GROUND PLANE. Figure. LFCSP Pin Configuration View from the op of the Die 973-3 EN3 VIN 3 NC FB 5 EN 6 VIN 7 SW 8 PGND 9 NC NC EN FB 3 OP VIEW (Not to Scale) 8 VIN3 7 3 6 FB3 5 NC AGND 3 AVIN VIN SW PGND 9 8 NC 7 EN 6 FB 5 NOES. NC = NO INERNALLY CONNECED.. I IS RECOMMENDED HA HE EXPOSED PAD BE SOLDERED O HE GROUND PLANE. Figure 3. SSOP Pin Configuration View from the op of the Die 973- able 8. Pin Function Descriptions Pin No. LFCSP SSOP Mnemonic Description 5 FB LDO Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the LDO resistor divider. For device models with a factory programmed output voltage, connect FB to the top of the capacitor on. 6 EN LDO Enable Pin. High level turns on this regulator, and low level turns it off. 3 7 VIN BUCK Input Supply (.3 V to 5.5 V). Connect VIN to VIN and AVIN. 8 SW BUCK Switching Node. 5 9 PGND Dedicated Power Ground for BUCK. 6,,, NC No Connect. Leave this pin unconnected or connect to ground. 8, 5 7 EN BUCK Enable Pin. High level turns on this regulator, and low level turns it off. 8 3 FB BUCK Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 9 BUCK Output Voltage Sensing Input. Connect to the top of the capacitor on. 5 BUCK Output Voltage Sensing Input. Connect to the top of the capacitor on. 6 FB BUCK Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 7 EN BUCK Enable Pin. High level turns on this regulator, and low level turns it off. 3 9 BUCK/BUCK Operating Mode. = high: forced PWM operation. = low: auto PWM/PSM operation. PGND Dedicated Power Ground for BUCK. 5 SW BUCK Switching Node. 6 VIN BUCK Input Supply (.3 V to 5.5 V). Connect VIN to VIN and AVIN. 7 3 AVIN Analog Input Supply (.3 V to 5.5 V). Connect AVIN to VIN and VIN. 8 AGND Analog Ground. 9 6 FB3 LDO Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the LDO resistor divider. For device models with a factory programmed output voltage, connect FB3 to the top of the capacitor on 3. 7 3 LDO Output Voltage. 8 VIN3 LDO Input Supply (.7 V to 5.5 V). EN3 LDO Enable Pin. High level turns on this regulator, and low level turns it off. 3 VIN LDO Input Supply (.7 V to 5.5 V). 3 LDO Output Voltage. EPAD EPAD EP Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane. Rev. E Page 8 of 8
Data Sheet YPICAL PERFORMANCE CHARACERISICS VIN = VIN = VIN3= VIN = 3.6 V, A = 5 C, unless otherwise noted. QUIESCEN CURREN (µa) 8 6 V OU (V) 3.3 3.35 3.3 3.35 3.3 3.95 3.9 3.85 3.8 3.75 A = C A = +5 C A = +85 C.3.8 3.3 3.8.3.8 5.3 INPU VOLAGE (V) Figure. System Quiescent Current vs. Input Voltage, = 3.3 V, =.8 V, 3 =. V, = 3.3 V, All Channels Unloaded 973-39 3.7...6.8.. I OU (A) Figure 7. BUCK Load Regulation Across emperature, VIN =. V, = 3.3 V, PWM Mode 973-.8 SW IOU V OU (V).8.88.86.8 A = C A = +5 C EN.8 3.8 A = +85 C CH.V B W CH 5.mA Ω B W M.µs A CH3.V CH3 5.V B W CH 5.V B W.% Figure 5. BUCK Startup, =.8 V, IOU = 5 ma 973-9.798...6.8.. I OU (A) Figure 8. BUCK Load Regulation Across emperature, VIN = 3.6 V, =.8 V, PWM Mode 973-.88 SW.87 IOU.86 A = +5 C EN V OU (V).85.8 A = +85 C A = C 3.83 CH.V B W CH 5.mA Ω B W M.µs A CH3.V CH3 5.V B W CH 5.V B W.% Figure 6. BUCK Startup, = 3.3 V, IOU = ma 973-8.8...6.8.. I OU (A) Figure 9. BUCK Load Regulation Across Input Voltage, VIN = 3.6 V, =.8 V, PWM Mode 973-3 Rev. E Page 9 of 8
Data Sheet 9 V IN = 3.9V 9 V IN = 3.6V EFFICIENCY (%) 8 7 6 5 3 V IN = 5.5V V IN =.V EFFICIENCY (%) 8 7 6 5 3 V IN =.3V V IN =.V V IN = 5.5V... I LOAD (A) Figure. BUCK Efficiency vs. Load Current, Across Input Voltage, = 3.3 V, Auto Mode 9 973-... I OU (A) Figure 3. BUCK Efficiency vs. Load Current, Across Input Voltage, =.8 V, PWM Mode 9 973-6 EFFICIENCY (%) 8 7 6 5 V IN = 3.9V V IN = 5.5V EFFICIENCY(%) 8 7 6 5 V IN = 3.6V V IN =.V V IN = 5.5V V IN =.3V 3 3 V IN =.V... I OU (A) Figure. BUCK Efficiency vs. Load Current, Across Input Voltage, = 3.3 V, PWM Mode 973-8... I OU (A) Figure. BUCK Efficiency vs. Load Current, Across Input Voltage, =.8 V, Auto Mode 973-5 EFFICIENCY (%) 9 8 7 6 5 V IN = 3.6V V IN =.V V IN = 5.5V V IN =.3V EFFICIENCY (%) 9 8 7 6 5 V IN = 3.6V V IN =.3V V IN = 5.5V V IN =.V 3 3... I OU (A) Figure. BUCK Efficiency vs. Load Current, Across Input Voltage, =.8 V, Auto Mode 973-... I OU (A) Figure 5. BUCK Efficiency vs. Load Current, Across Input Voltage, =.8 V, PWM Mode 973-7 Rev. E Page of 8
Data Sheet EFFICIENCY (%) 9 8 7 6 5 3 +5 C +85 C C... I OU (A) Figure 6. BUCK Efficiency vs. Load Current, Across emperature, VIN = 3.9 V, = 3.3 V, Auto Mode 973-8 SCOPE FREQUENCY (MHz) 3.3 3. 3. 3..9.8.7.6 +5 C +85 C.5...6.8.. I OU (A) C Figure 9. BUCK Switching Frequency vs. Output Current, Across emperature, =.8 V, PWM Mode 973-3 9 +5 C +85 C EFFICIENCY (%) 8 7 6 5 3 C I SW SW... I OU (A) Figure 7. BUCK Efficiency vs. Load Current, Across emperature, =.8 V, Auto Mode 973-3 CH 5.mV CH 5mA Ω M.µs A CH ma CH.V 8.% Figure. ypical Waveforms, = 3.3 V, IOU = 3 ma, Auto Mode 973-5 EFFICIENCY (%) 9 8 7 6 5 +5 C C +85 C I SW 3 SW... I OU (A) Figure 8. BUCK Efficiency vs. Load Current, Across emperature, =.8 V, Auto Mode 973-9 CH 5.mV B W CH 5mA Ω M.µs A CH ma CH.V B W 8.% Figure. ypical Waveforms, =.8 V, IOU = 3 ma, Auto Mode 973-5 Rev. E Page of 8
Data Sheet VIN I SW SW SW 3 CH 5mV B W CH 5mA Ω M ns A CH ma CH.V B W 8.% Figure. ypical Waveforms, = 3.3 V, IOU = 3 ma, PWM Mode 973-53 CH 5.mV B W CH3.V B W CH.V B W M.ms A CH3.8V 3.% Figure 5. BUCK Response to Line ransient, VIN =.5 V to 5. V, =.8 V, PWM Mode 973- SW I SW SW I OU CH 5mV B W CH 5mA Ω M ns A CH ma CH.V B W 8.% Figure 3. ypical Waveforms, =.8 V, IOU = 3 ma, PWM Mode 973-5 CH 5.mV B W CH 5.mA Ω B W CH 5.V M.µs A CH 356mA 6.µs Figure 6. BUCK Response to Load ransient, IOU from ma to 5 ma, = 3.3 V, Auto Mode B W 973- SW VIN SW I OU 3 CH 5.mV B W CH3.V B W CH.V B W M.ms A CH3.8V 3.% Figure. BUCK Response to Line ransient, Input Voltage from.5 V to 5. V, = 3.3 V, PWM Mode 973- CH 5.mV B W CH 5.mA Ω B W M.µs A CH 379mA CH 5.V B W.% Figure 7. BUCK Response to Load ransient, IOU from ma to 5 ma, =.8 V, Auto Mode 973-3 Rev. E Page of 8
Data Sheet SW EN I OU 3 I IN CH 5.mV B W CH ma Ω B W M.µs A CH 8mA CH 5.V B W.% Figure 8. BUCK Response to Load ransient, IOU from ma to 8 ma, = 3.3 V, Auto Mode 973-5 CH ma CH3 V CH 5V Mµs.5GS/s A CH.V 59.µs Figure 3. LDO Startup, 3 =.8 V 973-5 SW 3.36 3.355 3.35 V IN = 5.5V 3.35 3.3 V OU (V) 3.335 3.33 V IN =.V I OU 3.35 3.3 V IN = 3.8V 3.35 CH mv B W CH ma Ω B W M.µs A CH CH 5.V B W 9.% 88.mA Figure 9. BUCK Response to Load ransient, IOU from ma to 8 ma, =.8 V, Auto Mode 973-6 3.3 5 5 5 3 I OU (ma) Figure 3. LDO Load Regulation Across Input Voltage, 3 = 3.3 V 973-6 35 3 SW RDS ON (mω) 3 5 5 +5 C +5 C SW C 5 CH 5.V B W CH 5.V B W M ns A CH.9V CH3 5.V B W CH 5.V B W 5.% Figure 3. and SW Waveforms for BUCK and BUCK in PWM Mode Showing Out-of-Phase Operation 973-6.3.8 3.3 3.8.3.8 5.3 INPU VOLAGE (V) Figure 33. LFCSP NMOS RDSON vs. Input Voltage Across emperature 973-37 Rev. E Page 3 of 8
Data Sheet 5 5 5 RDS ON (mω) 5 C +5 C +5 C GROUND CURREN (µa) 35 3 5 5 5 5.3.8 3.3 3.8.3.8 5.3 INPU VOLAGE (V) Figure 3. LFCSP PMOS RDSON vs. Input Voltage Across emperature 973-38.5..5..5 LOAD CURREN (A) Figure 37. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, 3 =.8 V 973-36.8.8.8 A = C I OU.799 V OU (V).798.797.796 A = +5 C.795.79.793 A = +85 C.79 5 5 5 3 I OU (ma) Figure 35. LDO Load Regulation Across emperature, VIN3 = 3.6 V, 3 =.8 V 973-7 CH mv B W CH ma Ω B W M.µs A CH 5.mA 9.% Figure 38. LDO Response to Load ransient, IOU3 from ma to 8 ma, 3 =.8 V 973-7 3. I OU = ma I OU = µa.5. I OU = ma I OU = ma I OU = 5mA I OU = 3mA VIN V OU (V).5..5 3..6.8 3. 3. 3. 3.6 3.8....6.8 5. 5. 5. V IN (V) Figure 36. LDO Line Regulation Across Output Load, 3 =.8 V 973-3 CH.mV CH3.V M µs A CH3.8V 8.% Figure 39. LDO Response to Line ransient, Input Voltage from.5 V to 5 V, 3 =.8 V 973- Rev. E Page of 8
Data Sheet 6 55 V IN = 5V V IN = 3.3V RMS NOISE (µv) 5 5 35 3 5... I LOAD (ma) Figure. LDO Output Noise vs. Load Current, Across Input Voltage, 3 =.8 V 973-55 PSRR (db) 6 8 µa ma ma 5mA ma 5mA k k k M M FREQUENCY (Hz) Figure 3. LDO PSRR Across Output Load, VIN3 = 3.3 V, 3 = 3. V 973-58 RMS NOISE (µv) 65 6 55 5 5 V IN = 5V V IN = 3.3V PSRR (db) 6 8 µa ma ma 5mA ma 5mA 35 3 5... I LOAD (ma) Figure. LDO Output Noise vs. Load Current, Across Input Voltage, 3 = 3. V 973-56 k k k M M FREQUENCY (Hz) Figure. LDO PSRR Across Output Load, VIN3 = 5. V, 3 =.8 V 973-59 3 µa ma ma 5mA ma 5mA 3 µa ma ma 5mA ma 5mA PSRR (db) 5 6 PSRR (db) 5 6 7 7 8 8 9 9 k k k M M FREQUENCY (Hz) Figure. LDO PSRR Across Output Load, VIN3 = 3.3 V, 3 =.8 V 973-57 k k k M M FREQUENCY (Hz) Figure 5. LDO PSRR Across Output Load, VIN3 = 5. V, 3 = 3. V 973-6 Rev. E Page 5 of 8
Data Sheet HEORY OF OPERAION FB FB AVIN GM ERROR AMP ENBK 75Ω 75Ω ENBK GM ERROR AMP VIN PWM COMP SOF SAR SOF SAR PWM COMP VIN I LIMI LOW CURREN PWM/ PSM CONROL BUCK PSM COMP PSM COMP PWM/ PSM CONROL BUCK I LIMI LOW CURREN SW SW PGND EN EN EN3 EN ENABLE AND CONROL DRIVER AND ANISHOO HROUGH ENBK ENBK ENLDO ENLDO LDO UNDERVOLAGE LOCKOU OSCILLAOR SYSEM UNDERVOLAGE LOCKOU HERMAL SHUDOWN R OP DRIVER AND ANISHOO HROUGH SEL B Y A LDO UNDERVOLAGE LOCKOU ENLDO 6Ω R3 PGND AVIN LDO CONROL AVIN LDO CONROL R 6Ω ENLDO R VIN3 AGND FB3 3 VIN FB 973-5 POWER MANAGEMEN UNI he is a micropower management unit (micro PMU) combining two step-down (buck) dc-to-dc converters and two low dropout linear regulators (LDOs). he high switching frequency and tiny -lead LFCSP package allow for a small power management solution. o combine these high performance regulators into the micro PMU, there is a system controller allowing them to operate together. he buck regulators can operate in forced PWM mode if the pin is at a logic high level. In forced PWM mode, the buck switching frequency is always constant and does not change with the load current. If the pin is at logic low level, the switching regulators operate in auto PWM/PSM mode. In this mode, the regulators operate at fixed PWM frequency when the load current is above the PSM current threshold. When the load current falls below the PSM current threshold, the regulator in question enters PSM, where the switching occurs in bursts. he burst repetition rate is a function of the current load and the output capacitor value. Figure 6. Functional Block Diagram Rev. E Page 6 of 8 his operating mode reduces the switching and quiescent current losses. he auto PWM/PSM mode transition is controlled independently for each buck regulator. he two bucks operate synchronized to each other. he has individual enable pins (EN to EN) controlling the activation of each regulator. he regulators are activated by a logic level high applied to the respective EN pin. EN controls BUCK, EN controls BUCK, EN3 controls LDO, and EN controls LDO. Regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default values (see the Ordering Guide section). When a regulator is turned on, the output voltage ramp rate is controlled through a soft start circuit to avoid a large inrush current due to the charging of the output capacitors.
Data Sheet hermal Protection In the event that the junction temperature rises above 5 C, the thermal shutdown circuit turns off all the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A C hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temperature drops below 3 C. When coming out of thermal shutdown, all regulators restart with soft start control. Undervoltage Lockout o protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated into the system. If the input voltage on AVIN drops below a typical.5 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more. AVIN Alternatively, the user can select device models with a UVLO set at a higher level, suitable for 5 V supply applications. For these models, the device reaches the turn-off threshold when the input supply drops to 3.65 V typical. In case of a thermal or UVLO event, the active pull-downs (if factory enabled) are enabled to discharge the output capacitors quickly. he pull-down resistors remain engaged until the thermal fault event is no longer present or the input supply voltage falls below the VPOR voltage level. he typical value of VPOR is approximately V. Enable/Shutdown he has an individual control pin for each regulator. A logic level high applied to the ENx pin activates a regulator, whereas a logic level low turns off a regulator. Figure 7 shows the regulator activation timings for the when all enable pins are connected to AVIN. Also shown is the active pull-down activation. V UVLO V POR 3 3µs (MIN) 5µs (MIN) 3µs (MIN) 5µs (MIN) BUCK, LDO, LDO PULL-DOWNS BUCK PULL-DOWN Figure 7. Regulator Sequencing on the (EN = EN = EN3 = EN = VAVIN) 973-6 Rev. E Page 7 of 8
Data Sheet BUCK AND BUCK he buck uses a fixed frequency and high speed current mode architecture. he buck operates with an input voltage of.3 V to 5.5 V. he buck output voltage is set through external resistor dividers, shown in Figure 8 for BUCK. he output voltage can optionally be factory programmed to default values as indicated in the Ordering Guide section. In this event, R and R are not needed, and FB can be left unconnected. In all cases, must be connected to the output capacitor. FB is.5 V. VIN BUCK R V OU = V FB + R L µh SW FB AGND R R C5 µf Figure 8. BUCK External Output Voltage Setting Control Scheme he bucks operate with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency but shift to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. PWM Mode In PWM mode, the bucks operate at a fixed frequency of 3 MHz set by an internal oscillator. At the start of each oscillator cycle, the pfe switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfe switch and turns on the nfe synchronous rectifier. his sends a negative voltage across the inductor, causing the inductor current to decrease. he synchronous rectifier stays on for the rest of the cycle. he buck regulates the output voltage by adjusting the peak inductor current threshold. Power Save Mode (PSM) he bucks smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When either of the bucks enters PSM, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. he output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device Rev. E Page 8 of 8 973-8 drives the inductor to make the output voltage rise again to the upper threshold. his process is repeated while the load current is below the PSM current threshold. he has a dedicated pin controlling the PSM and PWM operation. A high logic level applied to the pin forces both bucks to operate in PWM mode. A logic level low sets the bucks to operate in auto PSM/PWM. PSM Current hreshold he PSM current threshold is set to ma. he bucks employ a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. his scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from the PSM. he PSM current threshold is optimized for excellent efficiency over all load currents. Oscillator/Phasing of Inductor Switching he ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Additionally, the ensures that when both bucks are in PWM mode, they operate out of phase, whereby the Buck pfe starts conducting exactly half a clock period after the BUCK pfe starts conducting. Short-Circuit Protection he bucks include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. he reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. Soft Start he bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. his prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Current Limit Each buck has protection circuitry to limit the amount of positive current flowing through the pfe switch and the amount of negative current flowing through the synchronous rectifier. he positive current limit on the power switch limits the amount of current that can flow from the input to the output. he negative current limit prevents the inductor current from reversing direction and flowing out of the load. % Duty Operation With a drop in input voltage, or with an increase in load current, the buck may reach a limit where, even with the pfe switch on % of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the pfe switch stays on % of the time. When
Data Sheet the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. Active Pull-Downs All regulators have optional, factory programmable, active pulldown resistors discharging the respective output capacitors when the regulators are disabled. he pull-down resistors are connected between x and AGND. Active pull-downs are disabled when the regulators are turned on. he typical value of the pull-down resistor is 6 Ω for the LDOs and 75 Ω for the bucks. Figure 7 shows the activation timings for the active pull-downs during regulator activation and deactivation. LDO AND LDO he contains two LDOs with low quiescent current and low dropout linear regulators, and provides up to 3 ma of output current. Drawing a low μa quiescent current (typical) at no load makes the LDO ideal for battery-operated portable equipment. Each LDO operates with an input voltage of.7 V to 5.5 V. he wide operating range makes these LDOs suitable for cascading configurations where the LDO supply voltage is provided from one of the buck regulators. Each LDO output voltage is set through external resistor dividers as shown in Figure 9 for LDO. he output voltage can optionally be factory programmed to default values as indicated in the Ordering Guide section. In this event, Ra and Rb are not needed, and FB3 must be connected to the top of the capacitor on 3. VIN3 LDO Ra V OU3 = V FB3 + Rb 3 FB3 Ra Rb 3 C7 µf Figure 9. LDO External Output Voltage Setting he LDOs also provide high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with only a small µf ceramic input and output capacitor. LDO is optimized to supply analog circuits because it offers better noise performance compared to LDO. LDO should be used in applications where noise performance is critical. 973-9 Rev. E Page 9 of 8
Data Sheet APPLICAIONS INFORMAION BUCK EXERNAL COMPONEN SELECION rade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure. Feedback Resistors For the adjustable model, referring to Figure 5 the total combined resistance for R and R is not to exceed kω. Inductor he high switching frequency of the bucks allows for the selection of small chip inductors. For best performance, use inductor values between.7 μh and 3 μh. Suggested inductors are shown in able 9. he peak-to-peak inductor current ripple is calculated using the following equation: I RIPPLE ( VIN = V f IN SW V L OU where: fsw is the switching frequency. L is the inductor value. he minimum dc current rating of the inductor must be greater than the inductor peak current. he inductor peak current is calculated using the following equation: I RIPPLE I PEAK = I LOAD( MAX) + Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI. Output Capacitor Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. ) Rev. E Page of 8 Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. he worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COU ( EMPCO) ( OL) where: CEFF is the effective capacitance at the operating voltage. EMPCO is the worst-case capacitor temperature coefficient. OL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (EMPCO) over C to +85 C is assumed to be 5% for an X5R dielectric. he tolerance of the capacitor (OL) is assumed to be %, and COU is 9. μf at.8 V, as shown in Figure 5. Substituting these values in the equation yields CEFF = 9. μf (.5) (.) 7. μf o guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. CAPACIANCE (µf) 8 6 3 5 6 DC BIAS VOLAGE (V) Figure 5. Capacitance vs. Voltage Characteristic able 9. Suggested. μh Inductors Vendor Model Dimensions (mm) ISA (ma) DCR (mω) Murata LQMMPNRNGB..6.9 85 Murata LQMHPNRMJL.5.. 5 9 Murata LQH3PNRNN 3..5.6 3 5 aiyo Yuden CBC35RMR 3..5.5 7 Coilcraft XFL-ME... 5 Coilcraft XPL-ML.9.. 8 89 oko MD5-CN.5.. 35 85 973-
Data Sheet he peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: V I RIPPLE IN RIPPLE = 8 fsw C OU V ( π fsw ) L COU Capacitors with lower effective series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: VRIPPLE ESRCOU I RIPPLE he effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 µf and a maximum of µf. he buck regulators require µf output capacitors to guarantee stability and response to rapid load variations and to transition into and out of the PWM/PSM modes. A list of suggested capacitors is shown in able. In certain applications where one or both buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the pin according to the operating state; consequently, it is possible to reduce the output capacitor from µf to.7 µf because the regulator does not expect a large load variation when working in PSM mode (see Figure 5). Input Capacitor Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: I CIN I LOAD( MAX) V OU ( V V IN IN V OU ) o minimize supply noise, place the input capacitor as close as possible to the VINx pin of the buck. As with the output capacitor, a low ESR capacitor is recommended. he effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 µf and a maximum of µf. A list of suggested capacitors is shown in able and able. able. Suggested μf Capacitors Vendor ype Model Case Size Murata X5R GRM88R6J6 63 6.3 DK X5R C68JBJ6K 63 6.3 aiyo Yuden X5R JMK7BJ6MA- 63 6.3 Panasonic X5R ECJVBJ6M 63 6.3 able. Suggested.7 μf Capacitors Vendor ype Model Case Size Murata X5R GRM88R6J75ME9D 6.3 aiyo Yuden X5R JMK7BJ75 6.3 Panasonic X5R ECJ-EBJ75M 6.3 able. Suggested. μf Capacitors Vendor ype Model Case Size Voltage Rating (V) Voltage Rating (V) Voltage Rating (V) Murata X5R GRM55B3J5K 6.3 Murata X5R GRM55R6A5KE5D. DK X5R C5JBJ5K 6.3 Panasonic X5R ECJEBJ5K 6.3 aiyo Yuden X5R LMK5BJ5MV-F..3V O 5.5V.7V O 5.5V C AVIN.µF C.7µF ON OFF C3 µf ON OFF AVIN VIN EN VIN C.7µF ON OFF C µf EN EN3 VIN3 EN VIN HOUSEKEEPING BUCK EN BUCK EN EN3 LDO (ANALOG) EN LDO (DIGIAL) AGND SW FB PGND SW FB PGND 3 FB3 FB L µh R R PWM L µh R3 R R5 R6 R8 R7 V OU @ ma C5 µf PSM/PWM V OU @ ma C6 µf V OU3 @ 3mA C7 µf V OU @ 3mA C8 µf 973- Figure 5. Processor System Power Management with PSM/PWM Control Rev. E Page of 8
LDO EXERNAL COMPONEN SELECION Feedback Resistors For the adjustable model, the maximum value of Rb is not to exceed kω (see Figure 9). Output Capacitor he LDOs are designed for operation with small, spacesaving ceramic capacitors, but function with most commonly used capacitors as long as care is taken with the ESR value. he ESR of the output capacitor affects stability of the LDO control loop. A minimum of.7 µf capacitance with an ESR of Ω or less is recommended to ensure that stability of the. ransient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the to large changes in load current. Input Bypass Capacitor Connecting a µf capacitor from VIN3 and VIN to ground reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance is encountered. If greater than µf of output capacitance is required, increase the input capacitor to match it. Input and Output Capacitor Properties Use any good quality ceramic capacitors with the as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 5 depicts the capacitance vs. voltage bias characteristic of a µf, V, X5R capacitor. he voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with higher voltage rating exhibits better stability. he temperature variation of the X5R dielectric is about ±5% over the C to +85 C temperature range and is not a function of package or voltage rating. CAPACIANCE (µf)...8.6.. 3 5 6 DC BIAS VOLAGE (V) Figure 5. Capacitance vs. Voltage Characteristic Data Sheet Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage: CEFF = CBIAS ( EMPCO) ( OL) where: CBIAS is the effective capacitance at the operating voltage. EMPCO is the worst-case capacitor temperature coefficient. OL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (EMPCO) over C to +85 C is assumed to be 5% for an X5R dielectric. he tolerance of the capacitor (OL) is assumed to be %, and CBIAS is.85 μf at.8 V as shown in Figure 5. Substituting these values into the following equation, CEFF =.85 μf (.5) (.) =.65 μf herefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. o guarantee the performance of the, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 973- Rev. E Page of 8
Data Sheet POWER DISSIPAION AND HERMAL CONSIDERAIONS he is a highly efficient µpmu, and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (5 C). When the temperature exceeds 5 C, the turns off all the regulators, allowing the device to cool down. When the die temperature falls below 3 C, the resumes normal operation. his section provides guidelines to calculate the power dissipated in the device and ensure that the operates below the maximum allowable junction temperature. he efficiency for each regulator on the is given by POU η = % () P IN where: η is the efficiency. PIN is the input power. POU is the output power. Power loss is given by PLOSS = PIN POU (a) or PLOSS = POU ( η)/η (b) Power dissipation can be calculated in several ways. he most intuitive and practical is to measure the power dissipated at the input and all the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). he difference between input and output power is dissipated in the device and the inductor. Use Equation to derive the power lost in the inductor and, from this, use Equation 3 to calculate the power dissipation in the buck converter. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, and the power lost on each LDO can be calculated using Equation. When the buck efficiency is known, use Equation b to derive the total power lost in the buck regulator and inductor, use Equation to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the two LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN,, and IOU. o account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation and the losses in the LDO provided by Equation. Rev. E Page 3 of 8 BUCK REGULAOR POWER DISSIPAION he power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: PDBUCK is the power dissipation on one of the buck regulators. PL is the inductor power losses. he inductor losses are external to the device, and they do not have any effect on the die temperature. he inductor losses are estimated (without core losses) by PL IOU(RMS) DCRL () where: DCRL is the inductor series resistance. IOU(RMS) is the rms load current of the buck regulator. r I OU ( RMS) = I OU + (5) where r is the normalized inductor ripple current. r = ( D)/(IOU L fsw) (6) where: L is the inductance. fsw is the switching frequency. D is the duty cycle. D = /VIN (7) buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. here are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PRAN (8) he power switch conductive losses are due to the output current, IOU, flowing through the P-MOSFE and the N-MOSFE power switches that have internal resistance, RDSON-P and RDSON-N. he amount of conductive power loss is found by PCOND = [RDSON-P D + RDSON-N ( D)] IOU(RMS) (9) where RDSON-P is approximately. Ω, and RDSON-N is approximately.6 Ω at 5 C junction temperature and VIN = VIN = 3.6 V. At VIN = VIN =.3 V, these values change to.3 Ω and. Ω, respectively, and at VIN = VIN = 5.5 V, the values are.6 Ω and. Ω, respectively.
Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. he amount of switching power loss is given by PSW = (CGAE-P + CGAE-N) VIN fsw () where: CGAE-P is the P-MOSFE gate capacitance. CGAE-N is the N-MOSFE gate capacitance. For the, the total of (CGAE-P + CGAE-N) is approximately 5 pf. he transition losses occur because the P-channel power MOSFE cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near (and from to ground). he amount of transition loss is calculated by PRAN = VIN IOU (trise + tfall) fsw () where trise and tfall are the rise time and the fall time of the switching node, SW. For the, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. he converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation he power loss of a LDO regulator is given by PDLDO = [(VIN ) ILOAD] + (VIN IGND) () where: ILOAD is the load current of the LDO regulator. VIN and are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small and it can be ignored. he total power dissipation in the simplifies to PD = PDBUCK + PDBUCK + PDLDO + PDLDO (3) Data Sheet JUNCION EMPERAURE In cases where the board temperature, A, is known, the thermal resistance parameter, θja, can be used to estimate the junction temperature rise. J is calculated from A and PD using the formula J = A + (PD θja) () Refer to able 7 for the thermal resistance values of the LFCSP and SSOP packages. A very important factor to consider is that θja is based on a -layer in 3 in,.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper used to remove the heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. he exposed pad should be connected to the ground plane with several vias. If the case temperature can be measured, the junction temperature is calculated by J = C + (PD θjc) (5) where C is the case temperature and θjc is the junction-to-case thermal resistance provided in able 7. When designing an application for a particular ambient temperature range, calculate the expected power dissipation (PD) due to the losses of all channels by using the Equation 8 to Equation 3. From this power calculation, the junction temperature, J, can be estimated using Equation. he reliable operation of the converter and the two LDO regulators can be achieved only if the estimated die junction temperature of the (Equation ) is less than 5 C. Reliability and mean time between failures (MBF) are highly affected by increasing the junction temperature. Additional information about product reliability can be found from the ADI Reliability Handbook, which can be found at www.analog.com/reliability_handbook. Rev. E Page of 8