TVS Diodes Transient Voltage Suppressor Diodes ESD101-B1-02 Series Bi-directional Ultra Low Capacitance TVS Diode ESD101-B1-02ELS ESD101-B1-02EL Data Sheet Revision 1.2, 2013-07-22 Final Power Management & Multimarket
Edition 2013-07-22 Published by Infineon Technologies AG 81726 Munich, Germany 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Revision History: Rev..1.1, 2013-06-12 Page or Item Subjects (major changes since previous revision) Revision 1.2, 2013-07-22 All ESD101-B1-02EL status change to final Trademarks of Infineon Technologies AG AURIX, BlueMoon, COMNEON, C166, CROSSAVE, CanPAK, CIPOS, CoolMOS, CoolSET, CORECONTROL, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, EUPEC, FCOS, HITFET, HybridPACK, ISOFACE, I²RF, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PROFET, PRO-SIL, PRIMARION, PrimePACK, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SMARTi, SmartLEWIS, TEMPFET, thinq!, TriCore, TRENCHSTOP, X-GOLD, XMM, X-PMU, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, PRIMECELL, REALVIEW, THUMB of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Sattelite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update 2010-06-09 Final Data Sheet 3 Revision 1.2, 2013-07-22
Bi-directional Ultra Low Capacitance TVS Diode 1 Bi-directional Ultra Low Capacitance TVS Diode 1.1 Features ESD / Transient protection of RF signal lines according to IEC61000-4-2: ±12 kv (contact), ±14 kv (air) Extremely low capacitance C L =0.1pF (typical) Maximum working voltage: V RWM =±5.5V Very low reverse current: I R <0.1nA Very low series inductance down to 0.2 nh typical (TSSLP-2-4) Extremely small form factor down to 0.62 x 0.32 x 0.31 mm² Pb-free package (RoHS compliant) 1.2 Application Examples Tailored for ESD Protection of capacitance-susceptible application like Super high speed interface RF antenna 1.3 Product Description Pin 1 Pin 2 Pin 1 Pin 1 marking (lasered) TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd Figure 1 Pin configuration and Schematic diagram Table 1 Ordering Information Type Package Configuration Marking code ESD101-B1-02ELS TSSLP-2-4 1 line, bi-directional R ESD101-B1-02EL TSLP-2-20 1 line, bi-directional R Final Data Sheet 4 Revision 1.2, 2013-07-22
Characteristics 2 Characteristics Table 2 Maximum Ratings at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. ESD contact discharge 1) contact air V ESD -12-14 Operating temperature T OP -55 125 C Storage temperature T stg -65 150 C 1) V ESD according to IEC61000-4-2 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 12 14 kv 2.1 Electrical Characteristics at T A = 25 C, unless otherwise specified V F Forward voltage I F I F Forward current I PP V R Reverse voltage R DYN I R Reverse current I Hold I Trig V Trig V Hold V RWM I RWM V CL V R V CL I RWM V RWM V Hold V Trig I Trig I Hold R DYN -I PP I R R DYN Dynamic resistance V FC Forward clamping voltage V Trig Triggering reverse voltage I Trig Triggering reverse current V CL Clamping voltage I Hold Holding reverse current V Hold Holding reverse voltage I PP Peak pulse current V RWM Reverse working voltage maximum I RWM Reverse working current maximum Figure 2 Definitions of electrical characteristics Diode_Characteristic_Curve_with _snapback_bi-directional.vsd Final Data Sheet 5 Revision 1.2, 2013-07-22
Characteristics Table 3 DC Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM -5.5 5.5 V Trigger voltage V Trig 7.3 V I BR = 1 ma, from Pin 1 to Pin 2 7.3 V I BR = 1 ma, from Pin 2 to Pin 1 Reverse current I R <1 50 na V R =5.5V Table 4 RF Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Line capacitance C L 0.2 pf V R =0V, f =1MHz 0.1 pf V R =0V, f = 1 GHz Serie inductance L S 0.2 0.4 nh ESD101-B1-02ELS ESD101-B1-02EL Table 5 ESD Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Clamping voltage 1) V CL 18 V I TLP =8A 30 V I TLP =16A Dynamic resistance 1) R DYN 1.5 Ω t p =100ns 1) ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z 0 =50Ω, t p =100ns, t r = 0.6 ns I TLP and V TLP averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between I TLP1 = 10 A and I TLP2 = 30 A. Please refer to Application Note AN210[1]. Final Data Sheet 6 Revision 1.2, 2013-07-22
Typical Characteristic 3 Typical Characteristic The curves are all specified at T A =25 C 10-3 10-4 10-5 10-6 I R [A] 10-7 10-8 10-9 10-10 10-11 10-12 0 1 2 3 4 5 V R [V] Figure 3 Reverse current: I R = f(v R ) 150 125 100 C L [ff] 75 50 25 0-5 -4-3 -2-1 0 1 2 3 4 5 V R [V] Figure 4 Line capacitance C L = f(v R ), f z=1ghz Final Data Sheet 7 Revision 1.2, 2013-07-22
Typical Characteristic 20 ESD101-B1-02Eseries R DYN 10 15 7.5 10 R DYN = 1.5 Ω 5 5 2.5 I TLP [A] 0 0 Equivalent V IEC [kv] -5-2.5-10 R DYN = 1.5 Ω -5-15 -7.5-20 -10-40 -30-20 -10 0 10 20 30 40 V TLP [V] Figure 5 Clamping voltage (TLP): I TLP = f(v TLP ) according ANSI/ESD STM5.5.1- Electrostatic Dischange Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z 0 =50Ω, t p =100ns, t r =0.6ns, I TLP and V TLP averaging window: t 1 =30ns to t 2 = 60 ns, extraction of dynamic resistance using squares fit to ELP charactersistic between I TLP1 =5A and I TLP2 = 40 A. Please refer to Application Note AN210 [1] Final Data Sheet 8 Revision 1.2, 2013-07-22
Typical Characteristic 350 300 Scope: 20 GS/s 250 V CL [V] 200 150 100 50 0 V CL-max-peak = 300 [V] V CL-30ns-peak = 25 [V] -50-50 0 50 100 150 200 250 300 350 400 450 t p [ns] Figure 6 Clamping voltage at +8 kv discharge according IEC61000-4-2 (R =330Ω, C =150pF) 50 0 Scope: 20 GS/s V CL [V] -50-100 -150-200 -250-300 V CL-max-peak = -304 [V] V CL-30ns-peak = -19 [V] -350-50 0 50 100 150 200 250 300 350 400 450 t p [ns] Figure 7 Clamping voltage at -8 kv discharge according IEC61000-4-2 (R =330Ω, C = 150 pf) Final Data Sheet 9 Revision 1.2, 2013-07-22
Package Information 4 Package Information 4.1 TSSLP-2-4 Top view +0.01 0.31-0.02 Bottom view 0.32±0.05 Cathode marking 0.05 MAX. 1) Dimension applies to plated terminals 0.355 2 1 1) 0.26±0.035 1) 0.2 ±0.035 0.62 ±0.05 TSSLP-2-3, -4-PO V01 Figure 8 TSSLP-2-4 Package outline 0.32 0.24 0.27 0.24 0.19 0.19 0.19 0.62 0.57 0.14 Copper Solder mask Stencil apertures TSSLP-2-3, -4-FP V02 Figure 9 TSSLP-2-4 Footprint 4 0.35 marking Ey 8 Tape type Punched Tape Embossed Tape Ex Ey 0.43 0.73 0.37 0.67 Cathode marking Figure 10 Ex TSSLP-2-4 Packing Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. TSSLP-2-3, -4-TP V03 Type code 1 Figure 11 TSSLP-2-4 Marking (example) Cathode marking Final Data Sheet 10 Revision 1.2, 2013-07-22
Package Information 4.2 TSLP-2-20 Top view +0.01 0.31-0.02 Bottom view 0.05 MAX. 0.6 ±0.05 0.65 ±0.05 2 1 1±0.05 Cathode marking 1) 0.5 ±0.035 1) Dimension applies to plated terminals 1) 0.25 ±0.035 TSLP-2-19, -20-PO V01 Figure 12 TSLP-2-20 Package outline 0.6 0.35 0.45 0.35 0.28 0.28 0.38 1 0.3 0.93 Copper Solder mask Stencil apertures TSLP-2-19, -20-FP V01 Figure 13 TSLP-2-20 Footprint 4 0.4 Cathode marking 1.16 8 0.76 TSLP-2-19, -20-TP V02 Figure 14 TSLP-2-20 Packing 12 Type code Cathode marking TSLP-2-19, -20-MK V01 Figure 15 TSLP-2-20 Marking (example) Final Data Sheet 11 Revision 1.2, 2013-07-22
References References [1] Infineon Technologies AG, Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology, Application Note 210, RF and Protection Devices, April 22, 2010, Rev.1.0 [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages Final Data Sheet 12 Revision 1.2, 2013-07-22
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