Bitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture. (4,4 x,0 cm) EMC Simulation EMC Simulation of a SEPIC DC-DC Conducted Emissions and Radiated Emissions 04 05 09 Leading Technical Expert "EMC Modeling & Simulation" EMC Validation Engineering / Simulation QL RBG 3 Qualification Laboratory Regensburg
EMC Simulation Capabilities EMC Simulation during Development IC / Component Schematic / PCB ECU System Level Analog simulation Analog simulation 3D simulation PCB Signal integrity 3D simulation PCB Housing 3D simulation PCB Housing Cable harness Development Process Innovation and Roadmap Quotation Concept Refinement Development Product Validation Series Production
Simulation Tasks Simulation of a Single-ended primary-inductor converter (SEPIC) DC-DC SEPIC DC-DC allows the electrical potential (voltage) at its output to be greater than, less than, or equal to its input. The output of the SEPIC is controlled by the duty cycle of the control transistor. Agenda Design Studio Simulation: Functional Simulation DC-DC Converter Conducted Emissions Simulation Microwave Studio: Simulation of the PCB Cable Studio: Simulation of Wires Radiated Emissions Simulation Summery and Outlook 3
Schematic Supplier Evaluation Board Battery 3.5V Controller for Switching Regulators Diode Load 8Ω / 5V MOSFET 4
Schematic Design Studio EMC Setup: Conducted Emissions Pspice Models S-Parameter R,L,C Components Battery_LISN 50 Coil_ Load 3 ' Mosfet Diode ssp4 Load Battery 0 m 3.5 V 50 n_r_flry_0qmm50_ n_r_flry_0qmm50_ 0cm Wire n_r_flry_0qmm50_ n_r_flry_0qmm50_ Wire_L0m_H50mm_Q0qmm50 L0UH_06749.SP 3 irf8707pbf ' R=8Ω GND_LISN 3 MOSFET 0.05 GND L0UH_06749.SP 5
LISN LISN: Line Impedance Stabilization Network A LISN is a low-pass filter typically placed between an AC or DC power source and the EUT (Equipment Under Test) to create a known impedance and to provide an RF noise measurement port. 3 3 u 5 u 00 n 6
Voltage/Current at MOSFET and Output Voltage Output Voltage: 5V 7
Voltage at LISN 8
EMI Test Receiver CISPR 6-- 9
Conducted Emissions 00 90 80 Conducted Emissions LISN (BW 9KHz, 0kHz) Battery LISN 00kHz 08MHz DS_wo_Filter_wo_Wire LISN_Battery.txt_PK.mes - CISPR 5 Limit (Peak/Average) DS_wo_Filter_wo_Wire LISN_Battery.txt_AV.mes - Simulation Peak - Simulation Average CISPR 5_class5_00803_CE_PK.lim CISPR 5_class5_00803_CE_AV.lim Interference Voltage Level [dbµv] 70 60 50 40 30 0 0 0-0 M 0M 00M Frequency [Hz] 0
DCDC Layout SEPIC DC-DC Layout: Layer Eagle Gerber ODB++ DCDC Layout: Top DCDC Layout: Bottom
DCDC Layout. Layout Import MWS. Ports Definition 3. F-Solver Simulation 4. Total Solver Time: 679 s (= h, 53m, s)
DCDC Simulation with Layout in Design Studio Battery_LISN 3 50 n_r_flry_0qmm50_ Voltage n_r_flry_0qmm50_ (PCB_Input_VCC) Load 4 (PCB_Output_VCC) Load R=8Ω 0 m LISN n_r_flry_0qmm50_ n_r_flry_0qmm50_ Wire_L0m_H50mm_Q0qmm50_ (PCB_Input_GND) 7 (C4) 3 (L_in) 5 (PCB_Output_GND) 8 (Cout_3) 7 (Lout) Load_GND Battery 3.5 V GND_LISN 3 50 8 (C3) 9 (C) 0 (C) 6 (Cout_) 5 (Cout_) LISN (L) 6 (Mosfet) 9 (Rsen) (CS) n 3 (L) 4 (D) Diode 0.05 ssp4 EMC Setup: Conducted Emissions L0UH_06749.SP 5 gate drain L0UH_06749.SP source 00 k IPD03N03M_L0 3
Conducted Emissions 00 80 Conducted Emissions LISN (BW 9KHz, 0kHz) Battery LISN 00kHz 08MHz Simulation_Battery _LISN.txt_Cutted_PK.mes CISPR5 5 CE PK.lim - CISPR CISPR5 55 CE Limit PK.lim - Simulation Peak - Measurement Peak Interference Voltage Level [dbµv] 60 40 0 0 Note: Offset due to FFT window function? -0 00k M 0M 00M Frequency [Hz] 4
Conducted Emissions 00 80 Conducted Emissions LISN (BW 9KHz, 0kHz) Battery LISN 00kHz 08MHz Simulation_Battery _LISN.txt_Cutted_PK.mes CISPR5 5 CE AV.lim - CISPR CISPR5 55 CE Limit AV.lim - Simulation Average - Measurement Average Interference Voltage Level [dbµv] 60 40 0 0-0 00k M 0M 00M Frequency [Hz] 5
DCDC Simulation with Layout in Design Studio m cable harness Load R=8Ω EMC Setup: Conducted Emissions 6
Cable Studio m cable harness 7
Conducted Emissions 00 80 Conducted Emissions LISN (BW 9KHz, 0kHz) Battery LISN 00kHz 08MHz Simulation_Wire_Battery _LISN_wire.txt_PK.mes CISPR5 5 CE PK.lim CISPR5 5 CE PK.lim - Peak, 5 Limit - Simulation - Measurement 60 Interference Voltage Level [dbµv] 40 0 0-0 00k M 0M 00M Frequency [Hz] 8
Conducted Emissions 00 80 Conducted Emissions LISN (BW 9KHz, 0kHz) Battery LISN 00kHz 08MHz AV-LISN_PCB3_Nr0.mes AV-LISN_PCB3_Nr0.mes CISPR5 5 CE AV.lim - Average, CISPR Limit - Simulation - Measurement 60 Interference Voltage Level [dbµv] 40 0 0-0 00k M 0M 00M Frequency [Hz] 9
Radiated Emissions Simulation: Monopole Setup Standard Test Setup: Harness length: m Harness height: 5cm Harness Twisted Monopole Antenna Cable Harness 0
Radiated Emissions 80 70 Radiated Emissions LISN (BW 9KHz, 0kHz) Battery LISN 00kHz 08MHz PK-RE30MHz LISN_PCB_Nr.mes Simulation - Simulation - Measurement Measurement Antenna.txt_Cutted_PK.mes 60 50 Interference Voltage Level [dbµv] 40 30 0 0 0-0 Note: Resonance Measurement Setup -0 00k M 0M Frequency [Hz]
Summary and Outlook Time Domain Simulation in Design Studio works Summary Time Domain Simulation with Layout and Wire Harness possible Conducted and Radiated Emissions shows good comparability Challenging Setup of different GUI and Solver Outlook Increased speed of time domain Simulations in Design Studio? Stability Design Studio
Thank you for your Attention Felix Müller Leading Technical Expert "EMC Modeling & Simulation" EMC Validation Engineering / Simulation Qualification Laboratory Regensburg 3
EMI Test Receiver CISPR 6-- EMI Test Receiver: Detectors Detectors IF-Signal Envelope- Detector Peak U t Average U t Quasipeak U t 4