7 Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 JPE 13-1-8 http://dx.doi.org/1.6113/jpe.213.13.1.7 rnsformerless hree-level DC-DC Buck Converter with High Step-Down Conversion tio Yun Zhng, Xing-to Sun **, Yi-feng Wng *, nd Hong-jun Sho * * School of Electricl Engineering nd Automtion, injin University, injin, Chin ** School of Electricl Engineering nd Automtion, injin Polytechnic University, injin, Chin Astrct For high power high step-down dc-dc conversion pplictions, conventionl three-level dc-dc converters re suject to extreme duty cycles or incresed volume nd cost due to the use of trnsformers. In this pper, trnsformerless three-level dc-dc uck converter with high step-down conversion rtio is proposed. he converter comprises two symmetricl hlf ridges, which re of the neutrl point clmped structures. herefore, the output pulse voltge of the converter cn e otined in terms of the voltge difference etween the two hlf ridges. In order to relize hrmonious switching of the converter, modultion strtegy with cpcitor voltges self lnce is presented. According to the deduced output dc voltge function, trnsformerless opertion without extreme duty cycles cn e implemented. Experimentl results from 1kW prototype verify the vlidity of the proposed converter. It is suitle for ship electric power distriution systems. Key words: DC-DC uck converter, High step-down conversion, Non-extreme duty cycles, hree-level I. INODUCION With the development of power electronics techniques, there hs een growing interest in multilevel converters for high power nd high voltge pplictions [1]-[6]. Bsiclly, there re three types of multilevel inverters for dc-c pplictions: diode-clmped inverters, flying-cpcitor inverters, nd cscded H-ridge inverters [7]-[9]. In 1981, the neutrl point clmped (NPC) three-level inverter ws proposed y A. Ne [1]. During the following yers, this concept for multilevel conversion technique hs een pplied to dc-dc pplictions. J.. Pinheiro proposed three-level ZVS (zero-voltge switching) PWM converter with the NPC structure in 1992 [11]. hen new concept in high voltge dc-dc conversion ws estlished. Lter, the sic fmily of three-level dc-dc converters ws discussed in [12]. From the conventionl hlf ridge converter, the hlf ridge three-level converter ws derived with the so-clled three-level switch cells. hen, six nonisolted three-level converters sed on the uck, oost, Mnuscript received Dec. 11, 211; revised Nov. 21, 212 ecommended for puliction y Associte Editor Hnju Ch. Corresponding Author: zhngy@tju.edu.cn el: +86-13-322-176, injin University * School of Electricl Eng. nd Automtion, injin University, Chin ** School of Electricl Eng. nd Automtion, injin Polytechnic University, Chin uck-oost, Cuk, SEPIC, nd Zet topologies were otined, s well s five isolted three-level converters sed on the forwrd, flyck, push-pull, hlf ridge, nd full ridge topologies. As for three-level step-down converters, the non-isolted three-level dc-dc uck converter is the sic topology to implement the conversion from high voltge input to low voltge output. Unfortuntely, this sic topology my lso e suject to extreme duty cycles when high step-down conversion is required [13]. herefore, the output rectifier diode in the sic three-level uck converter must sustin short pulse width current with high mplitude, which leds to severe reverse recovery nd high electromgnetic interference (EMI) prolems [14], [15]. Moreover, extreme duty cycles re not desirle, ecuse no spce is left for the controller to compenste chnges in lod or line. Another solution to chieve high step-down voltge gin is to increse the turns rtio of the trnsformer. Such n isolted three-level dc-dc converter cn del with the input high voltge nd void the extreme duty cycles due to the presence of trnsformer. Although the circulting current cn e minimized effectively, the trnsformer design is criticl to the success of the converter performnce [16]. However, severl pplictions require high step-down non-isolted dc-dc converters, for exmple, the uck type PFC (power fctor correction) [17], the uck converter used
Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 71 in ship electric power distriution systems [16], nd so on. A trnsformerless dc-dc converter without extreme duty cycles is necessry to decrese the volume nd to increse efficiency. In this pper, trnsformerless three-level dc-dc uck converter with high step-down conversion rtio is proposed for ship electric power distriution systems. his converter cn convert high DC us voltge to low DC voltge for importnt DC lods of high power. In Section II, the circuit of the converter is presented nd the opertion principles re descried in detil. hen modultion strtegy which cn stisfy the opertion of the converter is proposed with the cpcitor voltges self lnce, nd the function of the output dc voltge V o is deduced. Moreover, the principle of trnsformerless opertion without extreme duty cycles is lso clrified when the step-down conversion rtio is rther high. In Section III, 1 kw hrdwre prototype for the resistive lod hs een designed nd tested to verify the vlidity of the converter opertion nd performnce. II. OPEAIONAL PINCIPLES OF HE POPOSED CONVEE A. opology nd Opertion of the Converter Fig. 1 shows the proposed trnsformerless three-level dc-dc uck converter with high step-down conversion rtio. V in is the input dc voltge. he input filtering cpcitors C 1 nd C 2 re series connected nd serve s cpcitive voltge divider to split the input dc voltge V in into two equl voltges V nd V. hen there re three voltge levels: zero, V in /2 nd V in. he converter comprises the left hlf ridge (LHB) nd the right hlf ridge (HB). he LHB consists of the power switches Q 1 nd Q 2, nd the diodes D 1 nd D 2, whose locking voltges re ll clmped t V in /2 vi the clmped diodes D c1 nd D c2. he HB consists of the power switches Q 3 nd Q 4, nd the diodes D 3 nd D 4, whose locking voltges re lso clmped t V in /2 vi the clmped diodes D c3 nd D c4. Finlly, the output dc voltge V o is otined y the filters (L f nd C f ) etween the output ports nd of the converter for supplying power to the lod, s shown in Fig. 1. Both the LHB nd the HB cn operte, nd the switching stte concept is introduced in this pper, nmely S x or 1 denotes tht Q x is off or on (x1~4). As for the LHB, the three-level output voltge V g is V in when the switching stte is S 1 S 2 11. If the switching stte is S 1 S 2 1, V g is V in /2, which is the voltge cross C 2, nd the voltge stress of Q 1 is V in /2 (the voltge cross C 1 ). V g ecomes zero when the switching stte is S 1 S 2. Menwhile, D 1 nd D 2 re freewheeling, nd Q 1 nd Q 2 re oth clmped y the voltges (V in /2) cross C 1 nd C 2, respectively. As for the HB, the three-level output voltge V g is zero when the switching stte is S 3 S 4 11. When the switching stte is S 3 S 4 1, V g is V in /2 (the voltge cross C 2 ), nd the V in C 1 C 2 n p g Q 1 Q 2 D c1 D c2 D 1 D 2 LHB + Vo - locking voltge of Q 4 is the voltge cross C 2. V g is V in when the switching stte is S 3 S 4, nd D 3 nd D 4 re freewheeling. At the sme time, the locking voltges of Q 3 nd Q 4 re cross C 1 nd C 2, respectively. As result, the output pulse voltge (V ) etween the output ports nd of the proposed converter cn e otined s follows: V Vg - Vg (1) According to (1), the ville pulse voltge V cn e generted in the cse of hrmonious switching of the four power switches Q 1 ~Q 4, nmely the switching stte S 1 S 2 S 3 S 4. Assuming tht the inductor current i L is continuous, there re six opertion modes of the proposed converter, s shown in Fig. 2. When the switching stte is S 1 S 2 S 3 S 4 11, i L flows through: Q 2, the filter nd the lod (L f, C f nd ), Q 3, nd the clmped diodes D c4 nd D c1, s shown in Fig. 2(). hen the pulse voltge V is zero. When i L flows through the filter nd lod, the power switches Q 3 nd Q 4, nd diodes D 2 nd D 1, s shown in Fig. 2(), V is lso zero. Under similr condition to Fig. 2(), s shown in Fig. 2(c), i L flows through the filter nd lod, diodes D 4 nd D 1, nd the power switches Q 1 nd Q 2. Consequently, V is zero ll the sme. he opertion modes in Figs. 2()~(c) re ll in freewheeling sttes due to the continuous inductor current i L. Nmely, the converter hs three redundnt sttes for V. When the switching stte is S 1 S 2 S 3 S 4 111, s shown in Fig. 2(d), the inductor current i L flows through the filter nd the lod, the power switches Q 3 nd Q 4, the filtering ottom cpcitor C 2, the clmped diode D c1 nd the power switch Q 2. hen V V in /2 cn e otined due to the voltge cross the ottom divided cpcitor C 2. As result, C 2 is dischrged to supply the energy for the lod. In ddition, V V in /2 cn e generted when the switching stte is S 1 S 2 S 3 S 4 111, s shown in Fig. 2(e). hen, the inductor current i L flows through the filter nd the lod, the power switch Q 3, the clmped diode D c1, the filtering upper cpcitor C 1, nd the power switches Q 1 nd Q 2. herefore, the upper divided cpcitor C 1 is lso dischrged, tking the HB Fig. 1. Circuit digrm of the proposed converter. L f i L V g C f V g Q 3 Q 4 D 3 D 4 D c3 D c4
72 Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 + - Vo power supply for the lod. Nmely, there is the nother redundnt switching stte for V V in /2. he lst opertion mode, s shown in Fig. 2(f), cn e relized when the switching stte is S 1 S 2 S 3 S 4 1111. hen, the inductor current i L flows through the filter nd the lod, the HB power switches Q 3 nd Q 4, the input dc power supply V in, nd the LHB power switches Q 1 nd Q 2. Hence the pulse voltge V ecomes V in. B. Modultion Strtegy with Cpcitor Voltges Self Blnce In order to crry out hrmonious switching of the converter s power switches nd to chieve high voltge gin, the key modultion strtegy is proposed in Fig. 3, sed on the principle of the proposed converter. he modultion indices of the left nd right hlf ridges re m nd m, respectively, s shown in Fig. 3(). Both crrier wves (crrier1 nd crrier2) re π phse-shifted. In every crrier period (), the modultion lw is designed s follows: + - Vo () S 1 S 2 S 3 S 4 11, V. () S 1 S 2 S 3 S 4 11, V. + - Vo + Vo - (c) S 1 S 2 S 3 S 4 11, V. (d) S 1 S 2 S 3 S 4 111, V V in /2. + - Vo + (e) S 1 S 2 S 3 S 4 111, V V in /2. Fig. 2. Vo - (f) S 1 S 2 S 3 S 4 1111, V V in. opologicl opertion modes of the proposed converter. ìm > Vcrrier1,S1 ïm > Vcrrier2,S2 1 í (2) ïm > Vcrrier1,S3 1 ï îm > Vcrrier2,S4 where V crrier1 nd V crrier2 re the instntneous vlues of crrier1 nd crrier2, respectively. By virtue of (2), the gte signls of the four power switches S 1 ~S 4 (s well s the switching sttes) re shown in Figs. 3()~(e) nd (h). hen, the output three-level voltges re generted y ech hlf ridge, s shown in Figs. 3(f) nd (g). king dvntge of (1), the pulse voltge V cn e shown in Fig. 3(h). here re five switching sttes (S 1 S 2 S 3 S 4 ) in the first hlf period (~/2) due to redundnt switching sttes. In order these switching sttes re: 11-111-11-111-11 (s shown in Fig. 3(h)). hen, the two voltge pulses of V (V in /2) cn e otined etween the output ports nd just when the switching stte is 111, s shown in Fig. 3(h). his results in the dischrging of the upper divided cpcitor C 1 for the lod, s shown in Fig. 3(j). Similrly, in the second hlf period (/2~), the corresponding five switching sttes re in order: 11-111-11-111-11. hen, the other two voltge pulses of V (V in /2) re otined due to the switching stte 111, s shown in Fig. 3(h). As result, the lod is supplied y the ottom divided cpcitor C 2, nd C 2 is dischrged, s shown in Fig. 3(k). It is worth noting tht there is only one switching chnge etween the djcent switching sttes, s depicted in Fig. 3(h). Consequently, the requirement of miniml switching losses cn e met freely. According to the nlysis of the topologicl opertion modes, when V V in /2, oth C 1 nd C 2 re chrged nd dischrged in turn in every crrier period, s shown in Figs. 3(j) nd (k). he modultion wves m nd m nd the verge inductor current I L cn ll e considered constnt in every crrier period. In ddition, the crriers re symmetricl, so the dischrging/chrging time of C 1 nd C 2 cn e equl, nmely t 1_3 t 2_4, s shown in Figs. 3(c) nd (d). herefore, the voltges (V nd V ) cross C 1 nd C 2 cn e self lnced in ech crrier period. Furthermore, the equivlent frequency of V is doule the switching frequency, s shown in Figs. 3() nd (h). Assuming tht the inductor current i L is continuous, the energy W st is stored y L f when V is V in /2. his leds to i L incresing linerly, s shown in Fig. 3(i). he energy W tr is trnsferred when V is, nd it results in i L decresing linerly, s shown in Fig. 3(i). In every crrier period, W st nd W tr cn e descried s follows: ìwst ( / 2 - Vo ) IL 2 ( ton1 - toff3) ï íwtr Vo IL [ - 2 ( ton1 - toff3)] ï îwst Wtr (3)
Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 73 1 m m.5 S 1 S 2 S 3 S 4 V g V in/2 V g crrier1 t on1 t 1-3 t 1-3 t off3 V in crrier2 t off2 t 2-4 t 2-4 t on4 () () (c) (d) (e) (f) V in/2 V in (g) V V in/2 11 11 1111 11 11 (h) 111 111 /2 111 111 is dischrged is dischrged is dischrged is dischrged i L V V /2 (i) (j) (k) Fig. 3. Modultion strtegy with cpcitor voltges self lnce. where V o is the output dc voltge fter the L f C f filter, t on1 is the gte-on time of the power switch Q 1, nd t off3 is the gte-off time of the power switch Q 3, s shown in Fig. 3. From Figs. 3()~(e), the corresponding duty cycles d 1 ~d 4 of the four power switches Q 1 ~Q 4 re descried s: ì ton1 d1 d4 1- m ï í ï - toff3 d3 d2 m ïî By comining (3) nd (4), V o cn e written s: o in (4) V V ( m - m ) (5) Nmely, Vo ( d1 + d2-1) cn e otined nd the limited conditions re m < m 1 nd m + m > 1. C. rnsformerless Opertion without Extreme Duty Cycles For conventionl three-level dc-dc uck converters without trnsformers, high step-down conversion my lwys e chieved y mens of extreme duty cycles. For exmple, when the voltge gin is higher, 1 (V in /V o ), the conventionl duty cycle my e.1, which is fr from.5. Fortuntely, the duty cycles of the proposed trnsformerless scheme my e.6 nd.5 y setting m.6 nd m.5, y virtue of (4) nd (5). In fct, the essence of trnsformerless opertion without extreme duty cycles is tht the output pulse voltge V is otined from the three-level voltge difference etween V g nd V g, y mens of Figs. 3(f)~(h). he short pulse width is up to the switching time intervls t 1_3 nd t 2_4, s shown in Figs. 3(d) nd (e), which cn e descried s: ì ton1 - toff3 t1_ 3 ï 2 í (6) ï ton4 - toff2 t2 _ 4 ïî 2 nd t 1_3 t 2_4 cn e confirmed due to the symmetricl geometry reltionships in Fig. 3. According to (4)~(6), n identicl voltge gin hs infinite solution sets for m nd m. As result, with higher step-down conversion rtio, optimum duty cycles cn e chosen for the trnsformerless opertion of the proposed converter, insted of the extreme ones. he simple selection method for m nd m is to first set m s constnt, for exmple,.55 in this pper, ccording to the trdeoff etween the duty cycles (d 1 nd d 4 ) which re ner.5, nd the fluctuting mplitude of the inductor current. hen m cn e otined y mens of the output (m -m ) of the current PI controller. D. Filter Design of the Converter he filter of the proposed converter is importnt in terms of its opertion performnce, nd it includes the filtering inductor L f, nd the filtering cpcitor C f. herefore, the minimum vlues of L f nd C f cn e otined ccording to the required mximum inductor current ripple ΔI L_mx nd the output voltge ripple ΔV o_mx, respectively. According to (3) nd Fig. 3, when V is zero the energy stored in L f is trnsferred, which leds to the filtering inductor current flling. As result, the longer the flling time, the lrger the inductor current ripple ecomes. In this pper, the longer flling time t f is t off2 or t off3, s shown in Figs.3 (c) nd (d). hen t f cn e otined s: t (1 - d ) (7) f 2 where is the crrier period. During t f, the voltge of L f is written s: u - V -( d + d - 1) V (8) L o 1 2 in In ddition, the inductor current ripple ΔI L cn e descried s: -u L D IL tf (9) By sustituting (7) nd (8) into (9), the inductor current ripple ΔI L cn e written s: ( d + d - 1) (1 - d ) V 1 2 2 in D IL (1) When d 1 is set s.5, d 2 is clculted s.75, nd ΔI L_mx cn e otined s:
74 Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 V in D IL_mx (11) 16 herefore, the minimum vlue of L f is limited y mens of the required mximum inductor current ripple ΔI L_mx : L f_min 16DI L_mx (12) In ddition, the output voltge ripple ΔV o cn e descried s: 1 DIL D IL D Vo (13) C 2 8 16C f Hence the minimum vlue of C f is descried ccording to the inductor current ripple ΔI L nd the required output voltge ripple ΔV o_mx : C f_min D IL 16DV o_mx f (14) As result, the filter design of the converter cn e completed theoreticlly y mens of (12) nd (14). III. EXPEIMENAL ESULS he proposed converter with the voltge nd current doule-loop control scheme, in which PI controllers re dopted hs een experimentlly verified. he 1kW hrdwre prototype hs een set up in the l, s shown in Fig. 4. he experimentl prmeters nd components re listed in. 1. Fig. 5 shows the pulse voltge V (the mplitude of the pulse voltge is hlf the input dc voltge), the inductor current i L, nd the output dc voltge V o, which is constnt 68V output, nd smll ripple is chieved within ±2%. Fig. 6 shows the wveforms of voltges cross the power switches Q 1 nd Q 2, in which the locking voltges re lso the ones cross the divided cpcitors C 1 nd C 2. herefore, the voltges of C 1 nd C 2 re self lnced, nd oth of the duty cycles re round.45 nd.686, insted of.136 (68/5). Both of these vlues re closer to.5. Such non-extreme duty cycles re necessry for the converter when the switching frequency is incresed to minimize the filter. he output three-level voltges of the hlf ridges V g, nd V g re shown in Fig. 7. hey re in greement with the theoreticl nlysis in Figs. 3(f) nd (g). min controller left hlf ridge right hlf ridge AC-DC rectifier input filtering cpcitors ABLE I EXPEIMENAL PAAMEES AND COMPONENS prmeters nd components rted power P n input dc voltge V in reference voltge V ref input filtering cpcitors C 1 C 2 output filtering cpcitor C f vlues (units) 1 kw 5~64 V 68 V 22 μf 16 μf inductor L f 317 μh switching frequency f c 1 khz nd 11.36kHz lod resistor L 3.8~ 5 W power switches Q 1 ~Q 4 FGA3N6 (6V, 3A) diodes D 1 ~D 4 nd D c1 ~D c4 MU36 (6V, 3A) K pv of voltge PI controller 1.2 K iv of voltge PI controller 112 K pc of current PI controller.21 K ic of current PI controller 11.23 V (2V/div) (1A/div) Vo (2V/div) t(2μs/div) Fig. 5. Experimentl wveforms of V (upper), i L (middle), nd V o (ottom), when V in 5V nd f c 1kHz. V (C-E) (1V/div) V (C-E) (1V/div) locking voltges t(2μs/div) d 1» 45% d 2» 68.6% Fig. 6. Experimentl wveforms of voltges cross Q 1 (upper) nd Q 2 (ottom), when V in 5V nd f c 1kHz. Vg (2V/div) Vg (2V/div) t(2μs/div) Fig. 7. Experimentl wveforms of the output three-level voltges of V g (upper), nd V g (ottom), when V in 5V nd f c 1kHz. filtering inductor voltge nd current sensors Fig. 4. 1kW hrdwre prototype. output ports nd output filtering cpcitor lod resistor Fig. 8 shows the pulse voltge V (the mplitude of the pulse voltge is still hlf the input dc voltge), the inductor current i L, nd the output dc voltge V o when V in is chnged to 64V. V o is still controlled t constnt 68V output for the wide-input voltge rnge from 5V to 64V, nd smll ripple is still chieved within ±2%.
Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 75 V (2V/div) i L (1A/div) V o (2V/div) t(2μs/div) Fig. 8. Experimentl wveforms of V (upper), i L (middle), nd V o (ottom), when V in 64V nd f c 1kHz. V (2V/div) V o (2V/div) i L (5A/div) t(5μs/div) Fig. 9. Experimentl wveforms of V (upper), V o (middle), nd i L (ottom), t the step lod chnge from 4.6 W to 7 W, when V in 5V nd f c 1kHz. DCM V (2V/div) i L (5A/div) V o (2V/div) t(2μs/div) Fig. 1. DCM experimentl wveforms of V (upper), i L (middle), nd V o (ottom), when V in 5V nd f c 11.36kHz. Efficiency(%) 92 91 9 89 88 3 5 7 9 11 P(W) Fig. 11. Efficiency of the prototype versus output power, V in 5V, nd V o 68V. he output voltges nd current under step lod chnges re shown in Fig. 9. When the lod resistor is 4.6 W, the output dc voltge V o is round 68V, nd the inductor current i L fluctutes from 11A to 19A. At the moment of the step lod chnge (from 4.6 W to 7 W ), V o goes through the trnsient response, nd it is still controlled t round 68V fter out 1ms, due to the voltge controller. At the sme time, the inductor current i L goes down ccordingly, nd then it fluctutes from 6A to 14A in the stedy stte of the conversion system. he trnsient response time cn e reduced further y the improved controller, if the overshoot of the output dc voltge V o nd the input cpcitor voltges trnsient lnce cn e considered s well. In order to verify the usility of the proposed converter for light lod, the discontinuous conduction mode (DCM) experimentl wveforms with nother incresed switching frequency f c 11.36kHz re shown in Fig. 1. he light lod resistor is 45 W. hen the energy stored in the inductor is not enough to supply the lod. At this point i L ecomes zero, nmely it is in DCM. During DCM, the lod is supplied y C f merely, nd V is the voltge V o cross C f, s shown in Fig. 1. However, it is shown tht V o cn still e controlled t round the reference voltge 68V. When the high input dc voltge V in is 5V, nd the low output dc voltge V o is controlled t 68V, the efficiency of the experimentl prototype is mesured with the output power s illustrted in Fig. 11. he mximum efficiency is pproximtely 91.4% under full lod. Although lower locking voltges cross the power switches nd diodes cn reduce the switching losses, the soft-switching mode will improve the efficiency of the proposed converter more thn the present hrd-switching mode. IV. CONCLUSIONS A trnsformerless three-level dc-dc uck converter with high step-down conversion rtio is proposed. Such converter cn operte over wide input voltge rnge for high voltge pplictions with fewer low-voltge-rted power components. It cn lso void extreme duty cycles without trnsformer. he voltges cross the two series cpcitors re self lnced with the proposed modultion strtegy, the locking voltges of the IGBs re hlf the input dc voltge, nd the equivlent frequency of the output pulse voltge is doule the switching frequency. From the experimentl results, it cn e seen tht such dc-dc converter displys good performnce nd hence is suitle for high power converters operting from high-input dc voltge to low-output dc voltge. It would e especilly useful for ship electric power distriution systems. ACKNOWLEDGMEN his work ws supported in prt y the Specil Scientific nd eserch Funds for Doctorl Specility of Chinese Institution of Higher Lerning under Grnt 211321282, nd in prt y the Ntionl Nturl Science Foundtion of Chin under Grnt 512714. EFEENCES [1] H. M. Pirouzy nd M.. Bin, Modulr multilevel converter sed SACOM topology suitle for medium-voltge unlnced systems, Journl of Power Electronics, Vol. 1, No. 5, pp. 572-578, Sep. 21. [2] E. Bei, Optiml topologies for cscded su-multilevel converters, Journl of Power Electronics,
76 Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 Vol. 1, No. 3, pp. 251-261, My 21. [3] F. Iturriz nd P. Ldoux, Phse-controlled multilevel converters sed on dul structure ssocitions, IEEE rns. Power Electron., Vol. 15, No. 1, pp. 92-12, Jn. 2. [4] H. Mohmmdi nd M.. Bin, A trnsformerless medium-voltge SACOM topology sed on extended modulr multilevel converters, IEEE rns. Power Electron., Vol. 26, No. 5, pp. 1534-1545, My 211. [5] M. L. Heldwein, S. A. Muss, nd I. Bri, hree-phse multilevel PWM rectifiers sed on conventionl idirectionl converters, IEEE rns. Power Electron., Vol. 25, No. 3, pp. 545-549, Mr. 21. [6] M. Hgiwr nd H. Akgi, Control nd experiment of pulsewidth-modulted modulr multilevel converters, IEEE rns. Power Electron., Vol. 24, No. 7, pp. 1737-1746, Jul. 29. [7] K. Hsegw nd H. Akgi, A new DC-voltge-lncing circuit including single coupled inductor for five-level diode-clmped PWM inverter, IEEE rns. Ind. Appl., Vol. 47, No. 2, pp. 841-852, Mr./Apr. 211. [8] Y. Zhng nd L. Sun, An efficient control strtegy for five-level inverter comprising flying-cpcitor symmetric h-ridge, IEEE rns. Ind. Electron., Vol. 58, No. 9, pp. 4-49, Sep. 211. [9] Z. Du, L. M. olert, B. Ozpineci, nd J. N. Chisson, Fundmentl frequency switching strtegies of seven-level hyrid cscded H-ridge multilevel inverter, IEEE rns. Power Electron., Vol. 24, No. 1, pp. 25-33, Jn. 29. [1] A. Ne, I. khshi, nd H. Akgi, A new neutrl-point-clmped PWM inverter, IEEE rns. Ind. Appl., Vol. 1A-17, No. 5, pp. 518-523, Sep./Oct. 1981. [11] J.. Pinheiro nd I. Bri, he three-level ZVS PWM converter new concept in high-voltge dc-to-dc conversion, in Conf. ec. IECON, pp. 173-178, 1992. [12] X. un, B. Li, Q. Chen, S. C. n, nd C. K. se, Fundmentl considertions of three-level dc dc converters: topologies, nlyses, nd control, IEEE rns. Circuits Syst. I, eg. Ppers, Vol. 55, No. 11, pp. 3733-3743, Dec. 28. [13] B. Axelrod, Y. Berkovich, nd A. Ioinovici, Switched-cpcitor/switched-inductor structures for getting trnsformerless hyrid dc dc PWM converters, IEEE rns. Circuits Syst. I, eg. Ppers, Vol. 55, No. 2, pp. 687-696, Mr. 28. [14] E. H. Ismil, M. A. Al-Sffr, nd A. J. Szli, High conversion rtio dc dc converters with reduced switch stress, IEEE rns. Circuits Syst. I, eg. Ppers, Vol. 55, No. 7, pp. 2139-2151, Aug. 28. [15] L. Huer nd M. M. Jovnovic, A design pproch for server power supplies for networking pplictions, in Conf. ec. IEEE APEC, pp. 1163-1169, 2. [16] B. M. Song,. McDowell, A. Bushnell, nd J. Ennis, A three-level dc dc converter with wide-input voltge opertions for ship-electric-power-distriution systems, IEEE rns. Plsm Sci., Vol. 32, No. 5, pp. 1856-1863, Oct. 24. [17] V. F. Pires nd J. F. Silv, Single-stge doule-uck topologies with high power fctor, Journl of Power Electronics, Vol. 11, No. 5, pp. 655-661, Sep. 211. Yun Zhng ws orn in Jingsu, Chin, in 198. He received his B.S. nd M.S. in Electricl Engineering from the Hrin University of Science nd echnology, Hrin, Chin, in 23 nd 26, respectively, nd his Ph.D. in Electricl Engineering from the Hrin Institute of echnology, Hrin, Chin, in 21. Since 21 he hs een memer of the teching nd reserch stff in the School of Electricl Engineering nd Automtion, injin University, injin, Chin. His current reserch interests include power conversion systems nd controls, power electronics technique pplied to distriuted genertion systems, nd motor control. Dr. Zhng is Memer of the Chinese Society for Electricl Engineering nd is lso Memer of IEEE. Xing-to Sun ws orn in Heilongjing, Chin, in 1974. He received his B.S. in Electricl Engineering from Wuhn University, Wuhn, Chin, in 1997, nd his M.S. nd Ph.D. in Electricl Engineering from the Hrin Institute of echnology, Hrin, Chin, in 23 nd 29, respectively. He is currently Lecturer in the School of Electricl Engineering nd Automtion, injin Polytechnic University, injin, Chin. His current reserch interests include multilevel power conversion nd motor control. Yi-feng Wng ws orn in Huei, Chin, in 1981. He received his B.S., M.S. nd Ph.D. ll in Electricl Engineering from the Hrin Institute of echnology, Hrin, Chin, in 25, 27 nd 211, respectively. He is currently Lecturer in the School of Electricl Engineering nd Automtion, injin University, injin, Chin. His current reserch interests include grid connected inverters pplied in renewle energy systems, specil power supplies, nd electronic lighting. Hong-jun Sho ws orn in Lioning, Chin, in 1983. She received her B.S. from injin Polytechnic University, injin, Chin, in 25 nd her M.S. from injin University, injin, Chin, in 29, respectively, ll in Electricl Engineering. She is currently working towrds her Ph.D. in Electricl Engineering in the School of Electricl Engineering nd Automtion, injin University, injin, Chin. Her current reserch interests include multilevel power conversion nd motor control.