TVS (transient voltage suppressor) Bi-directional, 5.5 V, 3.5 pf, 21, RoHS and halogen free compliant Features ESD/transient protection of susceptible I/O lines to: - IEC61-4-2 (ESD): ±3 kv (air/contact discharge) - IEC61-4-4 (EFT): ±4 kv/±8 A (5/5 ns) - IEC61-4-5 (Surge): ±12 A (8/2 μs) Bi-directional working voltage up to: V RWM = ±5.5 V Line capacitance: C L = 3.5 pf (typical) at f = 1 MHz Clamping voltage: V CL = 12 V (typical) at I TLP = 16 A with R DYN =.3 Ω (typical) Very low reverse current: I R < 1 na (typical) Small form factor SMD size 21 and low profile (.58 mm x.28 mm x.15 mm); for further package information please refer to application note AN392 [4] Bi-directional and symmetric I/V characteristics for optimized design/assembly Potential applications USB 2. HA, MIPI, (μ)sd card (UHS), SIM card Control ports for DVI, HDMI, display port and Thunderbolt Audio line, speaker, headset, microphone protection, human interface devices (keyboard, touchpad,...) Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/2/22 Device information a ) Pin configuration b ) Schematic diagram Figure 1 Table 1 Pin configuration and schematic diagram Part information Type Package Configuration Marking code ESD231-B1-W21 WLL-2-1 1 line, bi-directional M 1) 1 The device has no marking or date code on the device backside. The marking code is on pad side. Datasheet Please read the Important Notice and Warnings at the end of this document Revision 1.2 www.infineon.com
Table of contents Table of contents Features............................................................................... 1 Potential applications.................................................................. 1 Product validation......................................................................1 Device information..................................................................... 1 Table of contents....................................................................... 2 1 Maximum ratings....................................................................... 3 2 Electrical characteristics................................................................ 4 3 Typical characteristic diagrams......................................................... 6 4 Package information.................................................................. 12 4.1 WLL-2-1 package....................................................................... 12 5 References............................................................................ 13 Revision history....................................................................... 13 Disclaimer............................................................................ 14 Datasheet 2 Revision 1.2
Maximum ratings 1 Maximum ratings Note: T A = 25 C, unless otherwise specified. Table 2 Maximum ratings Parameter Symbol Values Unit Note or test condition Reverse working voltage V RWM ±5.5 V ESD (air/contact) discharge 1) V ESD ±3 kv Peak pulse power 2) P PK 132 W Peak pulse current 2) I PP 12 A Operating temperature range T OP -55 to 125 C Storage temperature T stg -65 to 15 C Attention: Stresses above the maximum values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings. Exceeding only one of these values may cause irreversible damage to the component. Table 3 Thermal resistance Parameter Symbol Values Unit Note or test condition Min. Typ. Max. Junction - soldering point 3) R thjs 3 K/W 1 V ESD according to IEC61-4-2 (R = 33 Ω, C = 15 pf discharge network) 2 Stress pulse: 8/2 μs current waveform according to IEC61-4-5 3 For calculation of R thja please refer to application note AN77 [3], thermal resistance calculation Datasheet 3 Revision 1.2
Electrical characteristics 2 Electrical characteristics Note: T A = 25 C, unless otherwise specified. Device is electrically symmetrical. IF I PP VF... Forward voltage IF... Forward current VR... Reverse voltage IR... Reverse current I TLP R DYN ΔV ΔI ΔI ΔV VR V CL V TLP V t1 ΔV V h ΔI V RWM R DYN I R ΔV ΔI I T I R I T I PP I TLP V RWM V h V t1 V CL V TLP VF RDYN... Dynamic resistance VRWM... Reverse working voltage max. Vt1... Trigger voltage Vh... Holding voltage VCL... Clamping voltage VTLP... TLP voltage IR... Reverse leakage current Ipp... Peak pulse current ITLP... TLP current IT... Test current Figure 2 Definitions of electrical characteristics IR Diode_Characteristic_Curve_with_snapback_Bi-directional.svg Datasheet 4 Revision 1.2
Electrical characteristics Table 4 DC characteristics Parameter Symbol Values Unit Note or test condition Min. Typ. Max. Reverse current I R 2 na V R = 5.5 V Trigger voltage V t1 6.1 9.5 V Holding voltage V h 6.1 7.8 12.5 V I R = 1 ma Table 5 AC characteristics Parameter Symbol Values Unit Note or test condition Min. Typ. Max. Line capacitance C L 3 3.5 4.1 pf V R = V, f = 1 MHz 3.2 V R = V, f = 1 GHz Table 6 ESD and Surge characteristics Parameter Symbol Values Unit Note or test condition Min. Typ. Max. Clamping voltage 1) V CL 12 V I TLP = 16 A, t p = 1 ns 16 I TLP = 3 A, t p = 1 ns Clamping voltage 2) 8 I PP = 2 A, t p = 8/2 µs 1 I PP = 9 A, t p = 8/2 µs Dynamic resistance 1) R DYN.3 Ω t p = 1 ns 1 Please refer to application note AN21 [1], TLP parameters: Z = 5 Ω, t p = 1 ns, t r =.6 ns 2 Stress pulse: 8/2 μs current waveform according to IEC61-4-5 Datasheet 5 Revision 1.2
Typical characteristic diagrams 3 Typical characteristic diagrams Note: T A = 25 C, unless otherwise specified. 1-6 1-7 1-8 I R [A] 1-9 1-1 1-11 1-12 1-13 -5-4 -3-2 -1 1 2 3 4 5 V R [V] Figure 3 Reverse leakage current: I R = f(v R ) 4 3.8 3.6 C L [pf] 3.4 3.2 1 MHz 3 2.8 2.6 1 GHz -5-4 -3-2 -1 1 2 3 4 5 V R [V] Figure 4 Line capacitance: C L = f(v R ) Datasheet 6 Revision 1.2
Typical characteristic diagrams 45 Scope: 6 GHz, 2 GS/s 3 V CL [V] 15 V CL-max-peak = 31 V V CL-3ns-peak = 1 V -15-5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 5 Clamping voltage (ESD): V CL = f(t), 8 kv positive pulse (according to IEC61-4-2) 15 Scope: 6 GHz, 2 GS/s V CL [V] -15 V CL-max-peak = -31 V -3 V CL-3ns-peak = -9 V -45-5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 6 Clamping voltage (ESD): V CL = f(t), 8 kv negative pulse (according to IEC61-4-2) Datasheet 7 Revision 1.2
Typical characteristic diagrams 6 Scope: 6 GHz, 2 GS/s 45 V CL [V] 3 15 V CL-max-peak = 47 V V CL-3ns-peak = 13 V -15-5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 7 Clamping voltage (ESD): V CL = f(t), 15 kv positive pulse (according to IEC61-4-2) 15 Scope: 6 GHz, 2 GS/s V CL [V] -15-3 V CL-max-peak = -47 V -45 V CL-3ns-peak = -12 V -6-5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 8 Clamping voltage (ESD): V CL = f(t), 15 kv negative pulse (according to IEC61-4-2) Datasheet 8 Revision 1.2
Typical characteristic diagrams 7 6 ESD231-B1-W21 R DYN 35 3 5 4 R DYN =.3 Ω 25 2 3 15 2 1 I TLP [A] 1-1 5-5 Equivalent V IEC [kv] -2-1 -3-15 -4-5 R DYN =.3 Ω -2-25 -6-3 -7-35 -3-25 -2-15 -1-5 5 1 15 2 25 3 V TLP [V] Figure 9 Clamping voltage (TLP): I TLP = f(v TLP ) [1] Datasheet 9 Revision 1.2
Typical characteristic diagrams 14 12 1 8 6 4 2 I PP [A] -2-4 -6-8 -1-12 -14-12 -1-8 -6-4 -2 2 4 6 8 1 12 V CL [V] Figure 1 Clamping voltage (Surge): I PP = f(v CL ) (according to IEC61-4-5) [1] Datasheet 1 Revision 1.2
Typical characteristic diagrams -1 Insertion Loss [db] -2-3 -4-5 Figure 11-6.1 1 1 f [GHz] Insertion loss vs. frequency in a 5 Ω system Datasheet 11 Revision 1.2
Package information 4 Package information 4.1 WLL-2-1 package Note: Dimensions in mm. Top view Bottom view.15±.1.28±.3 2.36 (.16) 1.58 ±.3.26±.2.2 ±.2 SG-WLL-2-1-PO V1 Figure 12 WLL-2-1 package outline.32.27.24.19.19.19.62.57.24.14 Copper Solder mask Stencil apertures SG-WLL-2-1-FP V1 Figure 13 WLL-2-1 footprint (recommendation for printed circuit board assembly see [2]).23.68 8 2.35.21 SG-WLL-2-1-TP V2 Figure 14 WLL-2-1 packing Marking on pad-side Type code Type code 1 2 1 1 1 2 Figure 15 WLL-2-1 marking example (see Device information) Datasheet 12 Revision 1.2
References 5 References [1] Infineon AG - Application note AN21: Effective ESD protection design at system level using VF-TLP characterization methodology [2] Infineon AG - Recommendation for Printed Circuit Board Assembly of Infineon WLL Packages http://www.infineon.com/packageinformation_wll [3] Infineon AG - Application note AN77: Thermal resistance calculation [4] Infineon AG - Application note AN392: TVS diodes in ChipScalePackage reduce size and save cost Revision history Revision history: Rev. 1.1, 215-1-2 Page or Item Subjects (major changes since previous revision) Revision 1.2, All Data sheet layout changed, references updated Datasheet 13 Revision 1.2
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