CITIROC ASIC TIPP 2014, Amsterdam 4 June 2014 Salleh AHMAD Christophe DE LA TAILLE a, Julien FLEURY b, Nathalie SEGUIN- MOREAU a,ludovic RAUX a, Stéphane CALLIER a, Gisele MARTIN CHASSARD a a OMEGA/IN2P3/Ecole Polytechnique b Weeroc SAS
Weeroc and Omega Weeroc is a spin- off company from OMEGA lab CEO: Julien Fleury Weeroc addresses industrial needs for microelectronics in Aerospace, Medical imaging, ScienWfic instrumentawon, Homeland security, Nuclear industry Weeroc and OMEGA (13 microelectronics engineers) provide : off- the- shelf FE ASIC (the ROC chip family) customer- specific ASICs Services, Audit, ExperWse OMEGA : formerly a microelectronics group of LAL ORSAY, became an independent lab (IN2P3/CNRS/Ecole Polytechnique) in June 2013. Located in Palaiseau, directed by Christophe de La Taille Research InsWtute Industry company Weeroc : www.weeroc.com OMEGA: omega.in2p3.fr EducaWon University 2
SPIROC Presenta5on courtesy of N. Seguin- Moreau, OMEGA/IN2P3 3
SPIROC2 PERFORMANCE Presenta5on courtesy of N. Seguin- Moreau, OMEGA/IN2P3 4
From EASIROC to CITIROC EASIROC was developed around 2010 by OMEGA Based on SPIROC chips family (c.f. poster *) Used in many experiments 32- channel SiPM readout ASIC: 8- bits Input DAC for each channel Trigger outputs MulWplexed charge output Power consumpwon : 4.84 mw/channel EASIROC - > CITIROC: Pin- to- pin compawble Becer input DACs Peak sensing for CTA Industry transfer to Weeroc * L. Raux - Performances of 2 nd generawon CALICE ASICs 5
Experiments using EASIROC PEBS RTWH Aachen J- PARC Tohoku University & KEK MU- RAY INFN Napoli SIPMED IMNC Orsay 6
CITIROC descripwon Cherenkov Imaging Telescope Integrated Read Out Chip General ASIC for SiPM readout 32- channel readout, charge and trigger outputs (No ADC/TDC) Power pulsing Individual stage can be turned on or off for various config EvoluWon of EASIROC ASIC (OMEGA) for CTA experiment Power consumpwon : 6.26 mw/channel Front- end Trigger Fast shaper connected to either low or high gain preamp Two discriminators : one for Wming, one for event validawon on energy Energy measurement 2 voltage pre- amplifiers (10x gain difference) followed by shaper Analog memory : track and hold or peak detector Analog output mulwplexer 7
CITIROC Architecture 8
Input DAC measurements +HV Si PM High voltage on the cable shielding 8-bit DAC ASIC ~ 5V swing for SiPM overvoltage adjustment DAC uniformity between 32 channels~1% 8- bit : LSB ~17 mv Less non- uniformity compared to EASIROC Improvement by a factor of 3 due to complete redesign of the input DAC, with same power consumpwon Allows to compensate non- uniformity between channels by finely adjuswng channel by channel gain (SiPM bias Voltage). 9 Allows tuning of the applied voltage on the SiPM power line.
Trigger Linearity Trigger linearity < ± 0.3% Input charges: 1-30 p.e Threshold DAC : 10 bits on 2.25V reference => 2.2 mv LSB Trigger jicer : 60ps for Wming trigger 70ps for validawon trigger *Measurements courtesy of O. Catalano, INAF- Palermo & CTA collaborawon 10
Sampling vs Peak detector 2200 2000 PD 1800 ADC Unit 1600 SCA 1400 1200 1000 Sampling with 2.5 ns step 0 10 20 30 40 50 60 x 2.5 ns Same pulse measured in SCA and PD mode as a func5on of delayed HOLD *Measurements courtesy of O. Catalano, INAF- Palermo & CTA collaborawon 11
High Gain Shaper linearity Peak detector With preamp gain sesng HG dynamic range is linear up to 60 pe with residuals of the order of ± 0.3%. Linearity measurement includes the en1re channel chain: pulse generator + a7enuator + Ci1roc + ADC *Measurements courtesy of O. Catalano, INAF- Palermo & CTA collaborawon 12
Low Gain Shaper linearity Peak detector With preamp gain sesng LG dynamic range is linear up to 2000 pe with residuals of the order of ± 1%. Linearity measurement includes the whole channel chain: pulse generator + a7enuator + Ci1roc + ADC *Measurements courtesy of O. Catalano, INAF- Palermo & CTA collaborawon 13
SiPM Spectrum with CITIROC Gain preamplifier =4*25fF 150 nom. Shaping Time = 50ns Steps of 1,2,3,4,5,6,7,8,9,10 pe SiPM 4 pixel High Gain =150 Shaping Time = 50ns delay 5me = 38 x 2.5 ns Temp = 23.7 C U over = 1V Resistance = 50 Ohm Threshold = 922 DAC ~50% of 1 plateau *Measurements courtesy of O. Catalano, INAF- Palermo & CTA collaborawon 14
CTA SST PDM electronics ASSEMBLING SiPM board (9 +1 temperature sensors embedded) FOV = 9.6 Ø = 350mm Front- End board (2 CITIROC ASIC) PDM FPGA Board (XILINX ARTIX 7) Photon Detec5on Module (PDM) Pixel = 0.17! 6.2 x 6.2 mm Images courtesy of INAF- Palermo & CTA collaborawon 15
Conclusion & Status Experiment : CTA PDM Assembly CITIROC working properly and currently under tests Mature design Input DAC for HV tuning is working fine Good linearity of HG and LG shapers Excellent trigger linearity ASICs will be available in TFBGA packaging 16