TrilithIC BTS 7700 G Data Sheet Overview. Features Quad D-MOS switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications ow R DS ON : 0 mω high-side switch, 90 mω lowside switch (typical values @ 25 C) Maximum peak current: typ. 9 A @ 25 C= Very low quiescent current: typ. 5 µa @ 25 C= Small outline, enhanced power P-DSO-package oad and GND-short-circuit-protection Operates up to 40 V Status flag diagnosis Overtemperature shut down with hysteresis Internal clamp diodes Isolated sources for external current sensing Under-voltage detection with hysteresis PWM frequencies up to 50 khz P-DSO-28-4 Type Ordering Code Package BTS 7700 G Q67007-A9375 P-DSO-28-4.2 Description The BTS 7700 G is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated leadframes. The sources are connected to individual pins, so the BTS 7700 G can be used in H-bridge- as well as in any other configuration. The double high-side is manufactured in SMART SIPMOS technology which combines low R DS ON vertical DMOS power stages with CMOS control circuitry. The high-side switch is fully protected and contains the control and diagnosis circuitry. To achieve low R DS ON and fast switching performance, the low-side switches are manufactured in S-FET logic level technology. The equivalent standard product is the BUZ 04 S. In contrast to the BTS 770 G, which consists of lower ohmic chips in the same package, the BTS 7700 G offers a lower price for applications, which do not need the high current capability of the BTS 770 G or BTS 770 GP. Data Sheet 200-02-0
.3 Pin Configuration (top view) D 28 D I 2 27 S D N.C. 3 4 S-eadframe 26 S 25 D DHVS 5 24 DHVS GND 6 23 SH IH ST 7 8 HS-eadframe 22 SH 2 SH2 IH2 9 20 SH2 DHVS 0 9 DHVS N.C. D2 2 S-eadframe 8 D2 7 S2 I2 3 6 S2 D2 4 5 D2 Figure Data Sheet 2 200-02-0
.4 Pin Definitions and Functions Pin No. Symbol Function, 3, 25, 28 D Drain of low-side switch, leadframe ) 2 I Analog input of low-side switch 4 N.C. not connected 5, 0, 9, 24 DHVS Drain of high-side switches and power supply voltage, leadframe 2 ) 6 GND Ground 7 IH Digital input of high-side switch 8 ST Status of high-side switches; open Drain output 9 IH2 Digital input of high-side switch2 N.C. not connected 2, 4, 5, 8 D2 Drain of low-side switch2, leadframe 3 ) 3 I2 Analog input of low-side switch2 6,7 S2 Source of low-side switch2 20,2 SH2 Source of high-side switch2 22,23 SH Source of high-side switch 26,27 S Source of low-side switch ) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe. Pins written in bold type need power wiring. Data Sheet 3 200-02-0
.5 Functional Block Diagram DHVS 5,0,9,24 ST 8 Diagnosis Biasing and Protection IH IH2 7 9 Driver IN OUT 0 0 0 H 0 H H H R O R O2 20,2 2,4,5,8 SH2 D2 GND 6 22, 23 SH,3,25,28 D I 2 I2 3 26, 27 6, 7 S S2 Figure 2 Block Diagram Data Sheet 4 200-02-0
.6 Circuit Description Input Circuit The control inputs IH,2 consist of TT/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes. The inputs I and I2 are connected to the gates of the standard N-channel vertical power-mos-fets. Output Stages The output stages consist of an low R DS ON Power-MOS H-bridge. In H-bridge configuration, the D-MOS body diodes can be used for freewheeling when commutating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes. Short Circuit Protection The outputs are protected against output short circuit to ground overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-Voltage- Drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. Overtemperature Protection The high-side switches incorporate an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low. Undervoltage-ockout (UVO) When V S reaches the switch-on voltage V UVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage V S drops below the switch off value V UVOFF. Data Sheet 5 200-02-0
Status Flag The status flag output is an open drain output with Zener-diode which requires a pull-up resistor, c.f. the application circuit on page 4. Various errors as listed in the table Diagnosis are detected by switching the open drain output ST to low. A open load detection is not available. Freewheeling condition does not cause an error. 2 Truthtable and Diagnosis (valid only for the High-Side-Switches) Flag IH IH2 SH SH2 ST Remarks Inputs Outputs Normal operation; identical with functional truth table Overtemperature high-side switch 0 Overtemperature high-side switch2 Overtemperature both high-side switches 0 0 0 0 0 0 0 H H H H stand-by mode switch2 active switch active both switches active 0 detected 0 detected 0 0 detected detected Undervoltage not detected Inputs: Outputs: Status: 0 = ogic OW Z = Output in tristate condition = No error = ogic HIGH = Output in sink condition 0 = Error = don t care H = Output in source condition = Voltage level undefined Data Sheet 6 200-02-0
3 Electrical Characteristics 3. Absolute Maximum Ratings 40 C < T j < 50 C Parameter Symbol imit Values Unit Remarks min. max. High-Side-Switches (Pins DHVS, IH,2 and SH,2) Supply voltage V S 0.3 42 V Supply voltage for full short V S(SCP) 28 V circuit protection HS-drain current* I S 7 ** A T A = 25 C; t < 00 ms HS-input current I IH 5 5 ma Pin IH and IH2 HS-input voltage V IH 0 6 V Pin IH and IH2 Note: * single pulse ** internally limited Status Output ST Status pull up voltage V ST 0.3 5.4 V Status Output current I ST 5 5 ma Pin ST ow-side-switches (Pins D,2, I,2 and S,2) Drain- source break down V DS 55 V V I =0V; I D ma voltage S-drain current* I D 7 6 A t < 00 ms T A = 25 C 8 A t < 0 ms 8 A t < ms S-input voltage V I 20 20 V Pin I and I2 Note: * single pulse Temperatures Junction temperature T j 40 50 C Storage temperature T stg 55 50 C Data Sheet 7 200-02-0
3. Absolute Maximum Ratings (cont d) 40 C < T j < 50 C Parameter Symbol imit Values Unit Remarks min. max. Thermal Resistances (one HS-S-Path active) S-junction case R thjc 20 K/W measured to pin 3 or 2 HS-junction case R thjc H 20 K/W measured to pin 9 Junction ambient R thja = T j(hs) /(P (HS) +P (S) ) R thja 60 K/W device soldered to reference PCB with 6cm 2 cooling area ESD Protection (Human Body Model acc. MI STD 883D, method 305.7 and EOS/ ESD assn. standard S5. - 993) Input S-Switch V ESD 0.5 kv Input HS-Switch V ESD kv Status HS-Switch V ESD 2 kv Output S and HS-Switch V ESD 8 kv all other pins connected to Ground Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.2 Operating Range 40 C < T j < 50 C Parameter Symbol imit Values Unit Remarks min. max. Supply voltage V S V UVOFF 42 V After V S rising above V UVON Input voltages HS V IH 0.3 5 V Input voltages S V I 0.3 20 V Output current I ST 0 2 ma Junction temperature T j 40 50 C Note: In the operating range the functions given in the circuit description are fulfilled. Data Sheet 8 200-02-0
3.3 Electrical Characteristics I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Current Consumption HS-switch Quiescent current I S 5 8 µa IH = IH2 = 0 V T j = 25 C 2 µa IH = IH2 = 0 V Supply current I S 2 ma IH or IH2 = 5 V V S = 2 V 2 4 ma IH and IH2 = 5 V V S = 2 V eakage current of highside switch I SH K 6 µa V IH = V SH = 0 V eakage current through logic GND in free wheeling condition I KC = 0 ma I FH = 3 A I FH + I SH Current Consumption S-switch Input current I I 0 00 na V I = 20 V; V DS = 0 V T j = 25 C eakage current of lowside switch I D K 0 µa V I = 0 V V DS = 40 V Under Voltage ockout (UVO) HS-switch Switch-ON voltage V UVON 4.5 V V S increasing Switch-OFF voltage V UVOFF.8 3.2 V V S decreasing Switch ON/OFF hysteresis V UVHY V V UVON V UVOFF Data Sheet 9 200-02-0
3.3 Electrical Characteristics (cont d) I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Output stages Inverse diode of high-side switch; Forward-voltage Inverse diode of lowside switch; Forward-voltage Static drain-source on-resistance of highside switch Static drain-source on-resistance of lowside switch V FH 0.8.2 V I FH = 3A V F 0.8.2 V I F = 3 A R DS ON H 0 40 mω I SH =A T j = 25 C R DS ON 80 0 mω I S =A; V I = 5 V T j = 25 C Static path on-resistance R DS ON 480 mω R DS ON H +R DS ON I SH =A; Short Circuit of highside switch to GND Initial peak SC current I SCP H 9 3 A T j = 40 C Initial peak SC current I SCP H 7.5 9 A T j = + 25 C Initial peak SC current I SCP H 5.5 7 9 A T j = + 50 C Short Circuit of highside switch to V S Output pull-down-resistor R O 2 22 50 kω V DS = 3 V Thermal Shutdown Thermal shutdown junction temperature Thermal switch-on junction temperature T j SD 55 80 90 C T j SO 50 70 80 C Temperature hysteresis T 0 C T = T jsd T jso Data Sheet 0 200-02-0
3.3 Electrical Characteristics (cont d) I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Status Flag Output ST of highside switch ow output voltage V ST 0.2 0.6 V I ST =.6 ma eakage current I ST K 0 µa V ST = 5 V Zener-limit-voltage V ST Z 5.4 V I ST =.6 ma Switching times of highside switch Turn-ON-time; to 90% V SH t ON 75 60 µs R oad = 2 Ω V S = 2 V Turn-OFF-time; to 0% V SH t OFF 60 60 µs R oad = 2 Ω V S = 2 V Slew rate on 0 to 30% V SH dv/dt ON.7 V/µs R oad = 2 Ω V S = 2 V Slew rate off 70 to 40% V SH -dv/ dt OFF 2.5 V/µs R oad = 2 Ω V S = 2 V Note: switching times are guaranteed by design Switching times of low-side switch Turn-ON delay time; V I = 5V; R G = 6Ω Switch-ON time; V I = 5V; R G = 6Ω Switch-OFF delay time; V I = 5V; R G = 6Ω Switch-OFF time; V I = 5V; R G = 6Ω t d_on_ 7 ns resistive load I S = 3 A; V S = 30 V t ON_ 28 45 ns resistive load I S = 3 A; V S = 30 V t d_off_ 23 35 ns resistive load I S = 3 A; V S = 30 V t OFF_ 8 28 ns resistive load I S = 3 A; V S = 30 V Data Sheet 200-02-0
3.3 Electrical Characteristics (cont d) I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Gate charge of lowside switch Input to source charge; Q IS.5 2.3 nc I S = 3 A; V S = 4 V Input to drain charge; Q ID 5 7 nc I S = 3 A; V S = 4 V Input charge total; Q I 7 nc I S = 3 A; V S = 4 V V I = 0 to 0 V Input plateau voltage; V (plateau) 3. - V I S = 3 A; V S = 4 V Note: switching times and input charges are guaranteed by design Control Inputs of highside switches IH, 2 H-input voltage V IH High 2.5 V -input voltage V IH ow V Input voltage hysterese V IH HY 0.3 V H-input current I IH High 5 30 60 µa V GH = 5 V -input current I IH ow 5 20 µa V GH = 0.4 V Input series resistance R I 2.7 4 5.5 kω Zener limit voltage V IH Z 5.4 V I GH =.6 ma Control Inputs I, 2 Gate-threshold-voltage V I th 0.9.7 2.2 V I D = 0.5 ma Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25 C and the given supply voltage. Data Sheet 2 200-02-0
V S =2V I S C S 470nF C 00µF I FH,2 DHVS I ST K 5,0,9,24 I ST ST 8 V DSH2 V DSH -V FH2 -V FH Diagnosis Biasing and Protection V ST V ST I IH IH 7 Gate Driver V STZ V IH I IH IH2 9 Gate Driver R O R O2 20,2 2,4,5,8 SH2 D2 I SH2 I D2 V IH2 GND 6 I D K 2 V UVON I GND 22,23 SH I SH V UVOFF I KC,3,25,28 D I D I D K I I I 2 V I I I2 I2 3 V I th V I2 26,27 6,7 V DS V DS2 V I th 2 S S2 -V F -V F2 I SCP I SCP 2 I S I S2 Figure 3 Test Circuit HS-Source-Current Named during Short Circuit Named during eakage- Cond. I SH,2 I SCP H I D K Data Sheet 3 200-02-0
Watchdog Reset Q TE 4278G I V S =2V R Q 00 kω C Q 22µF D C D 47nF D0 Z39 C S 0µF WD R V CC DHVS 5,0,9,24 R S ST 8 0 kω Diagnosis Biasing and Protection IH 7 Gate Driver IH2 9 Gate Driver R O R O2 20,2 2,4,5,8 SH2 D2 µp GND 6 22,23 SH M,3,25,28 D I 2 I2 3 26,27 6,7 GND S S2 Figure 4 Application Circuit Data Sheet 4 200-02-0
4 Package Outlines P-DSO-28-4 (Plastic Transistor Single Outline Package) -0. 0.2 2.45-0.2 2.65 max 7.6 0.35 x 45 ) -0.2 0.23 +0.09 8 max.27 0.4 +0.8 +0.5 2) 0.35 0.2 28x 0. 0.3 ±0.3 28 5 Index Marking 4 ) 8. -0.4 ) Does not include plastic or metal protrusions of 0.5 max rer side 2) Does not include dambar protrusion of 0.05 max per side GPS0523 GPS0523 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information. SMD = Surface Mounted Device Dimensions in mm Data Sheet 5 200-02-0
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