International Journal of Electronics, Electrical and omputational System IJEES May 26 Design and Implementation of 3-Phase 3-Level T-type Inverter with Different PWM Techniques Amit Singh Jadon Department of Electrical Engineering Madhav Institute of Technology & Science Gwalior, India Praveen Bansal Department of Electrical Engineering Madhav Institute of Technology & Science Gwalior, India Dr. Anmol atna Saxena Department of Electrical & Electronics Engineering National Institute of Technology Delhi, India Abstract Multi-level inverter has a capability to handled high power with less total harmonic distortion (THD), reduced switching losses and good power quality due to which in recent year they become more popular in high power application, with Increase in the voltage level, harmonic content in output voltage waveform will decrease. Diode lamped Multilevel Inverter (DMLI) has a capability to increase the output voltage and performance with low switching losses, reduced voltage stress and total harmonic distortion. However, it suffers from problems of high conduction losses. T-type is used to overcome the drawbacks of DMLI, but the high side and low side power devices of T-type inverter need to block the whole dc link voltage. The switching frequency is limited due to the high switching losses caused by the high voltage rated power devices. Generally, it is used for both low conduction losses and switching losses with high switching frequency. Simulation result of 3-phase 3-level T-type multi-level inverter can be obtained by MATLAB/ SIMULINK software multi-level inverter using different PWM technique. Keywords- Multi-level inverter(mli); DMLI; T-type inverter; SPWM and ISPWM techniques. I. INTODUTION An inverter is used to convert dc to ac power at a desired ac voltage. But a multilevel inverter can generate a stair-case voltage waveform with less distortion, less switching frequency and higher efficiency. While conventional inverter having two voltage level is commonly used for domestic and commercial applications, since its configuration is simple and the reliability is better. However, there is a some limitations in high power and performance due to two level inverter output voltage is depend on Vdc. The basic idea of MLI is that the dc link voltage can be split between different power switches, which can provide intermediate voltage levels between the reference potential and the dc link voltage. Multilevel inverter provides many advantages over two-level inverter, it increase the output voltage waveform, reduced EMI and (dv/dt) voltage stress on the load, lower switching frequency and low rating devices for high power rating, but the copper loss, torque ripple and higher number of semiconductor switches are increased because of low frequency harmonics. Every switch requires a separate gate driver circuit, therefore increasing the complexity and size of the overall circuit. The SPWM strategy is commonly used to solve the harmonic problem of this six-step method in many applications. The switching loss is more prominent when the switching frequency is increased and the D link voltage becomes higher. Therefore a three-level inverter is being researched in various applications for further improvement of energy efficiency, reliability, power and density. The multilevel inverter topology such as the three-level inverter has been developed for both medium and high voltage level. Among various conventional multilevel inverter are categorized as Diode lamped Multilevel Inverter (DMLI) [], Flying apacitor multilevel inverter (FMLI) [2] and ascaded H-bridge multilevel inverter (HBMLI) [3] have been widely used. In 98 Nabae introduced a three level diode clamped inverter schemes.[4-5] research on the conventional DMLI applied in the renewable energy system. The clamping diodes in [4-5] are replaced by the IGBTs to reach active clamping in [6] to improve the semiconductor loss distribution[7] proposes a novel high efficiency stacked neutral point clamped 3L-NP inverter[8] proposes an active clamped 3L-SNP to improve the 3L-SNP s structure and control strategy are improved the 3L-SNP s efficiency[9] the 3L-SNP s structure and control strategy are improved to reduce the power loss, specifically in the low power range. The DMLI having the switching loss in each switch is 5 Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
International Journal of Electronics, Electrical and omputational System IJEES May 26 half and the conduction losses become double of the counterpart of the two-level inverter due to the two switch series connection. This paper proposes a 3-level T-type inverter topology which requires less number of switches and gate driver circuits as compared to conventional multilevel inverters. The T-type topology that was previously proposed here is implemented in three-phase with different PWM techniques. The pulse-width modulation (PWM) control is the most efficient method of controlling output voltage within the inverters. The carrier based PWM schemes used for multilevel inverters is the most efficient method, realized by the intersection of a modulating signal with triangular carrier waveform. The paper tries to prove that 3LTI is better than conventional multilevel inverters in terms of their number of components and THD. Even though the 3LTI is generally implemented and investigated to apply in low-voltage applications, it has difficulties to apply in low-voltage and low-power domestic appliances because the increased efficiency is not sufficient due to its complexity and cost problem.. First of all, the long current paths imply the high conduction loss. Second, higher stray inductance due to the long current paths results in higher power loss and turn-off overvoltage. To overcome these characteristics in the multi-level topology, the 3-Level T-type inverter (3LTI ) has been proposed for the high efficiency and performance in low-voltage applications. II. T-TYPE MULTILEVEL INVETE The basic topology of the 3-Level T-type is depicted in Fig. 2. [].The conventional two-level VSI topology is extended with an active, bidirectional switch to the dc-link midpoint. For low-voltage applications, the high side and the low-side power switches (T and T4 ) would usually be implemented with IGBTs as the full dc-link voltage has to be blocked. The block dc link voltage is twice of the DMLI inverter. When both IGBTs connected in series turn off at the same time. This undesirable effect cannot occur in the T-type topology. A 3-Phase 3-Level T-type inverter is implement low-level routines which prevent such transitions or ensure a transient voltage balancing among series connected IGBTs. [] applies 3L T-type in the solar system to avoid the high conduction loss. ascaded multilevel inverter reaches higher reliability. The cascaded inverter is used for large automotive electric drives. However, the requirement of more number of switches and separate dc source for each cell becomes a problem especially at higher level. The pulse-width modulation (PWM) control is the most efficient method of controlling output voltage within the inverters.the carrier based PWM schemes used for multilevel inverters is the most efficient method, realized by the intersection of a modulating signal with triangular carrier waveform. The paper tries to prove that optimization method is better than conventional multilevel inverters in terms of their number of components and THD. First of all, the long current paths imply the high conduction loss. Second, higher stray inductance due to the long current paths results in higher power loss and turn-off overvoltage. It should be mentioned that the foregoing discussed drawbacks of DMLI seem more prominent in renewable energy system because they are usually operating in much lower power range than the rated power T2 T3 T T5 T9 D T6 T T7 T Y B L O A D T4 T8 T2 6 Figure 2.: 3-Phase 3-Level T-type Inverter model using NP topology Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
International Journal of Electronics, Electrical and omputational System IJEES May 26 T D Vdc T2 D2 T3 D3 LOAD T4 D4 Figure. 2.2: One Leg of 3-Phase 3-level T-type Inverter. (T2 and T3 are Bi-Directional Switches). There are basically two ways; the two IGBTs can be configured to form a bidirectional switch, either in common emitter configuration or common collector configuration. The common emitter configuration as in Fig. 2. (T2 and T3) would require one additional isolated gate drive supply voltage for each bridge leg, summing up to three additional gate drive supplies compared to the two-level VS topology. T shares now a common emitter with the high-side switch T and can supplied with the isolated gate drive voltage of T and can be supplied with the isolated gate drive voltage of T. The emitter of the second IGBT is connected to the midpoint voltage level. If the 3-phase topology is considered, all three IGBTs share a common emitter, and therefore only one isolated gate drive supply is necessary. In total, the complete T-type topology can be implemented with only one additional isolated gate drive supply compared to the two-level topology. III. MODES & OPETAION T D Vdc T2 D2 T3 D3 T4 D4 LOAD Mode I Fig. (a). Level (+Vdc/2 volt) T2 T3 T D Vdc D2 D3 T4 D4 LOAD Mode II Fig. (b). Level ( volt) 7 Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
International Journal of Electronics, Electrical and omputational System IJEES May 26 Vdc T2 D2 T3 D3 T D LOAD T4 D4 Mode III Fig. (c). Level -(-Vdc/2 volt) Fig. 3: Fig. (a), Fig. (b) and Fig. (c) are Switching combination of One Leg of 3_Phase 3-level T-type Inverter. Generation of Level TABLE-I (SWITHING TABLE) Switching Devices T T2 T3 T4 +Vdc/2 on off On off +v off on On off v -Vdc/2 off on Off on -v Output Voltage The necessary power rating of the isolated gate drive supply of the high-side switch T is not increased if the gate charges of the IGBT are approximately equal. Because of the implemented commutation and modulation strategy T and T2 are newer switched both in the same modulation cycle.operation of the one leg of 3-Phase 3-level T-type inverter with can be easily explained with the help of Fig. 3 and table I. When switches T and T3 are turned on the output voltage will be +Vdc/2 (i.e., level ). When switches T2 and T3 are turned on the output voltage is zero (i.e., level ). When Switches T2 and T4 are turned on the output voltage will be -Vdc/2 (i.e., level -). The operation of this topology can also be easily understood by mode of operation of Single-phase 3-level T- type NP shown in Fig.3. The voltage source Vdc is required V. There are three sufficient switching modes in generating the multistep level for a 3-level T-type inverter. IV. MODULATION TEHNIQUES There are different pulse width modulation strategies with different phase relationships; Phase disposition pulse width modulation (PD PWM):- In phase disposition pulse width modulation strategy, where all carrier waveforms are in same phase shown in fig. 4(a)..8.6.4.2 -.2 -.4 -.6 -.8 8 -.5..5.2.25.3.35.4.45.5 Fig. 4(a). arrier arrangement for PDPWM strategy Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
Voltage International Journal of Electronics, Electrical and omputational System IJEES May 26 Phase opposition disposition pulse width modulation (POD PWM):- In phase opposition disposition pulse width modulation strategy, where all carrier waveforms above zero reference are in phase and below zero reference are 8 out of phase Shown in fig. 4(b)..8.6.4.2 -.2 -.4 -.6 -.8 -.5..5.2.25.3.35.4.45.5 Fig. 4(b). arrier arrangement for PODPWM strategy Alternate phase opposition disposition pulse width modulation (APOD PWM):- In alternate phase opposition disposition PWM scheme where every carrier waveform is in out of phase with its neighbor carrier by 8. Shown in fig. 4(c)..8.6.4.2 -.2 -.4 -.6 -.8 -.5..5.2.25.3.35.4.45.5 Fig. 4(c).arrier arrangement for APODPWM strategy Inverted Sine arrier PWM (ISPWM):- This control strategy replaces the conventional triangular based carrier waveform by inverted sine wave which has a better spectral quality and a higher fundamental output voltage without any pulse dropping[]. This technique combines the advantage of inverted sine and constant or variable frequency carrier signals as shown in Fig. 3.2 and Fig. 3.3 respectively. However, the fixed frequency carrier based PWM affects the switch utilization in multilevel inverters. In order to balance the switching duty among the various levels in inverters, a variable frequency carrier based PWM has been shown [2]-[3]. Both the techniques are explained in brief..8.6.4.2 -.2 -.4 -.6 -.8 -.5..5.2.25.3.35.4.45.5 Fig. 4(d).arrier arrangement for ISPWM strategy 9 Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
Voltage International Journal of Electronics, Electrical and omputational System IJEES May 26 Variable Frequency Inverted Sine arrier PWM (VFISPWM):- The VFISPWM technique provides an enhanced fundamental voltage, lower THD and minimizes the switch utilization among the bridges in inverters [4]. The number of active switching among the bridges is balanced by varying the carrier frequency based on the slope of the modulating wave in each band. The frequency ratio for each band should be set properly for balancing the switching action for all bridges..8.6.4.2 -.2 -.4 -.6 -.8 -.5..5.2.25.3.35.4.45.5 Fig. 4(e).arrier arrangement for VFISPWM strategy V. SIMULATION ESULTS The simulation parameters are as following : dc source voltage is V; Frequency of carrier signal is 4 khz. In this paper, three PWM techniques are used PD, POD, and APOD, with same modulation index (Ma). For Ma =., and Mf = 2, corresponding (%) THD are PD = 84.62%, POD = 7.55%, APOD = 7.55%, ISPWM = 98.49% and VFISPWM = 95.96%. Based on the PWM techniques, the harmonic spectrum was analysed using the FFT Window in MATLAB/Simulink..8.6.4.2 -.2 -.4 -.6 -.8 -.5..5.2.25.3.35.4.45.5 Fig. 5.: arrier Modulation Signals of Three-Phase 3-Level T-type. 2 Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
Mag Mag (% of Fundamental) Mag International Journal of Electronics, Electrical and omputational System IJEES May 26 5-5.5..5.2.25.3.35.4.45.5 5-5.5..5.2.25.3.35.4.45.5 5-5.5..5.2.25.3.35.4.45.5. Fig.5.2: Simulated Three-Phase Voltage by PDPWM for -Load. Selected signal: 2.5 cycles. FFT window (in red): 2 cycles 4 2-2 -4.5..5.2.25.3.35.4.45.5 (s) 8 Fundamental (5Hz) = 24.3, THD= 84.62% 6 4 2 5 5 2 25 3 35 4 Frequency (Hz) Fig. 5.3: Phase output voltage by PD (Ma=., Mf=2). Selected signal: 2.5 cycles. FFT window (in red): 2 cycles 4 2-2 -4.5..5.2.25.3.35.4.45.5 (s) Fundamental (5Hz) = 27.55, THD= 7.55% 8 6 4 2 5 5 2 25 3 35 4 Frequency (Hz) Fig.5.4: Phase output voltage by PODPWM (Ma=., Mf=2). 2 Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
Mag Mag Mag International Journal of Electronics, Electrical and omputational System IJEES May 26 Selected signal: 2.5 cycles. FFT window (in red): 2 cycles 4 2-2 -4.5..5.2.25.3.35.4.45.5 (s) Fundamental (5Hz) = 27.55, THD= 7.55% 8 6 4 2 5 5 2 25 3 35 4 Frequency (Hz) Fig. 5.5: Phase output voltage by APODPWM (Ma=., Mf=2). Selected signal: 2.5 cycles. FFT window (in red): 2 cycles 4 2-2 -4.5..5.2.25.3.35.4.45.5 (s) Fundamental (5Hz) = 2.4, THD= 98.49% 6 5 4 3 2 2 4 6 8 2 4 6 8 Frequency (Hz) Fig. 5.5: Phase output voltage by ISPWM (Ma=., Mf=2). Selected signal: 2.5 cycles. FFT window (in red): 2 cycles 4 3 2 - -2-3 -4.5..5.2.25.3.35.4.45.5 (s) Fundamental (5Hz) = 22.26, THD= 93.8% 8 6 4 2 5 5 2 25 3 35 4 Frequency (Hz) Fig. 5.5: Phase output voltage by VFISPWM (Ma=., Mf=2). 22 Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
International Journal of Electronics, Electrical and omputational System IJEES May 26 INVETE TYPE TABLE-II (NUMBE OF OMPONENTS) DMLI FMLI HBMLI T-TYPE NP Main Switches 4 4 4 4 Main 4 4 4 4 Diodes lamping Diodes 2 D Bus apacitor/ Isolated Supplies 2 2 2 Flying apacitor 3 Total Numbers 2 3 8 Modulation Index TABLE-III (TOTAL HAMONI DISTOTION) T-type Inverter PDPWM PODPWM APODPWM ISPWM VISPWM 84.62% 7.55% 7.55% 98.49% 79.8%.9 5.84% 84.% 84.% 29.49% 95.96%.8 7.9% 9.74% 9.74% 87.64% 5.59% Fig. (a) Total Harmonic Distortion of T-type inverter VI. ONLUSION In this paper, a 3-level T-type inverter is proposed with different PWM techniques is used to generate 3-level output phase voltage. It is proved that, the proposed work of 3-Phase 3-Level T-type inverter output voltage total harmonics distortion is reduced and improve the efficiency of system compare with different PWM techniques. Harmonic analysis carried out using Mat Lab 29a version software.. Simulation results show the performance of 3-Phase 3-Level T-type inverter with different PWM techniques. Table-II shows the number of power switches [IGBTs] and output voltage steps in the proposed topology. This proposed MLI topology requires less number of components as compared to conventional MLI inverters. EFEENES [] X.Yuan and I.Barbi, "Fundamentals of a New Diode lampingmultilevel Inverters", IEEE Transaction Power Electron., Vol.5, No.4, 2, pp.7-78. [2] Jose odriguez, Jih-Sheng Lai and Fang Zheng Peng. Multilevel Inverters: A survey of topologies, controls and applications. IEEE Trans. Ind.Electronics.vol-49 no.4 pp 724-738, Aug. 22. [3] E. Babaei, Optimal topologies for cascaded sub-multilevel converters, Power Electron., vol., no. 3, pp. 25 26, May 2 [4] Y. Wang, Q. Gao, X. ai, "Mixed P WM for Dead- Eliminination and ompensation in a Grid-Tied Inverter,"IEEE Trans. on Industrial Electronics, Vol. 58, No., pp.4797-483,2ll. [5] O.S. Senturk, L. Helle, S. M. Nielsen, P. odriguez,.teodorescu, "Power apability Investigation Based on Electrothermal Models of Press-Pack IGBT Three-Level NP and ANP V Ss for Multimegawatt WindTurbines," IEEE Trans. on Power Electronics, Vol. 27,No.7, pp. 395-326,22. [6] T. Li, LT. Liu, D. Boroyevich, P. Mattavelli, X. Y. Xue, "Three-level Active Neutral-Point-lamped Zero- urrenttransition onverter for Sustainable Energy Systems,"IEEE Trans. on Power Electronics, Vol. 26, No. 2, pp. 368-3693,2ll. 23 Amit Singh Jadon, Praveen Bansal, Dr. Anmol atna Saxena
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