PRELIMINARY DATASHEET

PRELIMINARY DATASHEET 27.5-31 GHz 37dBm High Power Amplifier DESCRIPTION The is a high performance GaAs Power Amplifier MMIC designed to operate in the Ka Band. The has an output power of 4W at the 1dB compression point and has a small signal gain of 19dB. It can be used in Radar, telecommunication and instrumentation applications. The is a 3 stages dual line-up architecture with couplers for power splitting and combining delivering excellent input and output matching. The die is manufactured using s High Performance 0.13µm gate length PHEMT Power Technology. The MMIC uses gold bonding pads and backside metallization, the die is fully protected with Silicon Nitride passivation to obtain the highest level of reliability. FEATURES Operating frequency range : 27.5 to 31 GHz Output Psat : > 5W (+ 37dBm) Output P1dB : > 4W (+ 36dBm) Gain : 19dB 50 Ohms input and output matched Input Return Loss : > 10dB Output Return Loss : > 7dB Power Supply : 5.6A at 4.5V Delivered as 100 % on-wafer RF tested dies Samples and evaluation Boards Available Die size = 3.92 x 4.22 mm Device Availability (Q3 2011) Tested, Inspected Known Good Die (KGD) Module Demonstration Boards Space and MIL-STD MMIC s VD1H VD2H VD3H RFOUT This technology has been evaluated for space applications and is on the European Preferred Parts List of the European Space Agency RFIN VG1H VD1L VG2H VD2L VG3H VD3L APPLICATIONS VG1L VG2L VG3L Radar Telecommunications High Power Amplifier Block Diagram Instrumentation Revision : 24/06/2011 Email : information@ommic.com

MAXIMUM VALUES T amb = + 25 C, at Die backside; unless otherwise specified. Preliminary Datasheet Symbol Parameter Conditions MIN. MAX. UNIT VG1N, VG2N, VG3N, VG1S, VG2S, VG3S VD1N, VD2N, VD3N, VD1S, VD2S, VD3S Gate voltage - 2,5 0 V Drain voltage 0 + 6 V ID1N, ID1S 600 ID2N, ID2S Drain current 1000 ma ID3N, ID3S 1800 IGNN, S (all gates) Gate Current - 1 + 1 ma P IN RF Input power + 20 dbm Tamb Ambient temperature - 40 + 85 C Tj Junction temperature + 175 C Tstg Storage temperature - 55 + 85 C Operation of this device outside the parameter ranges given above may cause permanent damage 2 / 13 THERMAL CHARACTERISTICS Symbol Parameter Value UNIT Rth (j - amb) Thermal resistance from junction to ambient (DC power at Tamb max) TBD C/W ELECTRICAL CHARACTERISTICS T amb = + 25 C, I D3N, I D3S = 1600mA, I D2N, I D2S = 800mA, I D1N, I D1S = 400mA, Symbol Parameter Conditions MIN. TYP. MAX. UNIT RFin Input frequency 27.5 31 GHz Performances on Reference Board at f i = 29 GHz V D1H, 2H, 3H V D1L, 2L, 3L Drain Supply voltage + 4,5 V I DD Total supply current @ Psat 5000 ma G Gain 19 db NF Noise Figure TBD db P1dB 1dB compression point + 36 dbm Psat Saturated power + 37 dbm PAE Power Added Efficiency 18 % OIP3 Output third order intercept point + 45 dbm IMD3 2 Carriers 3 db below P1dB - 25 dbc ISO rev Reverse Isolation RFOUT/RFIN -40 db S 11 Input reflection coefficient 50 Ohms -10 db S 22 Output reflection coefficient 50 Ohms -7 db P OFF Leakage when HPA off All gates = -2,5V RFIN = + 17 dbm -30 dbm (*) Measurement reference planes are the INPUT and OUTPUT plans of the MMIC. Caution : This device is a high performance RF component and can be damaged by inappropriate handling. Standard ESD precautions should be followed. document OM- CI-MV/ 001/ PG contains more information on the precautions to take.

CGY2138 have been measured on-wafer using a pulse measurement test-bench, this method assure a full polarization conditions and cold channel temperature. This method remove the risk of reliability damages due to high temperature overstress inherent to on wafer measurements at full polarization and reflects the performances of the devices in good cooling conditions. 3 / 13 S-PARAMETERS (SMITH CHARTS) Conditions : VD3N,D3S = VD2N, D2S = VD1N, D1S = 4.5V, (IDQ3N, IDQ3S = 1600mA, IDQ2N, IDQ2S = 800mA, IDQ1N, IDQ1S = 400 ma), Tamb = + 25 C (On carrier measurements) Figure 1 : S11 measurements Figure 2 : S22 measurements

4 / 13 Figure 3 : Gain and reverse isolation S PARAMETERS Conditions : VD1N, VD1S = VD2N, VD2S = VD3N, VD3S = 4.5V, IDQ1N, IDQ1S = 400mA, IDQ2N, IDQ2S = 800mA, IDQ3N, IDQ3S = 1600 ma, Tamb = + 25 C (On-Wafer measurements) GHz S11 S11 Phase S21 S21 Phase S12 S12 Phase S22 S22 Phase 19,00 0,74-19,6 0,55 24,8 0,001-28,3 0,70-57,0 20,00 0,71-41,1 0,78-27,9 0,001-17,8 0,67-81,7 21,00 0,68-62,0 1,08-77,1 0,002-40,2 0,65-104,6 22,00 0,65-83,2 1,73-130,2 0,002-102,2 0,62-128,1 23,00 0,63-104,4 2,81 177,5 0,001-138,4 0,57-153,7 24,00 0,61-127,0 5,05 117,7 0,001-126,8 0,48 174,0 25,00 0,58-154,7 9,50 48,3 0,001-124,9 0,36 123,9 25,50 0,55-173,5 13,53 4,9 0,001-152,5 0,29 83,3 26,00 0,50 163,4 17,64-44,9 0,001 149,3 0,24 32,2 26,50 0,41 135,2 19,77-96,7 0,000-7,2 0,23-11,3 27,00 0,31 101,8 20,31-147,7 0,001-61,4 0,24-39,1 27,50 0,23 62,9 18,66 164,4 0,002-95,0 0,26-51,2 28,00 0,21 20,9 16,80 120,5 0,002-119,5 0,31-60,6 28,50 0,23-15,8 15,39 79,6 0,003-150,9 0,37-71,3 29,00 0,25-46,0 14,47 37,9 0,003 175,0 0,42-85,1 29,50 0,26-63,4 13,39-3,2 0,003 163,2 0,43-98,6 30,00 0,26-80,1 12,24-42,4 0,003 135,2 0,43-110,4 30,50 0,24-87,0 11,37-78,4 0,003 94,7 0,38-118,4 31,00 0,24-95,2 11,04-118,3 0,002 64,9 0,34-122,0 31,50 0,22-103,4 10,60-162,6 0,001 33,8 0,30-122,3 32,00 0,17-108,9 9,92 150,5 0,001 3,3 0,27-116,7

32,50 0,09-103,6 8,69 102,3 0,001-30,3 0,27-103,8 33,00 0,12-23,1 7,10 51,0 0,001-118,2 0,34-95,3 33,50 0,31-23,6 5,36-3,6 0,002-165,7 0,43-96,2 34,00 0,50-42,3 3,43-54,5 0,002 157,9 0,52-102,4 34,50 0,63-59,9 1,97-97,2 0,003 132,7 0,59-110,5 35,00 0,72-74,5 1,12-131,1 0,003 75,4 0,65-118,4 36,00 0,82-97,3 0,42 173,6 0,001 7,1 0,74-133,7 38,00 0,89-129,1 0,08 71,4 0,001 120,6 0,83-164,4 40,00 0,93-154,7 0,02-18,5 0,001 107,7 0,85 161,3 5 / 13 1DB COMPRESSION POINT, SATURATED POWER, PAE AND GAIN Conditions : VD3N, VD3S = VD2N, VD2S = VD1N, VD1S = 4.5V, IDQ3N, IDQ3S = 1600mA, IDQ2N, IDQ2S = 800mA, IDQ1N, IDQ1S = 400 ma, Tamb = + 25 C (Pulsed On Wafer measurements) Figure 4 : Psat, P1dB, Gain and PAE at Psat

6 / 13 LINEARITY Conditions : VD3N, VD3S = VD2N, VD2S = VD1N, VD1S = 4.5V, IDQ3N, IDQ3S = 1600mA, IDQ2N, IDQ2S = 800mA, IDQ1N, IDQ1S = 400 ma, Tamb = + 25 C (On Carrier measurements) Linearity measurements have been performed with input signal formed of 2 carriers with 10MHz difference in frequency at the same carrier level. Figure 5 : Linearity curve

HPA MODULE plan to use the advance substrate TACLAM+ to deliver a module version of the PA. 7 / 13 APPLICATION SCHEMATIC To prevent unstability of the customer design it is hightly recommended to place a 47pF RF decoupling chip capacitor at each DC terminal with the shortest possible bonding wires. Additionnaly, a 10nF capacitor can be added on a drain connection. In the gate circuitry, a 500 Ω resistor have been added in serie with each gate introducing some low pass filtering in case of fast power switching. VD_1N VG_1N VD_2N VG_2N VD_3N VG_3N 47pF 10 nf 47pF 10 nf 47pF 10 nf 47pF 500 Ω 10 nf 47pF 500 Ω 10 nf 47pF 500 Ω 10 nf VD1N VG1N VD2N VG2N VD3N VG3N RFIN MMIC Contain RFOUT VD1S VG1S VD2S VG2S VD3S VG3S 47pF 500 Ω 10 nf 47pF 500 Ω 10 nf 47pF 500 Ω 10 nf 47pF 10 nf 47pF 10 nf 47pF 10 nf VD_1S VG_1S VD_2S VG_2S VD_3S VG_3S Figure 6 : Application schematics

8 / 13 Component NAME Value Type Comment All 47pF capacitors 47pF Chip Capacitor Chip capacitor PRESIDIO COMPONENTS P/N SA151BX470M2HX5#013B soldered close to the die with bonding as short as possible All 500 Ω resistors 500 Ω Chip Resistor Chip resistor US MICROWAVES RG1421-500-1% soldered close to the 47pF chip capacitor with bonding as short as possible All 10nF capacitors 10nF Chip Capacitor MURATA GMA085R71C103MD01T GM260 X7R 103M 16M100 PM520 Due to the highly symmetrical design of the component and the requirements of the power combiner, it is recommended to keep IDQ1N equal to IDQ1S, IDQ2N equal to IDQ2S and IDQ3N equal to IDQ3S, for the same reason, it is recommended to keep VD1N equal the VD1S, VD2N equal the VD2S and VD3N equal the VD3S. In order to save DC power consumption and improve PAE each of the 6 gates can be individually driven at a different bias voltage. In this case, when using the targeted RF signal (modulated carrier), the distortion is monitored while adjusting VG1N,VG2N, VG3N, VG1S, VG2S and VG3S. The global strategy is to introduce all the distortion allowed by the targeted standard in the last stage of the amplifier by adjusting VG3N, VG3S while VG1N, VG1S, VG2N, VG2S are positioned in such a way that the 2 first stages of each line-up are kept at a neglectable contribution to the global distortion. An additional amount of DC power supply can be saved in fine tuning the drain voltages VD1N,VD2N, VD3N, VD1S, VD2S and VD3S while following the same procedure and the same strategy as described above. In order to validate each stage of the amplifier, with respect to the DC, it is recommended to set VGNS or VGNN (N =1,2,3) to -2.5V, then to set first the corresponding drain voltage VDNL or VDNH (N =1,2,3) to +1V and check that the corresponding IDNL or IDNH (N =1,2,3) drain current stay at a very low level, after that verification, VDNL or VDNH (N =1,2,3) can be set to 4.5V. When VGNL or VGNH (N =1,2,3) is changed from -2.5 to - 0.3V, the corresponding drain current IDNL or IDNH increases slowly in a controlled manner to reach the typical targeted value. Each gate can be randomely and independently positionned, no particular order is required.

Preliminary Datasheet 9 / 13 DIE LAYOUT AND PIN CONFIGURATION In order to enable to access voltage drain, an additionnal sense pad have been implemented on each drain voltage. The customer is free to use it or not. Due to design constraints, VG3N and VG3S signals have been implemented twice and named VG3N2 and VG3S2. During testings used only VG3N and VG3S, no guaranty is provided regarding the use of VG3N2 and VG3S2. SVD2N SVD1N SVD3N VG2N VD1N VG3N2 VD2N VG3N VG1N VD3N RFIN RFOUT VD1S SVD1S VG3S2 VD2S SVD2S VG3S VG1S VG2S VD3S SVD3S Figure 7 Pad layout

PINOUT Preliminary Datasheet The amplifier has a North and South face, North is top and South is Bottom when RF input is on the left and RF output on the right. 10 / 13 Symbol Pad Description RFOUT OUT RF output RFIN IN RF input VD1N VD1N First stage Drain (amplifier North) VD2N VD2N Second stage Drain (amplifier North) VD3N VD3N Third stage Drain (amplifier North) SVD1N Sense VD1N First stage Drain Sense (amplifier North) SVD2N Sense VD2N Second stage Drain Sense (amplifier North) SVD3N Sense VD3N Third stage Drain Sense (amplifier North) VG1N VG1N First stage Gate (amplifier North) VG2N VG2N Second stage Gate (amplifier North) VG3N VG3N Third stage Gate (amplifier North) VG3N2 VG3N2 Alternate Third stage Gate (amplifier North) VD1S VD1S First stage Drain (amplifier South) VD2S VD2S Second stage Drain (amplifier South) VD3S VD3S Third stage Drain (amplifier South) SVD1S Sense VD1S First stage Drain Sense (amplifier South) SVD2S Sense VD2S Second stage Drain Sense (amplifier South) SVD3S Sense VD3S Third stage Drain Sense (amplifier South) VG1S VG1S First stage Gate (amplifier South) VG2S VG2S Second stage Gate (amplifier South) VG3S VG3S Third stage Gate (amplifier South) VG3S2 VG3S2 Alternate Third stage Gate (amplifier South) GND BACKSIDE Ground Note : In order to ensure good RF performances and stability It is key to connected to the ground the pad available on the backside of the die.

BONDINGS PAD COORDINATES 11 / 13 4835 4045 4550 4350 4150 2060 0 75 0 0 110 235 360 610 735 860 985 1110 1235 1360 1860 2235 2485 2860 2985 3110 3235 3360 3485 3610 3735 Figure 8 : pad coordinates MMIC Steps on the wafer are 3.92 and 4.22 mm along X and Y coordinated respectively, dicing typically reduce the die by 80um. PACKAGE

12 / 13 Type Description Terminals Pitch (mm) Package size (mm) DIE 100% RF and DC on-wafer tested 23-3.92 x 4.22 x 0.07 Module 100% RF and DC 15-15 x 15 x 4 SOLDERING To avoid permanent damages or impact on reliability during soldering process, die temperature should never exceed 330 C. Temperature in excess of 300 C should not be applied to the die longer than 1mn Toxic fumes will be generated at temperatures higher than 400 C

DEFINITIONS 13 / 13 Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. s customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify for any damages resulting from such application. Right to make changes reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ORDERING INFORMATION Generic type Package type Version Sort Type Description CGY2138 UH C1 - On-Wafer measured Die CGY2138 ML - - Module CGY2138 DB - - Demo-Board