MC4B Series B-Suffix Series CMOS Gates MC4B, MC4B, MC4B, MC4B, MC4B, MC4B, MC4B, MC4B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. Features Supply Voltage Range =. Vdc to Vdc All Outputs Buffered Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC4B and MC4B PinforPin Replacements for Corresponding CD4 Series B Suffix Devices PbFree Packages are Available MAXIMUM RATINGS (Voltages Referenced to ) Symbol Parameter Value Unit DC Supply Voltage Range. to +. V V in, V out I in, I out P D Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note ). to +. V ± ma mw T A Ambient Temperature Range to + C T stg Storage Temperature Range 6 to + C T L V ESD Lead Temperature (Second Soldering) ESD Withstand Voltage Human Body Model Machine Model Charged Device Model 6 C > > N/A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages:. mw/ C From 6 C To C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. V Device MC4B MC4B MC4B MC4B MC4B PDIP4 P SUFFIX CASE 646 D SUFFIX CASE A TSSOP4 DT SUFFIX CASE 94G SOEIAJ4 F SUFFIX CASE 96 4 DEVICE INFORMATION Description Quad Input NOR Gate Quad Input NAND Gate Triple Input NAND Gate 4 Triple Input NOR Gate Quad Input OR Gate MARKING DIAGRAMS MC4xxBCP AWLYYWWG 4 4 4xxBG AWLYWW 4 xxb ALYW xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = PbFree Package (Note: Microdot may be in either location) MC4B MC4B MC4B Triple Input AND Gate Quad Input AND Gate Dual 4Input AND Gate MC4xxB ALYWG ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, September, Rev. Publication Order Number: MC4B/D
MC4B Series LOGIC DIAGRAMS NOR NAND OR AND MC4B Quad Input NOR Gate MC4B Quad Input NAND Gate MC4B Quad Input OR Gate MC4B Quad Input AND Gate INPUT 6 9 4 6 9 4 6 9 4 6 9 4 MC4B Triple Input NOR Gate MC4B Triple Input NAND Gate MC4B Triple Input AND Gate MC4B Dual 4Input AND Gate INPUT 9 4 6 MC4B Quad Input NOR Gate 9 4 6 MC4B Quad Input NAND Gate PIN ASSIGNMENTS 9 4 6 MC4B Triple Input NAND Gate 4 9 = PIN 4 = PIN FOR ALL DEVICES NC = 6, MC4B Triple Input NOR Gate IN A IN A 4 IN D IN A IN A 4 IN D IN A IN A 4 IN C IN A IN A 4 OUT A IN D OUT A IN D IN B IN C IN B OUT B 4 OUT D OUT B 4 OUT D IN B 4 IN C IN B 4 IN B OUT C IN B OUT C IN B OUT C IN B IN B 6 9 IN C IN B 6 9 IN C OUT B 6 9 OUT A OUT B 6 9 IN C IN C IN A IN C IN C IN C OUT C OUT A IN A MC4B Quad Input OR Gate MC4B Triple Input AND Gate MC4B Quad Input AND Gate MC4B Dual 4Input AND Gate IN A IN A 4 IN D IN A IN A 4 IN C IN A IN A 4 IN D OUT A IN A 4 OUT A IN D IN B IN C OUT A IN D IN A OUT B 4 OUT D IN B 4 IN C OUT B 4 OUT D IN A 4 IN B OUT C IN B OUT C IN B OUT C IN 4 A IN B 6 9 IN C OUT B 6 9 OUT A IN B 6 9 IN C NC 6 9 IN C IN A IN C OUT B IN 4 B IN B IN B IN B NC NC = NO CONNECTION
MC4B Series ELECTRICAL CHARACTERISTICS (Voltages Referenced to ) ÎÎ C C ÎÎ C Î Characteristic Î Symbol Vdc Min MaxÎ Min Typ () Î Max Min Max Unit Î Output Voltage Level Î V OL..Î Î.. Vdc V Î in = or...... Î Level V OH ÎÎ. 4.9 Î V in = or 9.9 4.9 Î 9.9. 4.9 Î 9.9 Vdc 4.9 4.9 4.9 Input Voltage Level V Î (V O = 4. or. Vdc) Î IL Vdc. Î (V O = 9. or. Vdc)..Î.. 4.Î... (V O =. or. Vdc) 4. 6. 4. 4. Level V Î (V O =. or 4. Vdc) Î IH Vdc. Î (V O =. or 9. Vdc)... Î...Î.. (V O =. or. Vdc). Output Drive Current I Î (V OH =. Vdc) Source Î OH madc.. Î.4 4.Î. Î (V OH = 4.6 Vdc)..64 Î...6 (V Î OH = 9. Vdc).6...9 (V OH =. Vdc) 4..4.Î.4 Î (V OL =.4 Vdc) Sink Î I OL..64 Î (V OL =. Vdc).6. Î...6ÎÎ.Î.9 madc (V OL =. Vdc) 4..4..4 Input Current I in ±. ±. ±. ±. Adc ÎÎ Input Capacitance C Î (V in = ) Î in.î. pf Î Quiescent Current Î I DD. Î (Per Package).. Î..Î. Î.. Adc... Total Supply Current () (4) I Î (Dynamic plus Quiescent, Î T. I ÎÎ T = (. A/kHz) f + I DD /N Adc I T = (.6 A/kHz) f + I DD /N Per Gate, C Î L = pf) I Î T = (.9 A/kHz) f + I DD /N. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance.. The formulas given are for the typical characteristics only at C. 4. To calculate total supply current at loads other than pf: I T (C L ) = I T ( pf) + (C L ) Vfk where: I T is in A (per package), C L in pf, V = ( ) in volts, f in khz is input frequency, and k =. x the number of exercised gates per package.
MC4B Series BSERIES GATE SWITCHING TIMES SWITCHING CHARACTERISTICS () (C L = pf, T A = C) V Characteristic ÎÎ Symbol Î DD Vdc Î Min Î Typ Î (6) Max Unit Output Rise Time, All BSeries Gates ÎÎ t TLH Î Î Î ns t TLH = (. ns/pf) C L + ns ÎÎ. Î Î Î t TLH = (.6 ns/pf) C L + ns t TLH = (.4 ns/pf) C L + ns Î 4 Î Output Fall Time, All BSeries Gates t THL Î Î Î ns t THL = (. ns/pf) C L + ns ÎÎ. Î Î Î t THL = (.6 ns/pf) C L + ns t THL = (.4 ns/pf) C L ÎÎ Î Î Î + ns 4 Propagation Delay Time t MC4B, MC4B only ÎÎ PLH, t PHL ns Î Î Î t PLH, t PHL = (.9 ns/pf) C L + ns ÎÎ. Î Î Î t PLH, t PHL = (.6 ns/pf) C L + ns t PLH, t PHL = (.6 ns/pf) C L + ns ÎÎ Î Î 4 Î All Other,, and 4 Input Gates t PLH, t PHL = (.9 ns/pf) C L Î + ns. 6 t PLH, t PHL = (.6 ns/pf) C L + 4 ns ÎÎ Î Î 6 Î t PLH, t PHL = (.6 ns/pf) C L + ns Î Input Gates (MC46B, MC4B) t PLH, t PHL = (.9 ns/pf) C L + ns ÎÎ. Î Î Î t PLH, t PHL = (.6 ns/pf) C L + 6 ns Î t PLH, t PHL = (.6 ns/pf) C L + 4 ns. The formulas given are for the typical characteristics only at C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 6 PULSE GENERATOR INPUT * 4 C L OUTPUT *All unused inputs of AND, NAND gates must be connected to. All unused inputs of OR, NOR gates must be connected to. ns ns INPUT 9% % % t PHL t PLH OUTPUT INVERTING OUTPUT NON-INVERTING t THL t PLH t TLH V 9% V OH % % V OL t TLH t PHL V OH 9% % % V OL t THL Figure. Switching Time Test Circuit and Waveforms 4
MC4B Series CIRCUIT SCHEMATIC NOR, OR GATES MC4B, MC4B One of Four Gates Shown MC4B One of Three Gates Shown, 6,, 4,,,, 9, *, 4,, 4,, 4 * *Inverter omitted in MC4B 9, 6,,, *Inverter omitted in MC4B CIRCUIT SCHEMATIC NAND, AND GATES MC4B, MC4B One of Three Gates Shown MC4B, MC4B One of Four Gates Shown * 4, 4,,, 4, 4,, 9,,, *, 6,, *Inverter omitted in MC4B,, 9, 6, *Inverter omitted in MC4B
MC4B Series TYPICAL BSERIES GATE CHARACTERISTICS NCHANNEL DRAIN CURRENT (SINK) PCHANNEL DRAIN CURRENT (SOURCE). - - 9. I D, DRAIN CURRENT (ma) 4.... T A = - C + C - 4 C + C + C I D, DRAIN CURRENT (ma) -. -. - 6. -. - 4. -. -. T A = - C + C - 4 C + C + C -.... 4.. -. -. -. - 4. -. V DS, DRAIN-TO-SOURCE VOLTAGE (Vdc) V DS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure. V GS =. Vdc Figure. V GS =. Vdc - I D, DRAIN CURRENT (ma) 6 4. 6. 4. T A = - C - 4 C + C + C + C I D, DRAIN CURRENT (ma) - 4-4 - - - - - - T A = - C - 4 C + C + C + C. -.... 4.. 6... 9. -. -. -. - 4. -. - 6. -. -. - 9. - V DS, DRAIN-TO-SOURCE VOLTAGE (Vdc) V DS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 4. V GS = Vdc Figure. V GS = Vdc - 4-9 4 - I D, DRAIN CURRENT (ma) T A = - C - 4 C + C + C + C I D, DRAIN CURRENT (ma) - - 6 - - 4 - - T A = - C - 4 C + C + C + C. -. 4. 6.. 4 6 V DS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 6. V GS = Vdc -. - 4. - 6. -. - - - 4-6 - - V DS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure. V GS = Vdc These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is ma per pin. 6
MC4B Series TYPICAL BSERIES GATE CHARACTERISTICS (cont d) VOLTAGE TRANSFER CHARACTERISTICS V out, OUTPUT VOLTAGE (Vdc). 4.... SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND V out, OUTPUT VOLTAGE (Vdc). 6. 4.. SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND... 4... 4. 6.. V in, INPUT VOLTAGE (Vdc) V in, INPUT VOLTAGE (Vdc) Figure. =. Vdc Figure 9. = Vdc V out, OUTPUT VOLTAGE (Vdc) 6 4. 6. 4.. SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND DC NOISE MARGIN The DC noise margin is defined as the input voltage range from an ideal or input level which does not produce output state change(s). The typical and guaranteed limit values of the input values V IL and V IH for the output(s) to be at a fixed voltage V O are given in the Electrical Characteristics table. V IL and V IH are presented graphically in Figure. Guaranteed minimum noise margins for both the and levels =. V with a. V supply. 4. 6.. V in, INPUT VOLTAGE (Vdc). V with a. V supply. V with a. V supply Figure. = Vdc V out V out V O V O V O V O V in V in V IL V IH (a) Inverting Function V IL V IH = VOLTS DC (b) NonInverting Function Figure. DC Noise Immunity
MC4B Series ORDERING INFORMATION MC4BCP MC4BCPG Device Package Shipping PDIP4 PDIP4 Units / Rail MC4BD MC4BDG MC4BDR MC4BDRG MC4BDTR MC4BDTRG MC4BFEL MC4BFELG TSSOP4* TSSOP4* SOEIAJ4 SOEIAJ4 Units / Rail Units / Tape & Reel Units / Tape & Reel MC4BCP MC4BCPG MC4BD MC4BDG MC4BDR MC4BDRG MC4BDTR MC4BDTRG MC4BF MC4BFG MC4BFEL MC4BFELG PDIP4 PDIP4 TSSOP4* TSSOP4* SOEIAJ4 SOEIAJ4 SOEIAJ4 SOEIAJ4 Units / Rail Units / Rail Units / Tape & Reel Units / Rail Units / Tape & Reel MC4BCP MC4BCPG MC4BD MC4BDG MC4BDR MC4BDRG MC4BFEL MC4BFELG PDIP4 PDIP4 SOEIAJ4 SOEIAJ4 Units / Rail Units / Rail Units / Tape & Reel Units / Tape & Reel
MC4B Series ORDERING INFORMATION MC4BCP MC4BCPG Device Package Shipping PDIP4 PDIP4 Units / Rail MC4BD MC4BDG MC4BDR MC4BDRG MC4BFEL MC4BFELG SOEIAJ4 SOEIAJ4 Units / Rail Units / Tape & Reel Units / Tape & Reel MC4BCP MC4BCPG MC4BD MC4BDG MC4BDR MC4BDRG MC4BDT MC4BDTG MC4BDTR MC4BDTRG MC4BFEL MC4BFELG PDIP4 PDIP4 TSSOP4* TSSOP4* TSSOP4* TSSOP4* SOEIAJ4 SOEIAJ4 Units / Rail Units / Rail Units / Tape & Reel 96 Units per Rail Units / Tape & Reel Units / Tape & Reel MC4BCP MC4BCPG MC4BD MC4BDG MC4BDR MC4BDRG MC4BFEL MC4BFELG PDIP4 PDIP4 SOEIAJ4 SOEIAJ4 Units / Rail Units / Rail Units / Tape & Reel Units / Tape & Reel 9
MC4B Series ORDERING INFORMATION MC4BCP MC4BCPG Device Package Shipping PDIP4 PDIP4 Units / Rail MC4BD MC4BDG MC4BDR MC4BDRG MC4BDTR MC4BDTRG MC4BFEL MC4BFELG TSSOP4* TSSOP4* SOEIAJ4 SOEIAJ4 Units / Rail Units / Tape & Reel Units / Tape & Reel MC4BCP MC4BCPG MC4BD MC4BDG PDIP4 PDIP4 Units / Box Units / Rail MC4BDR MC4BDRG Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. *This package is inherently PbFree.
MC4B Series PACKAGE DIMENSIONS PDIP4 CASE 6466 ISSUE P 4 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, 9.. CONTROLLING DIMENSION: INCH.. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A...6 9.6 B.4.6 6. 6.6 F L C.4..69 4.69 D.... C F.4... G. BSC.4 BSC H..9..4 J.... K...9.4 K J L.9... M H G D 4 PL M N..9... (.) M
MC4B Series PACKAGE DIMENSIONS CASE A ISSUE H T SEATING PLANE G A 4 D 4 PL B K P PL C. (.) M T B S A S. (.) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, 9.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 4 F DIM MIN MAX MIN MAX A....44 B. 4... C...4.6 D..49.4.9 M J F.4..6.49 G. BSC. BSC J.9...9 K...4.9 M P. 6...44 R....9 SOLDERING FOOTPRINT* 4X. X.4 4X.. PITCH DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
MC4B Series PACKAGE DIMENSIONS TSSOP4 CASE 94G ISSUE B. (.6) T. (.6) T L. (.4) T SEATING PLANE U U S X L/ PIN IDENT. S D C 4 4X K REF. (.4) M T U S V S N. (.) M B U A V G H N J J F DETAIL E K K ÇÇÇ ÉÉÉ SECTION NN DETAIL E NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, 9.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED. (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED. (.) PER SIDE.. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.9..9. B 4. 4..69. C..4 D....6 F.... G.6 BSC.6 BSC H..6..4 J.9..4. J.9.6.4.6 W K.9... K.9... L 6.4 BSC. BSC M SOLDERING FOOTPRINT*.6.6 PITCH 4X.6 4X.6 DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
MC4B Series PACKAGE DIMENSIONS SOEIAJ4 CASE 96 ISSUE A L E 4 Q E H E M L Z DETAIL P D VIEW P e A c b A. (.) M. (.4) NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, 9.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED. (.6) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE.46 (.). MILLIMETERS INCHES DIM MIN MAX MIN MAX A ---. ---. A.... b...4. c...4. D 9.9..9.4 E..4.. e. BSC. BSC H E.4..9...... L E...4.9 M Q..9.. Z ---.4 ---.6 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 6, Denver, Colorado USA Phone: 6 or 446 Toll Free USA/Canada Fax: 66 or 446 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 4 9 9 Japan Customer Focus Center Phone: 4 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC4B/D