EE290C - Spring 04 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 11 Components Phase-Locked Loops Viterbi Decoder Borivoje Nikolic March 2, 04. Announcements Homework #2 due next week Project will be posted this week 2 1
Outline PLL and DLL components Introduction to Viterbi decoder Additional PLL material: ISSCC 04 tutorial by Dennis Fischette http://www.delroy.com References posted on the web Chapter 12 in the textbook 3 Loop Components Phase Comparator Produces UP/DN pulses corresponding to phase difference Charge Pump Sources/sinks current for duration of UP/DN pulses Loop Filter Integrates current to produce control voltage Voltage-Controlled Delay Line Changes delay proportionally to voltage Voltage-Controlled Oscillator Generates frequency proportional to control voltage 4 2
Timing Loop Components Phase Comparator measures the time difference between two signal transitions for periodic signals measures the phase of one signal with respect to the other the sensor for most timing loops [Dally] Delay Lines adjust the delay between two points in a system the actuator for most timing loops except for PLLs that use VCOs Loop Filters smooth response of the timing loop stabilize the loop (for PLLs) 5 Phase Comparators Output describes phase difference between two inputs φ 1 φ 2 φc φ may be analog or digital may linearly cover a wide range, or just a narrow phase difference 0 π/2 π 3π/2 2π [Dally] 6 3
XOR Phase Detector Sensitive to duty cycle V out (t) Df Df V out 90 o 180 o Df 7 Flip-Flop Phase Comparator Feed f 1 into the clock input Feed f 2 into the data input With single-edge triggered FF, if Q is low, f 1 is. Note that when Df = 0, FF is put in a metastable state If same FF used for receiver and phase comparator, aperture offset is compensated for. Bang-bang loop control φ 2 φ 1 D Q Q 0 π/2 π 3π/2 2π [Dally] 8 4
Other Phase Comparators Sequential phase-only comparator asynchronous state machine pulses up or down output from transition on one input to transition on the other [Dally] Sequential phasefrequency comparator like the sequential phase-only comparator but also keeps track of number of transitions on the two inputs and attempts to make them equal don t use this for a DLL!!! 9 Phase-Frequency Detector Schematic Rst D Q A UP B State-transition diagram UP = 0 DN = 1 B UP = 0 DN = 0 A UP = 1 DN = 0 A Rst D Q DN A B B A A B B UP DN UP DN 10 5
Dead-Zone in PFD Dead-zone occurs when the loop doesn t respond to small phase errors - e.g. 10 ps phase error at PFD inputs: PFD cannot generate 10 ps wide Up and Down pulses Charge-pump switches cannot turn on and off in 10 ps Solution: delay reset to guarantee min. pulse width (typically > 0 ps) [Fischette] 11 Charge Pump Converts PFD digital UP/DN signals into charge Charge is proportional to duration of UP/DN signals Q cp = I UP *t UP I DN *t DN The LPF converts integrates currents Charge pump requirements: Match currents I UP and I DN Reduce control voltage coupling Supply noise rejection, PVT insensitivity (Simple or bandgap biased) I UP UP DN I DN LPF 12 6
Charge Pump: Better Switches Unity-gain buffer controls the voltage over switches Current mirrored into I up /I dn Transmission gate switches Young, JSSC 12/92 13 Charge Pump: Reversed Switches Helpers Ingino, JSSC 11/01 14 7
Loop Filter Integrates charge-pump current onto C 1 cap to set average VCO frequency ( integral path). Resistor provides instantaneous phase correction w/o affecting avg. freq. ( proportional path). C 2 cap smoothes IR ripple on V ctl Typical value R lpf in kw Loop Filter: Dual CP Transformation into PI Dual charge pump architecture integral proportional Maneatis, JSSC 12/96 16 8
Low-Pass Filter Smoothing Cap (C 3 ) Smoothing capacitor on control voltage filters CP ripple, but may make loop unstable Creates parasitic pole: v p = 1/(R C 2 ) C 3 < 1/10*C 1 for stability C 3 > 1/50*C 1 for low jitter Smoothing cap reduces IR -induced VCO jitter to < 0.5% from 5-10% Df vco = K vco I cp T err /C 3 Larger C 3 /C 1 increases phase error slightly Fischette, ISSCC 04 17 Filter Capacitors Traditionally thin gate capacitance has been used Below 130nm gate leakage is a problem C1 in the range of tens of pf Alternative: thick oxide or metal cap Area penalty 18 9
Variable Delay Elements Need: a delay element a method to vary the delay Delay elements inverter source-coupled amplifier Methods to vary delay multiplexing a tapped delay line varying the power supply to an inverter chain varying the capacitance driven by each stage varying the resistive load of a source-coupled amplifier Characterized by max and min delay typically a 2:1 throw stability (jitter) t d [Dally] 19 Variable Delay Elements Single-ended vs. differential In CMOS inverter 1% of change in supply changes the delay by 1% (keep this in mind when using clock buffering) Current starved inverters and RC-loaded inverters are worse than 1%-for-1%. Improve by adding stabilization 10
Example VCO Ring-oscillator-based VCO: RC loaded Ring-oscillator-based VCO: Current-starved Hudson, JSSC 88 Jeong, JSSC 87 21 Regulated Delay Line Sidiropoulos 00 22 11
VCO: simple differential delay Change current Or better: Resistances Need linear, variable resistors 23 Delay Elements Maneatis, JSSC 95 24 12
Replica Bias for the Delay Element Replica biasing improves supply and substrate rejection 25 Replica Bias for the Delay Element Interpolation: Place an edge in between two existing edges 0.2%delay/%supply Horowitz, IEEE Micro 98 26 13
Jared s Trip to Berkeley 27 Viterbi Algorithm Example of dynamic programming [Bellman 57] Invented by A. Viterbi in 1967 Explained by Forney in 1972,1973 Used for: Decoding convolutional codes Decoding trellis codes Maximum likelihood detection Speech recognition, etc. Types: Hard-input, hard-output Soft-input, hard-output Soft-input, soft-output 28 14
Trellis States + edges No loops Weights in minutes Mountain View Union Milpitas Hayward 10 City 40 40 Oakland Berkeley 5 Palo Alto Mateo Francisco 29 Shortest Time to Get to Berkeley? What is the best path to take to: Union City? Hayward? Mountain View Union Milpitas Hayward 10 City 40 40 Oakland Berkeley 5 Palo Alto Mateo Francisco Choose the minimum cost at each point (state) 30
Shortest Time to Get to Berkeley? What is the best path to take to: Union City? Milpitas () 10 Union City () Hayward Oakland Mountain View Berkeley 5 Palo Alto (5) Mateo Francisco 31 Shortest Time to Get to Berkeley? What is the best path to take to: Hayward? Milpitas Union City Hayward () (35) Oakland Mountain View 40 Berkeley 5 Palo Alto (5) Mateo Francisco 32 16
Shortest Time to Get to Berkeley? Mountain View Milpitas Union City Hayward () (35) Oakland (50) Berkeley (65) 5 Palo Alto (5) Mateo Francisco 33 The Viterbi Algorithm Illustrated by 2-state trellis sm1 n 1 bm1 sm1 n bm2 bm3 sm2 n 1 bm4 sm2 n t n 1 t n time ( 1 1 ) ( ) sm1n = min sm1n + bm1, sm2n + bm3 sm2n = min sm1n 1 + bm2, sm2n 1 + bm4 Select Add Add Compare 34 17
Digital Baseband Transceiver 35 Convolutional Codes Adding redundancy 1+D 2 + 0111 d i d i-1 d i-2 Channel D 0110 1+D+D 2 Generators: G 1 = 101 G 2 = 111 + D (00, 11, 10, 10) 0100 36 18
State Transition Diagrams 0/00 00 0/01 1/10 10 1/11 0/10 01 0/11 1/00 11 1/01 37 19