A CMOS Image Sensor With Dark-Current Cancellation and Dynamic Sensitivity Operations

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, JANUARY 2003 91 A CMOS Image Sensor With Dark-Current Cancellation and Dynamic Sensitivity Operations Hsiu-Yu Cheng and Ya-Chin King, Member, IEEE Abstract An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35- m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate/photodiode photon sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more than an order of magnitude. Through varying the bias conditions on the photogate, dynamic sensitivity can be obtained to increase maximum allowable illumination level. Combining the above two operation schemes, the dynamic range of this new cell can be extended by more than 20. Index Terms CMOS image sensor, dark current, dynamic range. I. INTRODUCTION CHARGE couple device (CCD) image sensors have shown overwhelmingly superior performances in the various digital imaging applications over a period of time. The predominant reason is the extending market demand for better image quality and eternally larger resolution, which no other technology could perform better than CCDs [1] [4]. With the rapid advances in CMOS technology, the evolution of image sensors based on CMOS logic process has been the subject of many studies in the past ten years. CMOS active pixel sensors (APSs) have the advantages of lower electric power consumption due to lower voltage supply, compatibility with standard CMOS processes, and possibly lower cost [5] [8]. Inherited performance limitations in the CMOS APS have confined its applications to medium-to-low-quality imaging such as fingerprint sensors, motion detect sensors, and low-end cameras. Major disadvantages of the CMOS APS are large dark signal level and low dynamic range, which become the most critical hurdles for achieving-high performance CMOS APS imagers [9] [12]. In recent development, CCD-based sensors using an optical fabrication process and advanced dark current management techniques outperform the CMOS APS by at least a factor of 10 in the dark-signal level [13], [14]. It is thus essential to establish simple and precise methods of suppressing dark signal in current CMOS APS systems to achieve high-quality imaging performance comparable to that of CCDs. Manuscript received March 26, 2002; revised October 22, 2002. This work was supported by the Twin Han Corporation and the National Science Council of Taiwan, R.O.C. The review of this paper was arranged by Editor A. Theuwissen. The authors are with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C. (e-mail: sychen@well.ee.nthu.edu.tw; ycking@ee.nthu.edu.tw) Digital Object Identifier 10.1109/TED.2002.806964 In this paper, an extraordinary low dark-signal pixel that has been implemented in a standard 0.35 m CMOS logic process is developed. Furthermore, we propose two operational schemes in combination with the novel sensor cell design to a dynamic range extension by 2. Effects of various structure parameters and operation schemes are investigated for further optimization of the cell structure and operation scheme. II. NEW PIXEL STRUCTURE AND OPERATION The architecture of the image sensor and the column dual signal-subtaction circuit schematic are shown in Fig. 1. The conventional three-transistor active pixel configuration is employed with our new sensing structure. The photon-sensing device is composed of a photogate (PG) and an n photodiode ring. Fig. 2 shows the corresponding pixel layout. The new proposed operation scheme is illustrated by the timing diagram in Fig. 3. In contrast with typical timing sequence, two reset cycles are included in one integration period. At the beginning, the photodiode (PD) node of the pixels are reset to a voltage approximately one threshold voltage drop below V by pulsing the reset gate (Rst) high. During the first reset cycle, a positive voltage is applied to the PG right after the reset pulse. Thus, the electrons excited by the photon are both generated in the depletion region beneath the photogate oxide and by the n photodiode. When the PG is bias returned to 0 V at the end of the applied pulse, the electrons attracted by the positive PG are then transferred to an adjacent n p junction capacitor. Within this period, the new sensing device works as a combination of PG and photodiode. During the second reset cycle, the bias voltage on the PG is held at 0 V. Consequently, the photon-sensing device functions as a simple photodiode of which carriers are mainly generated and collected in the depletion region of the n to a p-well junction. During sensor read-out, each row is addressed in turn with decoding logic (not shown in Fig. 1 driving the appropriate row line, ROW, to V. The final signals sampled at the end of the two-reset cycle, designated as V and V, are separately stored in the capacitors C and C of the dual signal-subtraction stage with timing sequences as shown in Fig. 3. The fixed pattern noise (FPN) due to variation in the threshold voltages of M1 and M2 is thus cancelled. The sampled output voltage in the end of two different operation reset intervals can thus be expressed as follows: (1) (2) where S and S are the corresponding optical sensitivities under different PG biasing conditions, V and V rep- 0018-9383/03$17.00 2003 IEEE

92 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, JANUARY 2003 Fig. 1. Pixel and column dual signal-subtraction circuit schematic of the proposed CMOS image sensor. Fig. 2. Layout of the novel cell combining PG and photodiode. Fig. 4. Illustration of the new operation scheme with the final signal as 1V 0 1V. depletion region remains almost unaffected. Also, in our timing design, t is identical for collecting V and V. The dark signals are expected to be close to identical for the two reset cycles. Consequently, the unwanted dark signals including their variation can be canceled in the output voltage through the subtracting operation by the op-amp (3) Fig. 3. Timing diagram of the new operation scheme in which t = 1ms, tp =0:5ms, and t I =2ms. resents the dark voltage drop at the first and second reset cycles, respectively, L is the illumination intensity, and t is the reset cycle time, one half of the integration period. The dark-signal variation of the photon-sensing device appears in the output signal, which cannot be removed with a signal-subtraction operation. Since the dark signals reflect the total charge leakage during the integration period, the dark signal nonuniformity components also contribute to the outputs, V and V.In many prior studies [15] [18], it has been shown that the dark current in the CMOS APS cell mainly results from the leakage current in the surface depletion region. By applying different bias voltages on the PG in the two reset cycles, the surface Fig. 4 shows the ideal sensitivity curves before and after the dual signal-subtraction cancellation circuits. Even though the overall sensitivity might be reduced, as illustrated in Fig. 4, V can be completely removed. III. SAMPLE FABRICATION AND MEASUREMENT CONDITION The sensor test structures with pixel dimensions of m m was fabricated by TSMC 0.35 m standard CMOS logic process. For the purpose of higher quantum efficiency and spectral sensitivity, a resist protection oxide (RPO) mask is used to define nonsilicide region, i.e., the photon-sensing area. A 500- s reset pulse at 3.3 V with extended integration period (500 ms) is used to extract the dark voltages. To determine the spectral sensitivity of the sensor pixel, a tungsten halogen lamp and integration sphere were used to provide a uniform source of

CHENG AND KING: CMOS IMAGE SENSOR WITH DARK-CURRENT CANCELLATION 93 Fig. 5. Cumulative probability of the pixel dark signal for a basic n /p diode and new cell structure. Fig. 7. Dependence of pixel sensitivity on the area ratio of PG to PD at t =t =2/3. Fig. 6. Cumulative probability of the cell sensitivity for two photon-sensing structures with or without RPO. illumination. A color-compensating filter was employed to suppress any infrared signal. IV. RESULTS AND DISCUSSIONS A. Sensor Performance The distribution of the cumulative probability of the measured pixel dark current for the conventional and new cell is compared in Fig. 5. It is found that the dark-current level is reduced by more than one order of magnitude to the level comparable to that reported for CCD-based imagers [5]. Moreover, the standard variation of the dark current itself is also drastically reduced from 10 to 0.74 na/cm. The high FPN of a conventional CMOS APS caused by dark current nonuniformity at low illumination levels is greatly reduced. It is reported that the lower quantum efficiency of the PG sensor, particularly at short wavelengths, is largely due to absorption in the gate poly-silicon [13], [19]. Along with the dual signal-subtraction circuit, the spectral sensitivity of the new structure is expected to decrease. However, the sensitivity of the new structure is found to be similar to that of the conventional photodiode from the measurement results demonstrated in Fig. 6. The charge conversion gain for the conventional and novel cell are 7.91 and 7.64 V/e, respectively, which agreed with the capacitance of the floating node ( 3 ff) calculated from the layout. The photon-induced electrons beneath the PG are transferred to the carrier-collecting node (n /p-well diffusion) with relatively smaller capacitance in comparison with the typical photodiode. The magnitude of the spectral Fig. 8. Dependence of pixel dark signal on the area ratio of a PG to a PD at t =t =2/3. sensitivity of the novel cell thus remains at the same level as the conventional ones. Dynamic range (DR) quantifies the ability of an image sensor to adequately image both high and low illuminations in the same scene or setup configuration. It is defined as the ratio of the largest nonsaturating input signal to the smallest detectable input signal. Using the photon induced current to represent the input signal, the largest nonsaturating signal is given by, where is the (effective) charge capacity, is the dark current, and is the integration time. Also, the smallest detectable input signal is usually defined as the standard deviation of the input-referred noise under dark conditions, which gives, where is the total noise due to reset and readout operation. Thus, the dynamic range of the new cell structure is expected to increase as a result of the rising and falling. Our measurement results demonstrate that the DR of the new pixel with the dual signal-subtraction operation scheme is improved by 15 db in comparison with a conventional CMOS APS. B. PG Structure Optimization The new photon-sensing device functions as the mixture of PG and photodiode during the first reset cycle. Consequently, the amount of carriers induced by the running of the PG determines the quantity of the sensitivity. To maximize the sensitivity difference between two reset cycles, the larger layout area ratio of the PG to the diode junction is preferable. Figs. 7 and 8 illustrate the dependencies of the pixel sensitivity and dark signal on the area ratio of the photogate (PG)

94 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, JANUARY 2003 Fig. 9. Dependence of pixel dynamic range on the area ratio of the PG to PD at t =t =2/3. Fig. 11. Dependence of pixel sensitivity on the PG bias voltage conditions. Fig. 10. Effect of PG bias pulse duration on sensitivity and dark signal at an area ratio equal to 1. Fig. 12. Measured output signal 1V +1V versus different illumination intensities. to the photodiode (PD). Apparently, higher pixel sensitivity can be obtained by further increasing the PG/PD area ratio at the cost of a slight increase in dark signal. However, the maximum charge capacity decreases as the area of the electron-collecting node (n /p photodiode junction) decreases. Therefore, the spectral dynamic range degrades slightly with an increased PG/PD ratio, as shown in Fig. 9. C. PG Bias Pulse Design To achieve a reasonable spectral sensitivity and dark-signal level comparable to other noise sources in the CMOS APS, the PG bias pulse optimization is required. One of the parameters that can easily be controlled is the pulse duration. With longer PG pulse duration, not only do the photon-induced carriers increase, but the excess charge accumulated by dark current increases as well. Thus, both the pixel sensitivity and dark signal level are expected to be higher. Fig. 10 illustrates the dependencies of the pixel sensitivity and dark signal on the PG pulse duty cycle. It is found that, with a 1.5 increase in PG pulsewidth, the spectral sensitivity is raised by 80% while the dark signal is increased by 3. Thus, the PG pulsewidth can be designed differently to meet different requirements in sensitivity, DR, and dark noise for better image quality or higher contrast in various applications. D. Adjustable Sensitivity and DR Extension It is observed that different PG bias conditions lead to variable sensitivity. With the 50% duty cycle PG pulse applied, the sensitivity increases by about 2 when the PG bias height rises to 3.3 V (as shown in Fig. 11). This is mainly due to the photon-sensing depletion region extending with higher bias voltage on the PG. However, the trend is completely the opposite when the PG is biased with a fixed positive voltage. This is because more photon-induced electrons are collected to form the inversion layer under the photogate with the fixed positive PG bias. Therefore, less charge is available to the n diffusion output node. Consequently, the sensitivity decreases about 5 as the fixed bias voltage goes up to 3.3 V. The ability to control spectrum sensitivity enables us to adapt different approaches to extend the relatively poor DR of CMOS-based imagers. By summing the output signals from two successive reset cycles and, the sensor can reflect high sensitivity at a low light intensity, whereas they exhibit low sensitivity at a high light intensity. The addition can be done either with an on-chip adder or by off-chip image processing. For example, a PG is applied with a 50% duty cycle at 3.3-V positive pulse during the first rest cycle and with a fixed 3.3-V bias throughout the second. A DR about 10 times larger can thus be obtained by means of adding two outputs (as illustrated in Fig. 12). Even though the dark signal level is doubled, the imager exhibits a better spectral sensitivity at a low light intensity as well. An in-pixel approach is to employ a special circuit, which can apply a bias voltage according to the light intensity. The pixel output signal is connected to the bias voltage on a PG through a feedback trigger circuit, as illustrated in Fig. 13. With a proper design of the low-to-high trigger point of the circuit (e.g., 1 V),

CHENG AND KING: CMOS IMAGE SENSOR WITH DARK-CURRENT CANCELLATION 95 Fig. 13. Proposed pixel schematic with a trigger circuit and its transfer curve. TABLE I PIXEL PERFORMANCE COMPARISON the PG will be pumped to a fixed positive bias at a high light intensity. Sensitivity can be reduced at high light intensity levels, thus the output signals saturate at a higher extended light intensity. The DR is improved as well. However, the main drawback of this technique is that more transistors per pixel is required, resulting in larger pixel sizes or a smaller fill factor. The performance comparison of the conventional photodiode pixel and the new cell with different operation schemes is summarized in Table I. V. CONCLUSION A novel CMOS image sensor implemented in a standard CMOS logic 0.35- m process was proposed. The pixels with a novel photon-sensing device and operation scheme can reduce the dark signal to a level comparable to CCD-based imagers. By optimizing the PG/PD area ratio and the bias pulse, the imaging sensitivity can be further improved for high-speed capture operation. The maximum saturated signal can be extended by variable sensitivity control. The new CMOS image sensor with a high DR and low dark signal is a very promising candidate for a high-quality imager in SOC system. [5] J. P. Albert Theuwissen, CCD or CMOS image sensors for consumer digital still photography?, presented at the 2001 Int. Symp. on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, R.O.C., Apr. 2001, pp. 168 171. [6] E. R. Fossum, CMOS image sensors: Electronic camera-on-a-chip, IEEE Trans. Electron Devices, vol. 44, pp. 1689 1698, Oct. 1997. [7] H. S. P. Wong, CMOS image sensors Recent advances and device scaling considerations, in IEDM Tech. Dig., 1997, pp. 201 204. [8] S. K. Mendis, S. E. Kemeny, R. C. Gee, B. Pain, Q. Kim, and E. R. Fossum, CMOS active pixel image sensors for highly integrated imaging systems, IEEE J. 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Kim, A new leakage component caused by the interaction of residual stress and the relative position of poly-si gate at isolation edge, in IEDM Tech. Dig., 1995, pp. 683 686. [19] T. Lule, S. Benthien, H. Keller, F. Mutze, P. Rieve, K. Seibel, M. Sommer, and M. Bohm, Sensitivity of CMOS based imager and scaling perspectives, IEEE Trans. Electron Devices, vol. 47, pp. 2110 2122, 2000. Hsiu-Yu Cheng was born in Taiwan, R.O.C. He received the B.S. and M.S. degrees in electrical engineering from National Tsing-Hua University, Hsinchu, Taiwan, in 2000 and 2002, respectively. He is currently serving in the R.O.C. army. His research interests include embedded CMOS image sensor design, imager sensor characterization, and analog circuit design. REFERENCES [1] E. R. Fossum, CMOS image sensors: electronic camera-on-a-chip, in IEDM Tech. Dig., 1995, pp. 17 25. [2] B. Ackland and A. Dickinson, Camera-on-a-chip, 1996 ISSCD Tech. Dig., pp. 22 25, 1996. [3] S. K. Mendis, S. E. Kemeny, R. C. Gee, B. Pain, Q. Kim, and E. R. Fossum, CMOS active pixel image sensors for highly integrated imaging systems, IEEE J. Solid-State Circuits, vol. 32, pp. 187 197, Feb. 1997. [4] R. H. Nixon, S. E. Kemeny, B. Pain, C. O. Staller, and E. R. Fossum, 256 2 256 CMOS active pixel sensor camera-on-a-chip, IEEE J. Solid-State Circuits, vol. 31, pp. 2046 2050, Dec. 1996. memory design. Ya-Chin King (S 92 M 99) was born in Taiwan, R.O.C. She received the B.S. degree from National Taiwan University, Taipei, in 1992 and the M.S. degree from the Unversity of California, Berkeley, both in electrical engineering. Her master s work focused on thin oxide technology and novel quasi-nonvolatile memory. She joined National Tsing-Hua University, Hsinchu, Taiwan, in August 1999 as an Assistant Professor. Her research topics include thin gate dielectrics, CMOS image sensors, and nonvolatile