To learn S-parameter, eye diagram, ISI, modulation techniques and to simulate in Matlab and Cadence.

Similar documents
To learn S-parameters, eye diagram, ISI, modulation techniques and their simulations in MATLAB and Cadence.

ECEN720: High-Speed Links Circuits and Systems Spring 2017

ECEN 720 High-Speed Links Circuits and Systems

if the conductance is set to zero, the equation can be written as following t 2 (4)

To learn fundamentals of high speed I/O link equalization techniques.

ECEN 720 High-Speed Links: Circuits and Systems

To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed I/O link circuits

To learn Statistical Bit-error-rate (BER) simulation, BERlink noise budgeting and usage of ADS to model high speed I/O link circuits.

Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission

ECEN720: High-Speed Links Circuits and Systems Spring 2017

TITLE. Capturing (LP)DDR4 Interface PSIJ and RJ Performance. Image. Topic: Topic: John Ellis, Synopsys, Inc. Topic: malesuada blandit euismod.

ECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment

Validation Report Comparison of Eye Patterns Generated By Synopsys HSPICE and the Agilent PLTS

University of Michigan EECS 311: Electronic Circuits Fall 2008 LAB 4 SINGLE STAGE AMPLIFIER

A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

06-496r3 SAS-2 Electrical Specification Proposal. Kevin Witt SAS-2 Phy Working Group 1/16/07

06-011r0 Towards a SAS-2 Physical Layer Specification. Kevin Witt 11/30/2005

DIGITAL VLSI LAB ASSIGNMENT 1

Statistical Link Modeling

SHF Communication Technologies AG. Wilhelm-von-Siemens-Str. 23D Berlin Germany. Phone Fax

Submission date: Wednesday 21/3/2018

56+ Gb/s Serial Transmission using Duobinary Signaling

Texas A&M University Electrical Engineering Department ECEN 665. Laboratory #3: Analysis and Simulation of a CMOS LNA

Project #3 for Electronic Circuit II

Text Book: Simon Haykin & Michael Moher,

ECEN620: Network Theory Broadband Circuit Design Fall 2014

Relationship Between Signal Integrity and EMC

ELEC 2210 EXPERIMENT 12 NMOS Logic

Handout 11: Digital Baseband Transmission

Taking the Mystery out of Signal Integrity

Qiz 1. 3.discrete time signals can be obtained by a continuous-time signal. a. sampling b. digitizing c.defined d.

Testing High-Speed Digital Interfaces with Automated Test Equipment

EE5713 : Advanced Digital Communications

Aries Kapton CSP socket

High Speed I/O 2-PAM Receiver Design. EE215E Project. Signaling and Synchronization. Submitted By

Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft

Assignment 8 Analyzing Operational Amplifiers in MATLAB and PSpice

Comparison of Time Domain and Statistical IBIS-AMI Analyses

University of Michigan EECS 311: Electronic Circuits Fall 2009 LAB 2 NON IDEAL OPAMPS

UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency

HMC853LC3. High Speed Logic - SMT. 28 Gbps, D-TYPE FLIP-FLOP. Typical Applications. Features. Functional Diagram. General Description

EE3723 : Digital Communications

An Example Design using the Analog Photonics Component Library. 3/21/2017 Benjamin Moss

0.85V. 2. vs. I W / L

Experiment 5 Single-Stage MOS Amplifiers

ECE 476/ECE 501C/CS Wireless Communication Systems Winter Lecture 6: Fading

Filters And Waveform Shaping

ECEN 474/704 Lab 6: Differential Pairs

ECEN 4634/5634, MICROWAVE AND RF LABORATORY

Optical Complex Spectrum Analyzer (OCSA)

The Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects

Probing Techniques for Signal Performance Measurements in High Data Rate Testing

DDR4 memory interface: Solving PCB design challenges

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

ECE 476/ECE 501C/CS Wireless Communication Systems Winter Lecture 6: Fading

ECEN689: Special Topics in Optical Interconnects Circuits and Systems Spring 2016

An Analog Phase-Locked Loop

Low-power 2.5 Gbps VCSEL driver in 0.5 µm CMOS technology

High Performance Signaling. Jan Rabaey

Experiments #6. Convolution and Linear Time Invariant Systems

ECE 476/ECE 501C/CS Wireless Communication Systems Winter Lecture 6: Fading

Curve Tracer Laboratory Assistant Using the Analog Discovery Module as A Curve Tracer

Serial Data Transmission

MPN Theory Predictions vs. Measurements. Meir Bartur ZONU, Inc. IEEE ah interim January 2002 Raleigh, NC

NRZ Bandwidth (-3db HF Cutoff vs SNR) How Much Bandwidth is Enough?

High Speed Digital Design & Verification Seminar. Measurement fundamentals

ECEN 325 Lab 5: Operational Amplifiers Part III

SINGLE-ENDED 16x8 GBPS DATA BUS IN 90NM CMOS

HMC721LP3E v Gbps, FAST RISE TIME XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT VOLTAGE

40Gb/s Optical Transmission System Testbed

5Gbps Serial Link Transmitter with Pre-emphasis

10 Mb/s Single Twisted Pair Ethernet 10BASE-T1L PSD Mask Steffen Graber Pepperl+Fuchs

Figure 1. Main window (Common Interface Window), CIW opens and from the pull down menus you can start your design. Figure 2.

Using Signaling Rate and Transfer Rate

Design of a High Dynamic Range CMOS Variable Gain Amplifier for Wireless Sensor Networks

EE 230 Lab Lab 9. Prior to Lab

Wireless Communication Systems Laboratory Lab#1: An introduction to basic digital baseband communication through MATLAB simulation Objective

Hot Topics and Cool Ideas in Scaled CMOS Analog Design

Probe Card Characterization in Time and Frequency Domain

SUNSTAR 微波光电 TEL: FAX: v HMC672LC3C 13 Gbps, AND / NAND / OR / NOR Gate T

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c,

DP Array DPAM/DPAF Final Inch Designs in Serial ATA Generation 1 Applications 10mm Stack Height. REVISION DATE: January 11, 2005

Final Exam. EE313 Signals and Systems. Fall 1999, Prof. Brian L. Evans, Unique No

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier

Lecture 10 Performance of Communication System: Bit Error Rate (BER) EE4900/EE6720 Digital Communications

Generating Jitter for Fibre Channel Compliance Testing

FIBRE CHANNEL CONSORTIUM

Beta and Epsilon Point Update. Adam Healey Mark Marlett August 8, 2007

Lecture Fundamentals of Data and signals

Agilent Time Domain Analysis Using a Network Analyzer

Q2 QMS-DP/QFS-DP Series 11 mm Stack Height Final Inch Designs in Serial ATA Generation 1 Applications. Revision Date: February 22, 2005

Advanced Product Design & Test for High-Speed Digital Devices

Aries CSP microstrip socket Cycling test

ESE531 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Signal Processing

LC VCO Structure. LV VCO structure

SHF Communication Technologies AG. Wilhelm-von-Siemens-Str. 23D Berlin Germany. Phone Fax

Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED

EM Analysis of RFIC Transmission Lines

Texas A&M University Electrical Engineering Department ECEN 665. Laboratory #4: Analysis and Simulation of a CMOS Mixer

Transcription:

1 ECEN 689 High-Speed Links Circuits and Systems Lab2- Channel Models Objective To learn S-parameter, eye diagram, ISI, modulation techniques and to simulate in Matlab and Cadence. Introduction S-parameters are widely used in industry for characterizing the transmission lines, vias, chip sockets, and connectors. A transmission line can be represented by an S-parameter model which can be used during the circuit design and frequency domain simulation. Channel impulse responses can be generated from the S-parameter by performing inverse Fourier transform. Convolving the channel impulse response with input data, channel output can be produced along with the eye diagram. In this lab, channel S-parameter model, Inter-Symbol Interference (ISI), peak distortion analysis, modulation scheme and termination circuit design are going to be studied. The plotting of channel output eye diagram and S-parameter will be performed through Matlab and Cadence. S-parameter ABCD parameters can represent a two-port network as shown in Figure 1, which describes the network in terms of input and output voltage and current. They are suitable for calculating cascaded circuits. Since the ABCD parameters are evaluated with short and open circuits, they are not measured directly; instead they are calculated from the measured S-parameters which can be measured directly by a network analyzer without causing short and open circuit. The conversion between ABCD parameters and S-parameters is shown in Figure 2. Figure 1 ABCD Parameters

2 Channel Impulse Response Figure 2 Two-Port S and ABCD Parameter Conversion A linear, time-invariant (LTI) system as shown in Figure 3 can be completely characterized by its impulse response. Thus, for any input, the output function can be calculated in terms of the input and the impulse response. Figure 3 LTI System The output function in time and frequency domain can be expressed as the following: Y(ω) = H(ω)X(ω) (1) + y(t) = h(t) x(t) = h(t τ)x(τ) (2) The impulse response of a system can be generated from its S-parameters by using inverse Fourier transform. h(t) = F 1 {S(ω)} (3) In this lab, channel S-parameters are provided. The impulse response of the channel is calculated through Matlab. It represents the channel response characteristic. If the input data is given and

3 the channel impulse response is obtained from S-parameters, the transient channel output can be calculated through convolving input data with impulse response. It is shown in Figure 4. Eye Diagram Figure 4 Channel Transient Response An eye diagram is made of overlaying a signal over many of its unit intervals (UI) as shown in Figure 5. It visually indicates a signal s voltage and timing uncertainty due to various circuit non-idealities (power/ground noise, crosstalk, channel loss, phase noise, etc.). It can be generated using simulation tools or be measured using an oscilloscope. The eye opening in the center of the diagram indicates the voltage and timing margin associated with the signal. The amount of the margin can be used to calculate the receiver s sensitivity requirement. The timing margin is often used to estimate a digital system timing budget or the receiver s aperture time. Figure 5 Eye Diagram

4 Inter-Symbol Interference Inter-symbol interference (ISI) is a form of a signal distortion which is caused by reflections, channel resonances and channel loss (dispersion). It is the interference between symbols where the current bit (symbol) could distort its subsequent and previous bits (symbol). An ideal 5Gb/s input pulse is passed through a channel as shown in Figure 6 (blue). Due to the channel characteristic, the pulse is dispersed as shown in Figure 6 (red). The dispersion spreads the pulse energy and distorts other bits, which reduces eye opening. Figure 6 Inter-Symbol Interference Peak Distortion Analysis Peak distortion analysis is used to estimate the worst-case eye diagram from pulse response. The worst-case 1 is the summation of a 1 pulse (t=0) with all negative (negative pre and post cursor ISI) non k=0 pulse responses (t 0, can be 1 or 0 ). It is shown as the following. S 1 (t) = y o (1) (t) + y (d k ) (t KT) y(t KT)<0 k= k 0 (4) The worst-case 0 is the summation of a 0 pulse (t=0) with all positive (positive pre and post cursor ISI) non k=0 pulse responses (t 0, can be 1 or 0 ). It is shown as the following. S 0 (t) = y o (0) (t) + y (d k ) (t KT) y(t KT)>0 k= k 0 The worst case eye height can be expressed as (5)

5 Example: S(t) = 2 y o (1) (t) + y (t) (t KT) y(t KT)<0 k= k 0 y (t) (t KT) y(t KT)>0 k= k 0 (6) Give the pulse response as shown in Figure 7, obtain the worst case eye high and worst case bit pattern using the peak distortion analysis. Figure 7 Channel Response Table 1 Peak Distortion Analysis and Worst-Case Bit Pattern UI -3-2 -1 0 1 2 3 4 5 6 7 8 9 10 volt 0.001 0.005 0.161 0.37 0.178 0.065 0.04 0.03 0.025-0.01-0.02 0.025 0.008 0.005 UI 10 9 8 7 6 5 4 3 2 1 0-1 -2-3 volt 0.005 0.008 0.025-0.02-0.01 0.025 0.03 0.04 0.065 0.178 0.37 0.161 0.005 0.001 Worst Case 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 Worst Case 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 S(t) = 2 y o (1) (t) + y (t) (t KT) y(t KT)<0 k= k 0 y (t) (t KT) y(t KT)>0 k= k 0 (7)

6 y (t) (t KT) y(t KT)<0 = 0.03 k= k 0 y (t) (t KT) y(t KT)>0 = 0.543 k= k 0 (8) (9) The worst case eye height can be calculated as S(t) = 2(0.37 0.03 0.543) = 0.418 (10) Modulation Schemes Most of channel responses are low-pass shape. It attenuates and distorts high frequency component of input signal. Modulation schemes can be used to reduce signal bandwidth and overcome some of the channel loss problems. NRZ, PAM4 and Duobinary modulation schemes are shown in Figure 8. Figure 8 Channel Modulation Schemes NRZ is the simplest and most common used modulation format. For 1Gb/s data rate, the majority of signal power is within 1GHz. PAM-4 transmits 2 bits/symbol, which runs ½ NRZ speed. Its

7 signal power concentrates at half of the NRZ bandwidth. Due to its lower frequency characteristic, it is affected less by the channel s high frequency loss. Less channel equalization is needed but with reduction of eye height. When the channel insertion loss at NRZ frequency is greater than -9.54dB than the channel insertion loss at PAM-4 frequency, PAM-4 scheme could be considered. Duobinary is another modulation scheme which also runs at half of the NRZ speed. It takes advantage of the inherent channel rolloff and results in simpler circuit structure. Duobinary data can be generated by sending NRZ data through a delay and add filer (Low Pass Filter) which is also shown in Figure 9. w[n] = x[n] + x[n 1] (11) Termination Circuits Figure 9 Duobinary Signaling In high speed link design, it is preferred to use on-chip termination. Off-chip termination may introduce unwanted reflection due to the package parasitics. One way to implement termination resistor is to use transistors. Triode base transistor can be used as a termination resistor. Its linear range of operation can extended by adding a diode connected FET. In differential signaling, pass-gate terminator can be used. This structure provides accurate termination resistance at the extremes of common-mode voltage near power rails. These termination schemes are shown in Figure 10.

8 Figure 10 Active Termination Schemes [Dally] Pre-Lab 1. Please plot S 11 and S 21 for the circuit shown in Figura 11using Cadence. R T =50Ω. a. T d =0ps (no t-line), C 1 =0pF, L 1 =0nH, C 2 =1pF b. T d =0ps (no t-line), C 1 =1pF, L 1 =2nH, C 2 =2pF c. T d =100ps, C 1 =1pF, L 1 =2nH, C 2 =2pF R S Z o =50 L 1 + + + V in Port1 C C Port2 - - 1 2 - R T Figura 11 S-parameter Simulation Circuit 2. Please briefly compare the difference between AC and DC Coupled Termination schemes

9 Lab Questions 1. Channel Transient Simulation. The objective of this problem is to use measured channel s- parameter data to produce an impulse response and perform a transient simulation in Matlab involving sending random NRZ data across this channel. a. Download the s-parameter file for a 12 Backplane channel, peters_01_0605_b12_thru.s4p b. Use the matlab file read_sparam.m to produce an impulse response. Note this code requires the function xfr_fn_to_imp.m. c. Use the produced impulse response to perform transient simulations. Plot eye diagrams with 10k random bits at 2, 6.4, and 8Gbps. Example code for this is the file channel_data.m. d. Using peak distortion analysis generate the worst case bit pattern and plot the worst case eye at 6.4 and 8Gbps. In generating the worst case bit pattern, truncate the pulse response such that there are 10 pre-cursor samples and 100 post-cursor samples. 2. To use measured channel S-parameter data to produce a pulse response and perform a transient simulation in Cadence Use a 12 Backplane channel, peters_01_0605_b12_thru.s4p and transfer the file to ECEN689 directory where Cadence runs. Perform an impulse response simulation using an ideal 1V pulse (differential) with 1ps rise/fall time and 156.25ps pulse width. The channel needs to be terminated at both input and output. The pulse response can be obtained by measuring V out. The circuit setup is shown in Figure 12. Refer to appendix on how to use channel model in Cadence. a. Show your schematic and simulation results. R S1 R S2 Z o1 Z o2 + Vout R T1 - peters_01_0605_b12_thru.s4p R T2 Figure 12 Circuit Setup for Impulse Response b. Please perform transient simulation using a 7 bit PRBS input pattern at 2Gbps, 6.4Gbps, and 8Gbps. Please refer to the appendix for PRBS in Cadence.

10 c. Plot eye diagrams at these data rates using Cadence s Calculator. Please refer to Appendix on how to plot eye diagram. Peak Distortion Analysis. For the 1 bit pulse response as shown in 3. Figure 13. Please give the worst-case input bit pattern, assuming the ISI is zero for samples outside the plot range. Please give the worst-case eye height pattern. Figure 13 Pulse Response for Peak Distortion Analysis 4. Modulation Scheme. NRZ is the most commonly used modulation format. PAM-4 transmits 2 bits/symbol and half of the speed. Duobinary allows for controlled ISI resulting in less channel equalization. a. Please explain the difference between these two schemes. b. Assuming the channel loss at 2.5Ghz is 7dB and at 5Ghz is 14dB, which modulating scheme would have better voltage margin? c. Please solve the code based on the duobinary waveform shown in Figure 15.

11 Figure 14 NRZ and PAM4 Modulation Schemes Figure 15 Duobinary Coding [Smith, D.R.] 5. Termination Circuit. a. Please briefly list the pros and cons of these termination schemes: (a) Off-chip vs. on-chip (b) Series vs. Parallel (c) DC vs. AC coupling. b. Please design three 50ohm active terminations and characterize the resistance of these three active termination schemes as shown in Figure 10. However the both Fig 10 (a) and (b) have to be implemented by nmos version instead of pmos. Please sweep the input voltage from GND to VDD and show the resistance curve vs. input voltage. If 90nm technology is used, supply voltage is 1.2V.

12 Appendix How to use channel model in Cadence Channel symbol (n4port) can be found in analoglib. The s-parameter file should be specified including its directory path in S-parameter data file. It is shown in Figure 16. Figure 16 n4port property in Cadence The n4port can be used as shown in Figure 17. 4 of the 8 ports are return paths. Figure 17 n4port in impulse response setup

13 How to use PRBS generator in Cadence PRBS generator can be found in ahdllib. It is called rand_bit_stream. Please specify a PRBS generator as shown in Figure 18. Please set seed to 128 for 7 bit PRBS. Figure 18 PRBS Generator Property Figure 19 PRBS Sample

14 How to plot eyediagram in Cadence Calculator Figure 20 How to plot eyediagram in Cadence using Calculator Reference [1] Digital Systems Engineering, W. Dally and J. Poulton, Cambridge University Press, 1998. [2] Digital Transmission Systems, D.R. Smith, Boston Kluwer Academic Publishers, 1985.