Chapter 4 SOFT SWITCHED PUSH-PULL CONVERTER WITH OUTPUT VOLTAGE DOUBLER

61 Chapter 4 SOFT SWITCHED PUSH-PULL CONVERTER WITH OUTPUT VOLTAGE DOUBLER S.No. Name of the Sub-Title Page No. 4.1 Introduction 62 4.2 Single output primary ZVS push-pull Converter 62 4.3 Multi-Output Primary ZVS Push-Pull QRC.. 82 4.4 Single output Voltage Doubler ZVS-QRC Push-pull converter 86 4.5 Multi-output Voltage Doubler ZVS-QRC Push-pull converter. 96 4.6 Current fed push-pull converter 104 4.7 Analysis. 125 4.8 Cascoded Transformer Connection... 127 4.9 Conclusion.. 129

62 4.1 Introduction Resonance is introduced in the primary switching circuit of the push-pull converter to reduce the switching losses in hard switched converters operating at high frequencies. Soft switching push-pull converters used for powering applications like robotic arm motor, TTL logic circuits and CMOS circuits are presented in this chapter. Multioutput and voltage doubler are also introduced with detailed operating modes and design procedure. The design is validated through simulation and experimental results. 4.2 Single Output Primary ZVS Push-Pull Converter Primary ZVS push-pull converter is introduced in this section. Detailed explanation of circuit operation and design procedure are also presented. 4.2.1 Principle of Operation The ZVS push-pull converter is shown in Fig. 4.1(a). Lr1, Lr2, Cr1, Cr2 are resonant inductors and resonant capacitors respectively. The filter components are Lf and Cf. The circuit operation is explained in six modes under ideal conditions. Fig. 4.1(b) shows the waveforms of gate pulses for switches S1 (Vg1) and S2 (Vg2), resonant capacitor voltages and inductor currents respectively under ideal conditions [60].

63 (a) (b) Fig: 4.1 (a) Primary ZVS push-pull circuit (b) Idealized Waveforms 4.2.2 Modes of Operation The operation of the converter is explained in the following six modes. The assumptions made are: Magnetising inductance is larger than resonant inductor All semiconductor switches are ideal

64 Analysis is carried out at steady state Lossless capacitors and inductors Output filter capacitor value is assumed to be large Supply and load are maintained constant A. Mode 1 (t0 t t1): (Power Transfer Interval: Td1 = t1 t0) Switches S1 and S2 are OFF at time Td1. Diode D2 present in the secondary of the circuit is forward biased, while D1 is reverse biased. During this interval, power is transferred from primary to secondary. The conduction path and the operating region of the interval Td1 is highlighted in Fig. 4.2(a) and Fig. 4.1(b). It can be noticed from Fig. 4.1(b) that the resonant capacitor voltage Vcr1 is charging from 0 to 2Vdc and Vcr2 is discharging from 2Vdc to 0. Resonant inductor current ilr1 is maintaining its charge (constant current source) and resonant inductor current ilr2 is negatively charging. The equation governing this mode is consolidated with its initial and final conditions and is presented in Table 4.1. B. Mode 2 (t1 t t2): (Resonant Transition Interval 1: Td2 = t2 t1) When S2 is turned ON, the interval Td2 starts and S1 is in OFF state. D1 in the secondary circuit is forward biased whereas D2 is reverse biased. This period is called resonant transition interval 1 since the resonance of the converter begins in this phase.

65 Resonant inductor Lr1 and resonant capacitor Crl form the resonant circuit. In this interval, energy from the resonant inductor is transferred to the resonant capacitor, leading to the overcharging of the capacitor to a value of 2Vdc + ImZo/2. Conduction path and operating region of the interval Td2 are shown in Fig. 4.2(b) and 4.1(b). (a) Mode 1 (b) Mode 2 (c) Mode 3 (d) Mode 4 (e) Mode 5 (f) Mode 6 Fig: 4.2 Equivalent circuits of the ZVS PWM push-pull converter

66 At t = t2, ILrl value reaches zero and the voltage Vcrl reaches its peak value. Resonant inductor current, ilr1 discharges positively while ilr2 discharges negatively. C. Mode 3 (t2 t t3): (Resonant Transition Interval 1: Td3 = t3 t2) In interval Td3, S1 and S2 conditions are the same as that of mode 2 (S1 is OFF and S2 is ON). Secondary diodes D1 and D2 are forward and reverse biased respectively. As the resonance is maintained, this interval is also known as resonant transition interval 1. Fig. 4.2(c) shows the conduction path for the interval Td3. Fig. 4.1(b) shows the resonant capacitor voltages Vcr1 discharging from 2Vdc + ImZo/2 to 2Vdc and Vcr2 is 0. Resonant inductor currents are charged in opposite directions and energy transfer is same as that of the second interval. When voltage across the resonant capacitor VCr = 2Vdc, resonance between Lr and Cr ends. D. Mode 4 (t3 t t4): (Power Transfer Interval: Td4 = t4 t3) In the fourth interval Td4, both S1 and S2 are OFF, D1 is forward biased and D2 is reverse biased in the secondary. This mode also transfers power similar to mode 1. The conduction path for the interval Td4 is shown in Fig. 4.2(d). The resonant capacitor voltage Vcr1 discharges from 2Vdc to 0, Vcr2 charges from 0 to 2Vdc. In this interval, resonant inductor current ilr1 increases negatively but the resonant inductor current ilr2 remains constant.

67 Table 4.1 Mode equations Mode Formula Initial Condition Final condition ( ) =, ( ) ( ) Mode 1 ( ) ( ) Vcr2 = 2Vdc ( ) ( ) ( ) ( ) ( ) ( ) ( ) ILrl( ) Mode 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) Mode 3 ( ) ( ) ( ) ( ) ; ( ) ( ) ; ( ) ( ) ( ) ( ) ( ) Mode 4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )

68 ( ) ( ) ( ) ( ) ( ) ( ) ( ) Mode 5 ( ) ( ) ( ) ( ) [ ] ( ) ( ) ( ) ( ) Mode 6 [ ] ( ) ( ) ( ) ( ) ( ) E. Mode 5 (t4 t t5): (Resonant Transition Interval 2: Td5 = t5 t4) In interval Td5, S1 is ON and S2 is OFF, D2 is forward biased and D1 is reverse biased in the secondary. This mode is called resonant transition interval 2. Fig. 4.2(e) shows the conduction path while Fig. 4.1(b) details the charging of Vcr2 from 2Vdc to (2Vdc + ImZo/2) and Vcr1 = 0. The resonant inductor current ilr1 decays to zero towards positive and decays to zero towards negative. F. Mode 6 (t5 t t6) (Resonant Transition Interval 2: Td6 = t6 t5) In interval Td6, S1 is ON and S2 is OFF. The secondary working is same as that of the previous mode. This mode is also known as resonant

69 transition interval 2. The conduction path and the region of operation are shown in Fig. 4.2(f). Resonant capacitor voltage Vcr1 is 0 and Vcr2 discharges from 2Vdc + ImZo/2 to 2Vdc as shown in Fig. 4.1(b). Resonant inductor current, ilr1 charges positively and ilr2 charges negatively. When the sixth mode ends, a new cycle repeats. 4.2.3 Design The specifications and the design aspects of the power supply are discussed in detail in this section. 4.2.3.1 Specifications Converter Specifications: Switching frequency (fs) = 50 khz Input Voltage (Vdc) = 15 V = 0.4 Resonant frequency (f0) = 125 khz DC Motor Specifications: Output power (Po) = 5 W Output Voltage (Vo) = 5V Output Current (Io) = 1A Speed = 95rpm Torque = 0.5Nm

70 4.2.3.2 Converter Design The design of 5W, 50 khz ZVS push-pull converter is given below: Voltage conversion ratio, M = 0.2898 = 0.39 (max value of M is chosen) Where, Vsmin and Vsmax are minimum and maximum supply voltages respectively. Magnetizing current, ( ) = 1.39 (4.1) i) Resonant Condition Condition for ZVS is ; 21.47 = 25 Ω (chosen) Characteristic impedance, (4.2) Resonant frequency, = ii) Resonant component calculation Resonant frequency, (4.3) Resonant capacitor, = 0.048 = = Resonant inductor, = 45 = = Angular resonant frequency, (4.4)

71 iii) Filter inductor and Capacitor design Cut-off frequency, Filter capacitor, = 220 Filter inductor, = 4.7 4.2.3.3 Transformer and Inductor Design Design of transformer and inductors are carried out as per the design elaborated in section 3.3.1.4 and the results obtained are tabulated in Table 4.2. Parameters Np = 12 Table 4.2 Transformer and Inductor design details Core selected Transformer design From Appendix I : core - EE 20/10/5,, From Appendix II : SWG = 28 ( ), SWG =24 ( ) Resonant Inductor Design From Appendix I : core - EE 20/10/5,, From Appendix II : SWG =19 ( ) Filter Inductor Design,, From Appendix I : core - EE 20/10/5 From Appendix II : SWG=24 ( ) 4.2.3.4 Motor speed calculation The motor specifications (section 4.2.3.1) reveal that the motor develops a torque of 0.5Nm for an input power of 5W.

72 Torque = 0.5 Nm The motor used in robotic applications has less inertia, negligible iron and friction losses. For this lossless machine, power input = power output. Output power of the converter (Po) = Input power to the motor = 5W Motor Power output = Torque * Speed in rad/sec Therefore, Speed = 5 /0.5 = 10 rad/sec = 95.5rpm The simulation and hardware results of the converter with this robotic arm motor specification are explained in sections 4.2.4 and 4.2.6.2 respectively. 4.2.4 Open-loop Simulation Results The simulation was carried out with the designed values and the circuit diagram of the simulated circuit for a robotic arm application is shown in Fig. 4.3(a). The resonant waveforms obtained, illustrated in Fig. 4.3(b), are similar to the theoretical waveforms shown in Fig. 4.1(b). The figure clearly confirms ZVS turn ON for both switches. It is further observed that the peak resonant capacitor voltage across each switch is 45V and 42V respectively. The output voltage 5V, output current-1a and speed of 98rpm obtained, is shown in Fig. 4.3(c). Thus the simulation confirms that the converter is well suited for powering a robotic arm controlled by a motor of 5W, 0.5Nm, 10rad/sec specifications.

73 (a) (b) (c) Fig: 4.3 Primary ZVS Push-pull QRC fed servo motor (a) Simulation circuit (b) Resonant waveforms (c) Motor inputs and outputs 4.2.5 Closed loop Simulation Results The closed loop simulations are carried out for electronic PI controller and Enhanced PID Controller and the results obtained are discussed in this section for a single output converter.

74 4.2.5.1 Electronic PI Controller The designed primary ZVS push-pull converter is simulated in PSIM for the specifications stated in section 4.2.3.1. A PI Controller has the properties of P and I controllers and is widely used in DC DC converter fed servo control applications. The equation which describes PI controller is, u(t) = KP e(t) + KPKI e(t) dt (4.5) Where, u(t) output signal, e(t) error input, KP proportional constant, KI integral constant. Proportional controller is described by the value of its proportional gain Kp. The integral term of a PI controller varies the output as long as there is a non-zero error. Therefore such a controller can eliminate even a small error. An electronic PI controller designed for the primary ZVS push-pull converter with OP-AMPs is shown in Fig. 4.4(a). The circuit comprises of a difference amplifier, PI Controller, non inverting amplifier and a PWM generator. The design equations are as given below: For P Proportional Controller, output voltage Vo = Ve (4.6) For I Integral Controller, output voltage Vo = dt (4.7) The effect on the load change is depicted in Fig. 4.4(b). From the figure it is clear that, for the load change applied at 1.5 seconds, the output

75 voltage is regulated and its corresponding change is observed in the current waveform. Fig. 4.4(c) shows the resonant waveforms, which is similar to the theoretical waveforms in Fig. 4.1(b). (a) (b) (c) Fig: 4.4 ZVS Push-pull converter using PI Controller (a) Closed loop simulation circuit (b) Output waveforms (c) Resonant waveforms 4.2.5.2 Enhanced PI Controller (EPI) Closed loop simulation is carried out with PID, PI, EPID and EPI controllers to analyse the performance of the controllers. The error,

76 which is the difference between the measured output voltage and the desired set point, is fed to the PID controller. The controller processes the error and produces output which further reduces the error. Based on the nature of the system, the proportional, derivative and integral constants are chosen. The constants chosen react on the present error, cumulative errors and rate of change of error, respectively. The controller output is the weighed sum of all these three actions. The output is variable in nature, which in turn varies the pulse width of the PWM thus controlling the switch. The enhanced constants b and c of the Enhanced PID controller (EPID) helps in improving the performance of the controller by reducing the peak overshoot and settling time of the output, without affecting the PI parameters. The value of the enhanced constants varies between 0 and 1. Fig. 4.5(a) and (b) reveal the PSIM simulation diagram of the PID and EPID controlled converter. The closed loop output response of the EPID controller for 2Ω change (both increase and decrease) is shown in Fig. 4.5(c) and (d) respectively. From the figures, it is observed that the voltage is regulated at the rated value for both increase and decrease in load, and Table 4.3 gives the comparison of various controllers with respect to peak time, settling time etc. Observations are carried out for a load variation of ±50% and the resonant waveforms for the same are as shown in Fig. 4.6(a) and (b).

77 (a) (b) (c) (d) Fig: 4.5 Closed loop simulation circuit of ZVS Push-pull converter using (a) PI Controller (b) EPID Controller (c) & (d) Output voltage and current for ± 20% load variation with EPID controller. The equations governing the controllers are: PID Controller, ( ) ( ) ( ) EPI Controller, ( ) ( ) EPID Controller, ( ) ( ) ( ) Efficiency = ( ) ( ) (4.8) Where, P - Controller output, Ysp - desired set point, Y - Measured output voltage, KD - differential constant, b and c are enhancement

78 constants, ( ) - error input e(t), ( ) &( ) are the average output and input voltages and currents respectively. (a) (b) (c) Fig: 4.6 Voltage and current waveforms for load change within ± 50% with EPID controller (a) Switch-1 (b) Switch-2 (c) Efficiency graph. It is observed that the shape of the resonant voltage and current waveforms prevail throughout the ±50% load changes and the peak voltage and current are in the range of 45V to 50V and 0.8 to 0.9A. The

79 efficiency graphs shown in Fig. 4.6(c) are plotted for an input voltage of 14V, 15V and 16V and the maximum efficiencies (equation 4.8) noted from the graphs is 84.54%, 85.53% and 86.16% at 5W output power respectively. Table 4.3 Time domain analysis Parameters Controllers PID EPID EPI PI Before Load Change Peak time (tp in msec) 0.370 0.326 0.352 0.353 Peak Overshoot (V) 5.216 5.213l 5.213 5.215 Settling time (ts in sec) 0.223 0.190 0.19 0.190 After load change Peak Overshoot (V) 5.932 5.932 5.988 5.978 Peak time (tp in msec) 0.049 0.0366 0.039 0.0366 Settling time (ts in sec) 7.96 7.9276 8.17 8.37 A comparison Table 4.3 is tabulated for analysing the closed loop response of PID, PI, EPID and EPI controllers. From the table it is obvious that the response of EPID have less peak time, settling time, less overshoot and faster response. Therefore, it is the best option for switched mode power supplies with stringent regulation. The enhanced coefficients introduced improve the dynamic response of the system by reducing the error at a faster rate. The standard power supply data sheet for avionics, mobile, ground systems and other applications are given in Appendix VI and the important parameters are listed in Table 3.4. The inference from standard military power supply table 3.4 is load overshoot: 400mV. While that obtained from EPID controller is 932mV; comparing these

80 values it is clear that the overshoot is large in the EPID controller output and could be reduced by tuning the EPID constants values. 4.2.6 Experimental implementation The designed converter is implemented in hardware and the implementation particulars are detailed below. 4.2.6.1 PWM Generation The pulses for the switches are generated from DSPIC30f4011. TTL of 0-5V is used by typical logic systems such as micro controllers. TTL s cannot supply enough current to switch a high power MOSFET ON and OFF. In order to perform high speed switching most MOSFET s are activated with pulses of amplitude 12-20V and with a higher current. Hence, a MOSFET driver is an essential interface between logic system and MOSFET. The pulses are amplified to a range of 12V to 15V and isolated before being fed to the switches with the help of an opto-coupler cum driver IC TLP250 as shown in Fig. 4.7. Fig: 4.7 Gating Pulse from opto-coupler IC TLP250

81 4.2.6.2 Power circuit Results Fig. 4.8(a) and (b) show the resonant capacitor voltages (VCr1-pk = 46V, VCr2-pk = 37.8V) with gate pulses of switches S1 and S2. For a rated supply voltage of 15V and load resistance of 5Ω the output voltage (4.8V) and output current (1A) of the ZVS push-pull converter obtained is presented in Fig. 4.9(a) and (b) respectively. The complete hardware set up of the converter is represented in Fig. 4.9(c). (a) (b) Fig: 4.8 (a) Resonant capacitor-1 voltage with gate pulse-1 (b) Resonant capacitor-2 voltage with gate pulse-2 (a) (b) (c) Fig: 4.9 (a) Output voltage and current (b) Supply voltage and current (c) Hardware setup The ripples observed in Fig 4.9(b) are due to the combined effect of supply voltage ripples at 100Hz (push-pull converter has full wave

82 rectification at output (i.e.) 100Hz) and switching frequency ripples at 50 khz. This could be eliminated by adding a filter at the input of the converter. 4.3 Multi-Output Primary ZVS Push-Pull QRC To increase compactness, the primary resonant converter dealt above is implemented for multi-output operations. The operation and design procedure of a 6.2W, 50kHz multi-output primary ZVS push-pull converter is explained in this section. In order to validate the design procedure, the simulation and experimental results are presented and analysed in detail. 4.3.1 Principle of Operation The multi-output ZVS push-pull converter is shown in Fig. 4.10. The resonant inductors and resonant capacitors are Lr1, Lr2 and Cr1, Cr2 respectively and filter components are Lf and Cf. Primary resonance is similar to single output topology; with 6 modes, the ideal operation of the circuit is same as explained in section 4.2.2. Fig: 4.10 ZVS multi-output push-pull circuit

83 The waveforms for switch pulses for S1 and S2, resonant capacitor voltages and resonant inductor currents are same as illustrated in Fig. 4.1(b). 4.3.2 Design The design procedure is same as explained in section 4.2.3. The design parameters for primary ZVS multi-output converter are described in this section. 4.3.2.1 Specifications Switching frequency (fs) = 50kHz Output power (Po) = 6.2W Input Voltage (Vdc) = 15 V Output Voltage-1(Vo) = 2V Output Current-1(Io) = 0.6A Output Voltage-2(Vo) = 10V Output Current-2(Io) = 0.5A 4.3.2.2 Converter Design The design parameters required for the multi-output converter is same as that explained in section 4.2.3.2. 4.3.2.3 Transformer and Inductor Design The design of the transformer, resonant inductor and filter inductor are same as explained in section 4.2.3.3 and the results

84 obtained are same as tabulated in Table 4.2, except for the secondary turns in the transformer (i.e) number of turns in secondary-1 is 7 and secondary-2 = 14 4.3.3 Open-loop Simulation Results With the designed values the converter is simulated in PSIM software and the simulation results are analysed in this section for a resistive load. The two output voltages obtained 2.1V and 10V at rated supply (15V) and load condition (7Ω & 20Ω), are as shown in Fig. 4.11(a). The two resonant capacitors peak voltages and currents obtained are 60.10V and 1.93A, 55.29V and 1.46A respectively and are shown in Fig. 4.11(b).. (a) (b) Fig: 4.11 (a) Output voltages and currents (b) Resonant waveforms 4.3.4 Experimental Results Fig. 4.12 and 4.13 show the hardware implemented waveforms of the designed converter. Fig. 4.12(a) and (b) show the resonant capacitor

85 voltages (VCr1-pk = 19.4V, VCr2-pk = 17.8V) with the gate pulse of both the switches S1 (39.5%) and S2 (41.3%). The output voltage-1 (1.9V), current1 (638mA), voltage-2 (10.1V) and current-2 (531mA) of the ZVS push-pull converter are shown in Fig. 4.12(c) and 4.13(a), and the complete hardware set up of the converter is shown in Fig. 4.13(b). The ripples observed in output voltage and current (Fig 4.12(c)) are due to the combined effect of ESR and ESL of the output electrolytic capacitor. This can be reduced by adding a non-electrolytic capacitor (0.47µF) at the output of the converter. (a) (b) (c) Fig: 4.12 (a) and (b) Resonant capacitor voltages with corresponding gate pulses (c) Output-1 voltage and current. (a) (b) Fig: 4.13 (a) Ouput-2 voltage and current (b) Hardware Setup.

86 The converters explained in sections 4.2 and 4.3 deals with the resonance in the primary circuit alone, while the secondary diodes experience high surge due to transformer leakage inductance. This issue is addressed in the next section. 4.4 Single Output Voltage Doubler ZVS-QRC Push-Pull Converter The primary resonant converters dealt in the above two sections for single and multi-output converters do not engross energy stored in the leakage inductance which appear as voltage stress in the secondary diodes; hence resonance is introduced in the secondary circuit to reduces the losses in the passive switches. This resonant circuit also serves the purpose of voltage doubling at the output, thus increasing the voltage at the output with less component count. 4.4.1 Voltage Doubler Circuit It is an electronically controlled circuit which charges the capacitor from input voltage through switches. The advantages of this circuit are - it is more adaptable to changes, easy to implement, economical and can obtain an output which is an odd or even multiple of the input voltage. The basic doubler circuit is shown in Fig. 4.14(a). The advantages are: It clamps the voltage stress on secondary diodes D1 and D2 to V0. The rectifier does not need a RC snubber and hence it can obtain a high efficiency and low noise output voltage.

87 The conduction loss can be minimized by including a rectifier diode of low voltage rating, which leads to simplified structure. (a) (b) Fig: 4.14 (a) Voltage doubler circuit (b) Circuit diagram of the push-pull ZVS-QRC with output voltage doubler. 4.4.2 Principle of Operation The circuit diagram of the ZVS push-pull QRC with secondary voltage doubler is as shown in Fig. 4.14(b). The primary circuit working is similar to the primary ZVS push-pull QRC, as explained in section 4.2, with an added feature of secondary ZCS in the rectifying diodes (D1 and D2). The switches (S1 and S2) are switched ON one after the other, so that the transformer does not saturate but is excited in both the directions, hence increasing the transformer utilization factor. The magnetizing inductance is assumed to be large so as to maintain continuous conduction even at light load conditions. The resonant circuit is formed with resonant inductors (Lr1 & Lr2) and resonant capacitors (Cr1& Cr2) to achieve ZVS in the main switches. The theoretical waveform [60] is as presented in Fig. 4.15.

88 4.4.3 Modes of Operation The CCM operation of the converter is explained in 6 modes as illustrated in Fig. 4.16(a) (f). The assumptions were discussed earlier in section 4.2.2. A. Mode 1 (t0 t t1): (Power Transfer Interval: Td1 = t1 t0) Upper limb: Mode 1 starts with an initial condition of ILr1 = Im/2. During this interval (Td1), the main switches are in the OFF condition. The resonant inductor acts as a constant current source with some initial charge and charges the resonant capacitor voltage from 0 to 2VS. The diode D2 in the secondary is forward biased while D1 is reverse biased. Power is transferred from primary to secondary and charges the secondary resonant capacitor. The filter capacitor supplies the load. Lower limb: Same as the working of the upper limb in mode 4. The energy stored in the transformer leakage inductance is discharged to charge the secondary resonant capacitor. B. Mode 2 (t1 t t2): (Resonant Upper Transition Interval 1: Td2 = t2 t1) Upper limb: The initial conditions for this interval (Td2), are Vcr1(0) = 2VS, ILr1(0) = Im/2. This mode begins when S2 is turned ON, S1 is OFF and diodes D1 and D2 are forward biased and reverse biased respectively. The resonant capacitor is charged by the resonant inductor to (2VS + ImZo/2) from 2VS for a duration of Td2/2. The overcharged capacitor in turn

89 charges the resonant inductor in the reverse direction for the remaining Td2/2 duration. This interval is called resonant upper transition interval 1, as resonance occurs in this mode. This mode ends when the resonant capacitor voltage reaches 2VS. Lower limb: Working is same as upper limb in mode 5. The secondary circuit is the same as in the mode explained before. Fig: 4.15 Idealised resonant waveforms of primary ZVS push-pull converter with output voltage doubler C. Mode 3 (t2 t t3): (Resonant Upper Transition Interval 1: Td3 = t3 t2) Upper limb: The initial conditions for this mode are Vcr1(0) = 2VS. During this interval (Td3), S1 is OFF and S2 is ON, diode D1 is forward biased and

90 diode D2 is reverse biased. The resonant capacitor discharges and Vcr1 decreases from 2Vs to 0. Resonant inductor current, ilr1 increases linearly from a negative value at t = t2 and reaches -Im/2 at t = t3. Energy transfer from resonant capacitor to resonant inductor is observed in this mode. Lower limb: Working is the same as that of upper limb in mode 6. The energy stored in the capacitance is discharged back to the transformer secondary and the load. D. Mode 4 (t3 t t4): (Power Transfer Interval: Td4 = t4 t3) Upper limb: The initial conditions for this mode are Vcr1(0)=0 and ILr1(0) = -Im/2. In this interval (Td4), S1 and S2 are OFF; D1 is forward biased while D2 is reverse biased. This interval is similar to mode 1 and is known as power transfer interval. The resonant capacitor voltage Vcr1 is 0 during this period and the resonant inductor current ilr1 discharges negatively through the switch diode. Lower limb: Its working is same as that of upper limb in mode 1. The energy stored in the transformer leakage inductance is discharged to the load, charging the secondary resonant capacitor in the negative direction. E. Mode 5 (t4 t t5): (Resonant Lower Transition Interval 2: Td5 = t5 t4) Upper limb: The initial condition for this mode is ILr1(0) = -(Im/2)cosα. In this interval (Td5), S1 is turned ON and S2 is OFF, D2 is forward biased and D1 is reverse biased. Resonant inductor current ilr1 decreases linearly, reaches 0 and charges positively; hence it is known as resonant

91 lower transition interval 2. As the lower limb resonance ends, mode 5 terminates. Lower limb: Primary circuit working is similar to that of the upper limb in mode 2. The secondary circuit works in the same manner as in mode 4. (a) Mode 1 (b) Mode 2 (c) Mode 3 (d) Mode 4 (e) Mode 5 (f) Mode 6 Fig: 4.16 Modes of operation

92 F. Mode 6 (t5 t t6) (Resonant Lower Transition Interval 2: Td6 = t6 t5) Upper limb: In interval (Td6), switch S1 is turned ON and S2 is OFF, D2 is forward biased and D1 is reverse biased. Voltage across the resonant capacitor Vcr1 = 0, resonant inductor is positively charged and its corresponding current ilr1 increases linearly from a positive value at t = t5 to Im/2 at t = t6. Lower limb: Working is same as the upper limb of mode 3. The energy stored in the capacitance is discharged back to the secondary circuit. The next cycle starts and same operation continues at the end of this mode. 4.4.4 Design The specifications and the design aspects of the power supply are discussed in this section. 4.4.4.1 Specifications Switching frequency (fs) = 50kHz Output power (Po) = 1.32W Input Voltage (Vdc) = 15 V Output Voltage (Vo) = 3.3V Output Current (Io) = 400mA = 0.4

93 4.4.4.2 Converter Design The design of 1.32W, 50kHz ZVS push-pull converter with secondary voltage doubler is as given below: Voltage conversion Ratio, M = 0.191 = 0.26 (max value of M is chosen) Magnetizing current, ( ) = 1.26 This design is similar to the design explained in section 4.2.3; the designed values are: = 0.048, = 45, = 220, = 4.7. 4.4.4.3 Transformer and Inductor Design The design of the transformer, resonant inductor and filter inductor is carried out. The design is same as explained in section 4.2.3.3 and the results obtained for the inductors are same as tabulated in Table 4.2, while that for the transformer is tabulated in Table 4.4. Table 4.4 Transformer design Parameters Np = 12Turns Core selected From Appendix I : core - EE 20/10/5,, From Appendix II : SWG = 28 ( ) SWG =24 ( )

94 4.4.5 Open-loop Simulation Results Open loop simulation of the converter shown in Fig. 4.14(b) is carried out in PSIM. The obtained output voltage (3.3V) and current (400mA) are shown in Fig. 4.17(a) for rated supply (15V) and load conditions (8Ω). The peak voltage (78V) across both the resonant capacitors is as shown in Fig. 4.17(b). It can be observed that it is similar to that of the theoretical waveform shown in Fig. 4.15. It also confirms the turn ON ZVS in the active switches. The peak voltage across the rectifier diodes are VD1 = VD2 = 5V and the rectifier diode peak currents are id1 = id2 = 3A as shown in Fig. 4.17(c). From this, it is observed that there is no oscillation or voltage spike on the rectifier diodes. (a) (b) (c) Fig: 4.17 Simulation waveforms of (a) Output voltage & current (b) Resonant capacitor voltages with gating pulses (c) Diode current & voltages 4.4.6 Experimental Results A prototype converter with 1.32W output power (3.3V, 400mA) is developed to verify the operating principle of the single output ZVS-QRC

95 Push-pull converter with voltage doubler. The different devices used in the converter are: S1 and S2: IRF840, D1 and D2: Fast recovery schottky diodes BA159 (Detailed in Appendix-IV), dspic30f4011 is used for generating pulses, Driver cum isolator: TLP 250 (Detailed in Appendix-V). Fig. 4.18 shows the experimental results for full load condition. The nominal converter output voltage (VO), current (IO) are as shown in Fig. 4.18(a) and the gating pulses derived from driver circuit are as shown in Fig. 4.7. Fig. 4.18(b) & (c) present the resonant capacitor voltages Vcrl and Vcr2. (a) (b) (c) Fig: 4.18 (a) Output voltage & current (b) & (c) Resonant capacitor voltages with gating pulses From the figure it is observed that the switches S1 and S2 are turned ON when voltages Vcrl and Vcr2 become zero respectively. Also it is observed that these waveforms are similar to the theoretical waveforms shown in Fig. 4.15 and the simulated waveform shown in Fig. 4.17(b). The rectifier diode currents id1 and id2 are also obtained and it is observed that it does not have any oscillation or voltage spikes. The

96 pulses obtained from the DSPIC30f4011 is isolated and amplified in the opto-coupler circuit to 12.4V approximately. This pulse triggers the voltage controlled device (MOSFET IRF840). The resonant capacitor voltage obtained for switch- 1& 2 are 60V and 62V respectively, while in simulation it is 78V for both capacitors. This difference in voltage magnitude between the simulation and hardware results is due to the fact that the devices and capacitors used in the simulation are ideal. The switching frequency of the prototype is 50kHz and therefore the size of the components used is reduced to ¼ th the original size. 4.5 Multi-Output Voltage Doubler ZVS-QRC Push-Pull Converter This section discusses the multi-output ZVS push-pull converter with a secondary voltage doubler. This converter further adds the advantage of compactness and multiple isolated outputs to the single output converter mentioned in section 4.4, by adding one extra winding to the secondary of the transformer. Operation of the circuit is explained in detail and the design procedure is also presented. The closed loop hardware results obtained are also discussed. 4.5.1 Principle of Operation Fig. 4.19 shows the designed ZVS multi-output push-pull converter with secondary voltage doubler. Lr1, Lr2 and Cr1, Cr2, Cr3, Cr4

97 are resonant inductors and resonant capacitors respectively. Lf1, Lf2 and Cf1, Cf2 are the filter components. Resonance occurs on both sides of the converter; namely: in primary between (Lr1 & Cr1) and (Lr2 & Cr2), in secondary-1 between the magnetizing inductance of secondary-1 & Cr3, and in secondary-2 between magnetizing inductance of secondary-2 & Cr4. Fig: 4.19 ZVS multi-output quasi resonance push-pull converter with output voltage doubler 4.5.2 Modes of Operation Idealized operation and waveforms of the multi-output circuit is similar to single output converter explained in section 4.4.3 and is depicted in Fig. 4.15. 4.5.3 Design Specifications and the design aspects of the power supply are discussed in this section.

98 4.5.3.1 Specifications Switching frequency (fs) = 50kHz Output power (P0) = 3.6W Input voltage (Vdc) = 15±15% Output voltage-1 (V01) = 5V Output current-1 (I01) = 0.5A Output voltage-2 (V02) = 3.3V Output current-2 (I02) = 0.33A 4.5.3.2 Converter Design Sample design of 3.6W, 50 khz multi-output ZVS push-pull converter is listed below: Magnetizing current, Im = I0 (M+1) = 0.745A i) Resonant Condition The design is similar to the design details explained in section 4.2.3. Using equation (4.2), the characteristic impedance is calculated as Z0 = 40. ii) Resonant component calculation Using equations (4.3) and (4.4), the resonant components are calculated as - resonant capacitor Cr = 0.33µF and resonance inductor Lr = 60µH. iii) Filter inductor and Capacitor design It is similar to the design explained in section 4.2.3.2 and the designed values are: filter capacitor Cf = 220µF and filter inductor Lf = 10µH.

99 4.5.3.3 Transformer and Inductor Design Design of the transformer and inductors are carried out as per the design elaborated in section 3.2.1.4 and the results obtained are tabulated in Table 4.5. Table 4.5 Transformer and Inductor design details Parameters Core selected Transformer design Np = 8 From Appendix I : core - EE 20/10/5,, From Appendix II : SWG =29 ( ), SWG =35 ( ), SWG =27 ( ) Resonant Inductor Design E = 235 10-6 J From Appendix I : Core EE 25/9/6 a 0.44 mm 2 AP = 3120mm 4, Ac = 40mm 2, Aw = 78mm 2 N 14 turns From Appendix II : SWG = 21 (a= 0.51890 mm 2 ) a 0.5234mm 2 N 6 turns 4.5.4 Simulation Results Filter Inductor Design From Appendix I : Core- EE 22/10/5 AP = 1418mm 4, Ac = 31mm 2, Aw = 47.8mm 2 From Appendix II : SWG = 20 (a= 0.65670 mm 2 ) The simulation of the circuit is carried out in PSIM and the simulated waveforms for the converter are revealed in Fig. 4.20 and Fig. 4.21. The resonant voltages and currents obtained are displayed in Fig. 4.21(a) & (b) while the output voltage and current obtained (5V, 0.5A) and (3.3V, 0.33A) are exhibited in Fig. 4.20. The secondary diode currents and voltages are illustrated in Fig. 4.21(c).

100 (a) (b) Fig: 4.20 Output voltages and currents 4.5.5 Experimental Results Hardware implementation of multi-output push-pull converter is carried out for both open loop and closed loop with controller IC UC3825. The results obtained from the hardware implementation are presented and discussed in detail. (a) (b) (c) Fig: 4.21 (a) Primary resonant waveforms (b) Secondary resonant waveforms (c) diode waveforms

101 4.5.5.1 PWM Controller The pulses obtained from opto-coupler circuit have a frequency of 50kHz and a duty ratio of 40%. Peak voltage of the obtained pulses is found to be 14V. The duty ratio and frequency remains the same as obtained from IC UC3825. The implementation details and design of the IC components are same as explained in sections 3.4.1 to 3.4.3 and the pulse obtained is same as shown in Fig. 3.8. 4.5.5.2 Rated output condition Open loop hardware implementation results (5V, 0.5A), (3.3V, 0.33A) of multi-output push-pull converter with voltage doubler at rated load conditions are as shown in Fig.4.22 (a) and (b) respectively. The output voltages obtained (5V, 3.3V) and the hardware prototype developed is shown in Fig. 4.23. The distortions in Fig.4.22 (a) and Fig.4.23 (a) are due to the presence of ESR and ESL in the output electrolytic capacitor and can be reduced by adding a non-electrolytic capacitor (47 µf) at the output. (a) (b) Fig: 4.22 (a) First Output voltage and current (I01) (b) Second output voltage and current (I02)

102 (a) (b) Fig: 4.23 (a) Both output voltages (b) Open loop Hardware Prototype. (a) (b) Fig: 4.24 Waveforms of switch-1 pulse, Vcr1 and switch-2 pulse, Vcr2. The resonant capacitor voltages with the corresponding gating pulses are illustrated in Fig. 4.24(a) and (b). From the figure it is observed that the peak capacitor voltages 1 and 2 are 58V and 66V respectively. It is observed that when the voltage across the capacitor crosses zero, the switches are turned ON which reduces the switching losses and thereby increases the efficiency. 4.5.5.3 Line transients The output voltages for ±15% supply voltage variation are shown in Fig. 4.25. It was observed that the 5V output is regulated by the PWM controller IC UC3825 and the voltage variation in the other output is recorded. The regulated and unregulated voltages for the supply variation

103 are as shown in Fig. 4.25(a) and (b). From the results, it is observed that only output-1 (5V/500mA) is regulated for all line changes applied because of the feedback loop provided from output-1 to UC3825. The change in output voltage 1 and 2 from the desired value is calculated to be 125mV (5V- 4.875V) and 1.2V (3.6V-2.4V) respectively. The regulation of the regulated output is within the standard specification range (150mV) as specified in Table 3.4, while that of output-2 is above the standard range. This could be overcome by regulating load-2 by a post regulator IC UC3834 as discussed in the latter section 5.3.4. (a) (b) Fig: 4.25 Output voltages for supply voltage (a) Decrease (b) Increase 4.5.5.4 Load transients Closed loop implementation of multi-output push-pull converter for load transients are presented and discussed in this section. The output voltage waveforms for both the load variations (increase and decrease) are presented in the Fig. 4.26. The load regulation waveforms for ±20% load variations are presented in Fig. 4.26(a) and (b) respectively. In open loop implementation, both the output voltages are observed to vary when the load resistance is varied, but for closed loop, that is, in

104 Fig. 4.26, the regulated output is almost constant for load variation. From the results it is observed that output-1 is regulated for the load changes applied because of the feedback loop provided in UC3825, whereas the unregulated second output voltage varies with the load variations. The load voltages were observed for ± 20% variations in load- 1 and the waveforms obtained are as shown in Fig. 4.27.(b) (a) (b) Fig: 4.26 Output voltages for second load resistance (a) decrease (b) increase (a) (b) Fig: 4.27 Output voltages for first load resistance (a) decrease (b) increase 4.6 Current fed push-pull converter The current fed converters are dual to the voltage fed converters, where the input voltage is transformed to a constant current source with

105 the help of a high valued inductance added in series with the voltage source. This inductor added at the input side does not increase the component count in the converter as the necessity of filter inductor at the output of the voltage fed converter is removed. This section deals with the current fed push-pull converter that operates with ZVS. The converter is designed to operate at high switching frequency and a zero voltage switching technique is used to reduce the losses associated with high operating frequency. A 4.7W, 50 khz current fed ZVS push-pull converter is chosen. The operating modes of the circuit, design and experimental implementations are explained in detail. 4.6.1 Principle of Operation Fig. 4.28 shows the ZVS current fed push-pull converter. Two transformers - one main and another auxiliary, through which the regulation principle is applied, are put to use in the circuit diagram. Li and Ctun are the current fed inductor and the resonant capacitor respectively. Lm and Llk are the magnetizing and leakage inductances of the main transformer respectively. Cout is the output filter capacitor; LB and CB are the (auxiliary boost converter) inductor and capacitor respectively. For achieving ZVS, parasitic elements such as, transformer leakage inductance and MOSFET internal capacitance, are used in the resonant circuit. Hence, by maintaining ZVS, switching losses can be reduced. The regulating transformer is connected to the additional

106 secondary winding of the main transformer. Variable control voltage is imparted by the auxiliary converter through the auxiliary switch. Based on the variation in the output voltage, the duty cycle of the switch is varied by the error detector, compensator and comparator circuit. The current equivalent to the control voltage is in turn given back to the input and hence the desired regulation is achieved. Fig: 4.28 Converter Circuit diagram 4.6.2 Modes of Operation The converter operates in four different modes. Mode 1 and Mode 3 are power transfer intervals, while mode 2 and mode 4 are zero power transfer regions. Once the converter is rightly tuned for constant

107 frequency and fixed duty cycle, all the switches work in a resonant fashion. The operational waveforms [89] are displayed in Fig. 4.29. A. Mode 1 Switch S1 is turned ON at zero voltage so that switching losses are reduced. Ctun and the leakage inductance of the main transformer form a resonant tank. Hence, when the switch is turned ON, the current increases in a resonant fashion. This causes a half sinusoidal current flow through the closed circuit formed by source S1 and magnetizing inductance in primary circuit; while in the secondary, the closed circuit is formed by D1/D3, load and secondary winding. During this instant, the parasitic capacitance of S2 (Cds2) is charged to twice of the Ctun voltage. The magnetizing inductance (Lm) of the main transformer is charged. The transformer turns ratio regulation is applied through the regulating transformer as well as diode D3. The circuit diagram for mode 1 operation is presented in Fig. 4.30(a). B. Mode 2 When the current through S1, D1 and D3 falls to zero, the switch S1 is turned OFF to achieve zero current switching. The energy stored in the magnetizing inductance (Lm) discharges the parasitic capacitance of S2 (Cds2). Therefore, the parasitic capacitance of S1 (Cds1) is charged with a constant current. In this mode, all the diodes are OFF, there is no transfer of energy from the input to the output and Ctun is charged by the

108 supply current Iin. The circuit diagram for mode 2 operation is displayed in Fig. 4.30(b). Fig: 4.29 Theoretical waveforms C. Mode 3 The switch S2 is turned ON at zero voltage so that switching losses are reduced. During this period, the current through the switch increases in a resonant fashion because Ctun and leakage inductance of the main transformer form a resonant tank. Thereby, a half sinusoidal current flow through the closed circuit is formed through source S2 and magnetizing inductance in primary circuit; while in the secondary, the closed circuit is formed by D2/D4, load and secondary winding. The parasitic capacitance of S1 (Cds1) will be charged to twice the Ctun voltage. The magnetizing inductance (Lm) of the main transformer is discharged and the transformer turns ratio regulation is applied through

109 the regulating transformer and diode D4. The circuit diagram for mode 3 operation is illustrated in Fig. 4.30(c). (a) Mode 1 operation (b) Mode 2 & 4 operation (c) Mode 3 operation Fig: 4.30 Modes of operation D. Mode 4 When the current through switch S2 falls to zero, it is turned OFF; ensuring zero current switching. During this interval, Ctun is charged

110 with the supply current Iin. The parasitic capacitance of S2 (Cds2) is charged from the energy stored in the magnetizing inductance (Lm) and in the parasitic capacitance of S1 (Cds1). Transfer of energy from the input side to the output does not occur in this mode as all the switches and diodes are in OFF state. The circuit diagram for mode 4 operation is presented in Fig. 4.30(b). 4.6.3 Regulation Method The regulation is based on addition or subtraction of voltage in the AC path of the converter. Here, a controlled transformer is used as a post regulator which adds or subtracts an additional voltage to the output filter of the converter. This technique is implemented with ZVS for a current fed push-pull converter for any operating conditions. Vc = RMS value of the controlled AC voltage obtained from an auxiliary PWM controlled converter Vs = RMS value of the AC voltage obtained from the non-regulated input Vo = Average value of the regulated output 1 : No = turns-ratio relationship, from input to output of the main transformer of the converter An additional winding with a turns ratio 1: NM, with regard to the primary is used in the main transformer so that regulation can be implemented. A small regulating current transformer having a turn s ratio 1: NR is also used to add or subtract the controlled voltage. The following equations govern the regulation:

111 VM = Vdc VC = NR VR + NM VM VO = NO VM VR The output VO is given by: ( ) Where, By varying the duty cycle of the auxiliary converter, the control voltage VC is changed, thereby regulating the output voltage. But the voltage regulation is limited by the input voltage and transformer turns ratio. If VS varies between zero and Vs, the output will vary between: ( ) ( ) ( ) ( ) ( ) ( ) From equations (4.9) and (4.10), it can be seen that by fixing and the regulation limit can also been fixed. 4.6.4 Design The design procedure for a 4.7W, 15V current fed push-pull converter is detailed in this section.

112 4.6.4.1 Specifications This section deals with the specifications and design aspects of the power converter. The push-pull converter is fed from a DC source and the converter is followed by a main transformer. Secondary of the main transformer are connected to the regulating transformer and are used to obtain the desired regulation. The specifications of the converter are as given below: Switching frequency (fs) = 50kHz Output power (P0) = 4.7W Input voltage (Vdc) = 12±15%V Output voltage-1 (V0) = 15V Output current-1 (I0) = 0.31A Switching frequency of Push-pull MOSFET, fs = 50kHz Switching frequency of Boost converter MOSFET = 120kHz 4.6.4.2 Converter Design Maximum supply voltage Minimum supply voltage Tuning capacitor voltage, Vct = 1.05 * = 14 V = 0.59 = 0.55 Maximum average input current,

113 Assuming η as 90%, = 1.31 A For 20% ripple in input current, that is, X = 0.1 (for 20% peak to peak ripple), maximum input current ripple magnitude is Therefore, Minimum inductance required is Current fed inductor is chosen as Li = 150 Peak primary current magnitude Output capacitance, ( ) If the voltage ripple is 3% and y is 0.015, then output capacitance Cout = 450µF. 4.6.4.3 Transformer and Inductor Design Design of transformer and inductors are carried out as per the design elaborated in section 3.3.1.4 and the results obtained are tabulated in Table 4.6. Table 4.6 Transformer and Inductor design details Parameters 1004 mm 4, Np = 12,, Core selected Transformer design From Appendix I : core - EE 20/10/5,, From Appendix II : SWG =32 ( ), SWG =37 ( ) Resonant Inductor Design From Appendix I : core - E 22/10/5,, From Appendix II : SWG =22 ( )

114 4.6.4.4 Tuning Capacitor Design Using equations (4.1) (4.4), M = 2.35, Im = 1.675 A and Zo >15 Choosing Zo = 20, Where (4.11) From equation (4.11), Ctun = 1µF and Lm = 400µH 4.6.4.5 Boost Converter Design The boost converter operates at twice the switching frequency of the main switches. The tuning capacitor value is much lower than the product value of transformer ratio so as to avoid interference with the resonant stage. Input voltage Vi = 4V to 5 V Output voltage Vob = 12V For a boost converter, (4.12) When Vi = 4V, Dbmax = 0.67 When Vi = 5V, Dbmin = 0.58 Considering the worst case, the design is continued with Dbmin. The input-output relation is: (4.13) From equation (4.13), Choose input current ripple as 5%, thus The minimum value of inductance is given by:

115 (4.14) Substituting the values in the above equation we get Boost inductor value LB is chosen as 300 Peak current magnitude The design of the inductor is similar to the design explained in the section 3.2.1.4 and the calculated values are tabulated in Table 4.7. The value of capacitance is given by (4.15) For 3% output voltage ripple and R=10, Capacitance C = 0.22µF. Table 4.7 Boost Inductor Design Parameters Core selected From Appendix I : core - EE 20/10/5,, From Appendix II : SWG =28 ( ) 4.6.5 Closed loop Simulation Results The converter designed in section 4.6.4 is simulated. Since the auxiliary part of the converter requires a pulsating current for the regulating transformer to work, the converter needs to be operated in closed loop condition. Duty ratio of the auxiliary switch is primarily dependent on the load voltage. Hence, by adjusting the duty cycle of the switch, the required output voltage is obtained. The output voltage is sensed and is compensated by a network for closed loop operation.

116 Pulses required to drive the auxiliary switch are produced by comparing the DC output of the compensator with a ramp signal. This change is then fed back to the primary of the converter allowing it to operate in a closed manner. Fig. 4.31(a) shows the output voltage and load current during open loop operation for variation in load of ±25%. The closed loop regulated output voltage and output current for different values of a resistive load ranging from ±25% are presented in Fig. 4.31(b). (a) (b) Fig: 4.31 (a) Open loop output voltage and output current (b) Closed loop Output Voltage and Load current From Fig. 4.32, it can be observed that the switch is operated under ZVZCS, that is, it is turned ON at zero voltage and turned OFF at

117 zero current. The maximum switch voltage and switch current are 28.6V and 2.54A respectively. Fig: 4.32 Resonant voltage and current waveforms (a) (b) Fig: 4.33 Voltage waveforms for load change within ± 25% (a) Switch-1 (b) Switch-2

118 The tuning capacitor s maximum and minimum voltages are 14V and 10V respectively. The major advantage of the converter is that the load variations do not affect resonance. For a load change of ± 25%, Fig. 4.33(a) and (b) shows the switch voltages; similarly Fig. 4.34 (a) & (b) shows the switch currents. Resonant part alone is zoomed to justify that resonance is unaffected by load changes. (a) (b) Fig: 4.34 Current waveforms for load change within ± 25% (a) Switch-1 (b) Switch-2 4.6.6 Experimental Results The closed loop implementation of ZVS current-fed push-pull converter which is powered by a 12V DC supply is described here.

119 Considering the voltage rating which is well below 100V and current ratings below 2A, MOSFET IRF840 is selected as the switch. Fig. 4.35 shows the hardware circuit. The hardware implementation details of the converter are given in Table 4.8. Fig: 4.35 Hardware circuit of the converter Table 4.8 Hardware implementation details MOSFETS IRF 840 Diodes MUR1560 Pulse generator IC SG 3525 Optocoupler IC TLP 250 Tuning capacitor 1.4µF, 100 V box type Auxiliary capacitor 220 nf, 100 V box type Output capacitor 220µF, electrolytic Main transformer core EE 20/10/5, With turns ratio 1 : 1.5 Current transformer RM14 core with 3C90, 2 turns in primary, 10 turns in secondary Current fed inductor 150 µh; core EE 20/10/5, With 45 turns of SWG 22 Auxiliary inductor 300µH; core EE 20/10/5, With 60 turns of SWG 28 4.6.6.1 Pulse Generation for Main Switches The pulses needed to turn ON the two switches during open loop and closed loop operation is generated using dspic30f4011. Closed loop

120 operation is dependent on the auxiliary switch present in the secondary of the converter where the regulation technique is employed. The required isolation and amplification of the pulses for the MOSFET is achieved by using an opto-coupler TLP 250(Detailed in Appendix-V). 4.6.6.2 Pulse Generation from Analog Controller IC SG3525 This section deals with pulse generation for SMPS circuits with analog controller IC SG3525. In SMPS circuits, this 16 pin pulse generation IC with lower external part count is used for deriving switch pulses. The first pin of the IC takes in the feedback input. The feedback voltage is obtained from the voltage divider circuit connected across the output load. The reference voltage generated in the IC at the 16 th pin (5V) is fed to the reference input pin 2 of the IC. Pin 14 and 2 are inputs of the error detector circuit. The PI controller output at the 9 th pin is compared with saw tooth waveform generated at the 7 th pin of the IC. PWM generator generates the pulses at 11 th and 14 th pin and these pulses are used to turn ON the switches. The SG3525 with PI controller is shown in Fig. 4.36. The desired frequency is related to the values of timing resistor (RT), timing capacitor (CT) and dead time resistor (RD) as derived in equation (4.16). ( ) (4.16)

121 Fig: 4.36 SG3525 as PI controller The saw tooth and the PI output generated from SG3525, as shown in Fig. 4.37(a) and (b), are fed to the error detector which produces the pulses after comparison. The pulse width of the switch can be changed by varying the control voltage with which the ramp is compared. (a) (b) Fig: 4.37 (a) Saw tooth generated from SG3525 (b)pi output from SG3525 Whenever the output voltage is varied, the DC compensated value also changes, thereby altering the pulse width of the switch. The saw

122 tooth waveform produced by CT and the PI controller output produced at pin 9 are compared as explained in Fig. 4.38(a). The pulse width generated for an increase or decrease in load variations are 24% and 45% as verified in Fig. 4.38(b) and (c) respectively. (a) (b) (c) Fig: 4.38 (a) Pulse for normal load (b) Pulse generated when load increases (c) Pulse generated when load decreases 4.6.6.3 Pulse Generation for Auxiliary Switches For the operation of the auxiliary switch in closed loop operation of the converter, PWM pulses are generated with a switching frequency of at least 100kHz, since the auxiliary side of the converter should be operated at about two times the switching frequency. The pulse circuitry using IC SG3525 and the pulse width generated for normal load is 47% as illustrated in Fig. 4.36 and 4.38(b) respectively. The output voltage is regulated whenever there is a change in line or load. RT, CT and RD are designed for generating a ramp of frequency 120kHz from equation (4.16) and designed values are CT = 0.01µF, RD = 100Ω, RT = 1kΩ.

123 4.6.6.4 Load transients Addition of compensator and PWM generator circuitry to produce closed loop pulses for the auxiliary switch completes the closed loop circuit of the converter. The pulses produced for the switch depends on the load voltage. For a load variation of ±20%, the waveforms of closed loop voltage and current are shown in Fig. 4.39(b) and (c) and the change in output voltage from the desired value is calculated to be ±700mV respectively. From these waveforms it is clear that the output voltage is regulated stringently for ±20% load variations, while the load change applied is clearly confirmed in the current waveforms. Output voltage and current for rated condition are illustrated in Fig. 4.39(a). (a) (b) (c) Fig: 4.39 (a) Output voltage and load current (b) Output voltage and load current for 20% decrease of load (c) Output voltage and load current for 20% increase of load 4.6.6.5 Line transients Line regulation is the response of the closed loop circuit for changes in supply voltage. The output voltage and current waveform for

124 decrease in supply of 15% is displayed in Fig. 4.40. The controller responds to the supply variations and regulates the output voltage stringently as observed in the waveform illustrated in Fig. 4.40. Similarly, waveform is observed for increase in supply also. Fig: 4.40 Output voltage and load current for 15% supply variation 4.6.6.6 Resonant Waveform The MOSFET switches are turned ON at zero voltage and turned OFF at zero current to achieve ZVZCS. The first switch, gate pulse and switch-1 voltage waveforms are shown in Fig. 4.41(a). The peak voltage across the switch is 30.4V which is about two times the source voltage. Fig. 4.41(b) shows the switch-2 voltage waveform. (a) (b) Fig: 4.41 (a) Switch-1 pulse and switch-1 voltage (b) Switch-2 pulse and switch-2 voltages

125 The switch-2 voltage produces a peak value of 34.4 V when the duty cycle of the switch is 29.2. Switch-1 and 2 current waveforms are shown in Fig. 4.42(a) and (b). The main advantage of the converter is that load and supply variations do not affect resonance. The resonant waveforms for a load change of ±20% and supply variations of ±15% are observed and the results validate the above statement. (a) (b) Fig: 4.42 (a) Switch-1 current with gate pulse (b) Switch-2 current with gate pulse 4.7 Analysis The efficiency and regulation is assessed for a load change of ±25%. The graph of efficiency versus output power and regulation versus load current is plotted in Fig. 4.43(a) and (b) respectively. It is observed that the efficiency (as per equation 4.8) is about 90.31% at rated load of 48Ω. Regulation in this case is less than 4%. Regulation is as good as 0.13% for normal input voltage of 12V and a rated load of 48Ω. For the rated load condition, regulation is less than 1% and the converter works well even for a load change of ±25%.