Summary Last Lecture

EE247 Lecture 23 Converters Techniques to reduce flash complexity Interpolating (continued) Folding Multi-Step s Two-Step flash Pipelined s EECS 247 Lecture 23: Data Converters 26 H.K. Page Summary Last Lecture Converters Comparator design (continued) Comparator architecture examples Techniques to reduce flash complexity Interpolating (to be continued) EECS 247 Lecture 23: Data Converters 26 H.K. Page 2

Interpolation Idea Reduce number of preamps & instead interpolate between preamp outputs Reduced number of preamps Reduced input capacitance Reduced area, power dissipation Same number of latches (2 B -) Important side-benefit Decreased sensitivity to preamp offset Improved DNL EECS 247 Lecture 23: Data Converters 26 H.K. Page 3 Preamp Output Vin A 2 Preamp Output.6.4.2 -.2 -.4 -.6.5.5 Vin /Δ 2 2.5 3 Vref Vref2 A 2 A Vref2 Vref Zero crossings (to be detected by latches) at = = Δ 2 = 2 Δ A EECS 247 Lecture 23: Data Converters 26 H.K. Page 4

Differential Preamp Output Preamp Output A A 2.5 -.5.5.5 2 2.5 3.5 A 2 -A 2 A -A A A 2 -.5.5.5 2 2.5 3 Vin / Δ Differential output crossings @ = = Δ 2 = 2 Δ Note: Additional crossing of A &-A 2 (A 2 &-A ) A A 2 cross zero at: 2 =.5*(2) Δ=.5Δ EECS 247 Lecture 23: Data Converters 26 H.K. Page 5 Interpolation in Flash Vin A 2 Half as many reference voltages and preamps Interpolation factor:x2 A Example: For bit straight Flash need 2 B =24 preamps compared 2 B- =52 for x2 interpolation Compare A2& -A Comparator output is sign of AA2 Possible to accomplish higher interpolation factor Interpolation at the output of preamps EECS 247 Lecture 23: Data Converters 26 H.K. Page 6

Vin Interpolation in Flash Preamp Output Interpolation A 2 A. Z Z Z Z. V o 2 V o.5 = (V o V o 2 )/2 V o Interpolate between two consecutive output via impedance Z Choices of Z:. Resistors (Kimura) 2. Capacitors (Kusumoto) 3. Current mode (Roovers) Ref: H. Kimura et al, A -b 3-MHz Interpolated-Parallel A/D Converter, JSSC, pp. 438-446, April 993 K. Kusumoto et al, "A -b 2-MHz 3-mW pipelined interpolating CMOS," JSSC, pp.2-26, December 993. R. Roovers et al, "A 75 Ms/s, 6 b, 6 mw, 3.3 V CMOS A/D converter," JSSC, pp. 938-944, July 996. EECS 247 Lecture 23: Data Converters 26 H.K. Page 7 Higher Order Resistive Interpolation Resistors produce additional levels With 4 resistors per side, the interpolation factor M=8 (M ratio of latches/preamps) Ref: H. Kimura et al, A -b 3-MHz Interpolated-Parallel A/D Converter, JSSC April 993, pp. 438-446 EECS 247 Lecture 23: Data Converters 26 H.K. Page 8

DNL Improvement Preamp offset distributed over M resistively interpolated voltages: Impact on DNL divided by M Latch offset divided by gain of preamp Use large preamp gain Next: Investigate how large preamp gain can be Ref: H. Kimura et al, A -b 3-MHz Interpolated-Parallel A/D Converter, JSSC April 993, pp. 438-446 EECS 247 Lecture 23: Data Converters 26 H.K. Page 9 Preamp Input Range Preamp Output A A 2.5 -.5 Linear region of transfer curve not overlapping.5.5 2 2.5 3 A 2 -A 2 A -A.5 A A 2 -.5.5.5 2 2.5 3 Vin / Δ If linear region of preamp transfer curve do not overlap Dead-zone in the interpolated transfer curve! Results in error Linear consecutive preamp input ranges must overlap i.e. range > Δ Sets upper bound on preamp gain <V DD / Δ EECS 247 Lecture 23: Data Converters 26 H.K. Page

Interpolated-Parallel -bit overall resolution: 7-bit flash (27 preamps and 28 resistors) & x8 interpolation Ref: H. Kimura et al, A -b 3-MHz Interpolated-Parallel A/D Converter, JSSC April 993, pp. 438-446 EECS 247 Lecture 23: Data Converters 26 H.K. Page Measured Performance (73) Low input capacitance Ref: H. Kimura et al, A -b 3-MHz Interpolated-Parallel A/D Converter, JSSC April 993, pp. 438-446 EECS 247 Lecture 23: Data Converters 26 H.K. Page 2

Interpolation Summary Consecutive preamp transfer curve need to have overlap Limits gain of preamp to ~V DD /Δ The added impedance at the output of the preamp typically reduces the bandwidth and affects the maximum achievable frequencies DNL due to preamp offset reduces by interpolation factor M Interpolation reduces # of preamps and thus reduces input C- however, the # of required latches the same as straight Flash Use folding to reduce the # of latches EECS 247 Lecture 23: Data Converters 26 H.K. Page 3 Folding Converter V IN MSB LSB L O G I C Digital Output Folding Circuit Two s operating in parallel MSB Folder LSB Significantly fewer comparators than flash Fast Typically, nonidealities in folder limit resolution to ~Bits EECS 247 Lecture 23: Data Converters 26 H.K. Page 4

Example: Folding Factor of 4 Folding factor number of folds MSB bits V out Folder maps input to smaller range MSB determines which fold input is in LSB determines position within fold Logic circuit combines LSB and MSB results To LSB Quantizer V FS /2 V FS EECS 247 Lecture 23: Data Converters 26 H.K. Page 5 Example: Folding Factor of 4 V out How are folds generated? Fold V out = Fold 2 V out = - V FS /2 Fold 3 V out = -V FS /2 Fold 4 V out = - V FS Note: Sign change every other fold reference shift 3 2 4 V FS /2 V FS EECS 247 Lecture 23: Data Converters 26 H.K. Page 6

R V DD -Vo Generating Folds via Source-Couple Pairs R2 M M2 Vref M3 M4 Vref2 M5 M6 Vref3 M7 M8 Vref4 IS IS IS IS Vref < Vref2 < Vref3 < Vref4 As Vin changes, only one of M, M3, M5, M7 is on depending on the input level EECS 247 Lecture 23: Data Converters 26 H.K. Page 7 CMOS Folder Output Folder Output Error (Ideal-Real).5 Ideal Folder CMOS Folder -.5.5.5 2 2.5 3 3.5 4..5 -.5 -..5.5 2 2.5 3 3.5 4 /Δ CMOS folder transfer curve max. min. portions: Rounded Accurate at zero-crossings In fact, most folding s do not use the folds, but only the zero-crossings! EECS 247 Lecture 23: Data Converters 26 H.K. Page 8

Parallel Folders Using Only Zero-Crossings Folder 4 Comparator 3/4 * Δ Folder 3 Comparator 2/4 * Δ Folder 2 Comparator Logic LSB bits (to be combined with MSB bits) /4 * Δ Folder Comparator /4 * Δ EECS 247 Lecture 23: Data Converters 26 H.K. Page 9 Parallel Folder Outputs Folder Output.4.2 -.2 -.4 F F2 F3 F4 2 3 4 5 Vin /Δ 4 folders with 4 folds each 6 zero crossings 4 LSB bits Higher resolution More folders Large complexity Interpolation EECS 247 Lecture 23: Data Converters 26 H.K. Page 2

Folding & Interpolation Folder 4 3/4 * Δ Folder 3 2/4 * Δ Folder 2 /4 * Δ Fine Flash E N C O D E R Folder /4 * Δ EECS 247 Lecture 23: Data Converters 26 H.K. Page 2 Folder / Interpolator Output Example:4 Folders 4 Resistive Interpolator per Stage Folder / Interpolator Output.5.4.3.2. -. -.2 -.3 -.4 F F2 I I2 I3 -.5 2 3 4 5 Vin / Δ.4.2 -.2.5.6.7.8 Note: Output of two folders corresponding interpolator only shown EECS 247 Lecture 23: Data Converters 26 H.K. Page 22

Folder / Interpolator Output Example:2 Folders 8 Resistive Interpolator per Stage Folder / Interpolator Output.5.4.3.2. -. F F2 I I2 I3 -.2 -.3 -.4 -.5 2 3 4 5 Vin / Δ.6.4.2 -.2 -.4 -.6.5.6.7.8.9 2 2. Non-linear distortion Interpolate only between closely spaced folds to avoid nonlinear distortion EECS 247 Lecture 23: Data Converters 26 H.K. Page 23 A 7-MS/s -mw 8-b CMOS Folding and Interpolating A/D Converter Ref: B. Nauta and G. Venes, JSSC Dec 985, pp. 32-8 EECS 247 Lecture 23: Data Converters 26 H.K. Page 24

A 7-MS/s -mw 8-b CMOS Folding and Interpolating A/D Converter Note: Total of 4 comparators compared to 2 8 -= 255 for straight flash EECS 247 Lecture 23: Data Converters 26 H.K. Page 25 A 7-MS/s -mw 8-b CMOS Folding and Interpolating A/D Converter Ref: B. Nauta and G. Venes, JSSC Dec 985, pp. 32-8 EECS 247 Lecture 23: Data Converters 26 H.K. Page 26

Time Interleaved Converters Example: 4 s operating in parallel at sampling frequency f s Each converts on one of the 4 possible clock phases Overall sampling frequency= 4f s Note T/H has to operate at 4f s! Extremely fast: Typically, limited by speed of T/H Accuracy limited by mismatch in individual s (timing, offset, gain, ) V IN 4f s T/H f s f s T/4 f s 2T/4 f s 3T/4 Output Combiner Digital Output EECS 247 Lecture 23: Data Converters 26 H.K. Page 27 Two-Step (22) Example 2-bit 2-bit??? D out = ε q "Missing voltage" or "residue" ( -ε q ) Idea: Use second to quantize and add -ε q ε q [LSB] D out 2 3.5-2 3 Input [LSB] Using only one : output contains large quantization error -.5 EECS 247 Lecture 23: Data Converters 26 H.K. Page 28

Two Stage Example 2-bit Coarse 2-bit DAC - 2-bit -ε q Fine -ε q ε q2 D out = ε q -ε q ε q2 Use DAC to compute missing voltage Add quantized representation of missing voltage Why does this help? How about ε q2? EECS 247 Lecture 23: Data Converters 26 H.K. Page 29 Two Step (22) Flash 4-bit Straight Flash Ideal 2-step Flash EECS 247 Lecture 23: Data Converters 26 H.K. Page 3

Two Stage Example ε q /2 2 2 Second Fine First Coarse Fine is re-used 2 2 times Fine 's full scale range needs to span only LSB of coarse quantizer Vref 2 Vref ε q2 = = 2 2 2 2 2 2 EECS 247 Lecture 23: Data Converters 26 H.K. Page 3 Two-Stage (22) Transfer Function D out Coarse Bits (MSB) Fine Bits (LSB) EECS 247 Lecture 23: Data Converters 26 H.K. Page 32

Residue or Multi-Step Type Issues Vin coarse (B-Bit) DAC (B2-Bit) Residue Fine (optional) (K-Bit) Bit Combiner (BB2)-Bit Operation: Coarse determines MSBs DAC converts the coarse output to analog- Residue is found by subtracting ( -V DAC ) Fine converts the residue and determines the LSBs Bits are combined in digital domain Issue:. Fine has to have precision in the order of overall /2LSB 2. Speed penalty Need at least clock cycle per extra series stage to resolve one sample EECS 247 Lecture 23: Data Converters 26 H.K. Page 33 Solution to Issue () 2-bit Coarse 2-bit DAC - G=2 -ε B q 2-bit Fine -ε q ε q2 D out = ε q -ε q ε q2 Accuracy needed for fine relaxed by introducing inter-stage gain Example: By adding gain of x(g=2 B =4) prior to fine in (22)bit case, precision required for fine is reduced to 2-bit only! Additional advantage- coarse and fine can be identical stages EECS 247 Lecture 23: Data Converters 26 H.K. Page 34

Solution to Issue (2) 2-bit Coarse 2-bit DAC - T/H(G=2 B ) -ε q Fine T/H 2-bit D out = ε q -ε q ε q2 Conversion time significantly decreased by employing T/H between stages All stages busy at all times operation concurrent During one clock cycle coarse & fine s operate concurrently: First stage samples/converts/generates residue of input signal sample # n While 2 nd samples/converts residue associated with sample # n- EECS 247 Lecture 23: Data Converters 26 H.K. Page 35 Pipelined A/D Converters Ideal operation Errors and correction Redundancy Digital calibration Implementation Practical circuits Stage scaling EECS 247 Lecture 23: Data Converters 26 H.K. Page 36

Pipeline Block Diagram Stage B Bits Stage 2 B 2 Bits V res2 Stage k B k Bits MSB......LSB Align and Combine Data Digital output (B B 2... B k ) Bits Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. bit can be built with series of s each -bit only!) Each stage performs coarse A/D conversion and computes its quantization error, or "residue All stages operate concurrently EECS 247 Lecture 23: Data Converters 26 H.K. Page 37 Pipeline Characteristics Number of components (stages) grows linearly with resolution Pipelining Trading latency for conversion speed Latency may be an issue in e.g. control systems Throughput limited by speed of one stage Fast Versatile: 8...6bits,...2MS/s Many analog circuit non-idealities can be corrected digitally EECS 247 Lecture 23: Data Converters 26 H.K. Page 38

Pipeline Concurrent Stage Operation φ φ 2 acquire convert Stage B Bits convert acquire Stage 2 B 2 Bits...... Stage k B k Bits CLK φ φ 2 Align and Combine Data Digital output (B B 2... B k )Bits Stages operate on the input signal like a shift register New output data every clock cycle, but each stage introduces at least ½ clock cycle latency EECS 247 Lecture 23: Data Converters 26 H.K. Page 39 Pipeline Latency Note: One conversion per clock cycle & 7 clock cycle latency [Analog Devices, AD 9226 Data Sheet] EECS 247 Lecture 23: Data Converters 26 H.K. Page 4

φ φ 2 Pipeline Data Alignment acquire convert convert acquire...... Stage B Bits Stage 2 B 2 Bits Stage k B k Bits CLK φ φ 2 D out CLK CLK CLK Digital shift register aligns sub-conversion results in time EECS 247 Lecture 23: Data Converters 26 H.K. Page 4 Cascading More Stages Vref /2 B /2 (BB2) /2 (BB2B3) B bits B 2 bits B 3 bits DAC - LSB of last stage becomes very small Impractical to generate several All stages need to have full precision EECS 247 Lecture 23: Data Converters 26 H.K. Page 42

Pipeline Inter-Stage Gain Elements B bits 2 B B 2 bits 2 B2 2 B3 B 3 bits DAC - Practical pipelines by adding inter-stage gain use single Precision requirements decrease down the pipe Advantageous for noise, matching (later) EECS 247 Lecture 23: Data Converters 26 H.K. Page 43 Complete Pipeline Stage - ε q -G Vres B-bit D B-bit DAC Residue Plot E.g.: B=2 G=2 2 =4 V res EECS 247 Lecture 23: Data Converters 26 H.K. Page 44

Pipeline Errors We cannot build perfect s, DACs and gain elements How can we tolerate/correct errors? Let's first look at sub- errors Assumptions: Ideal DAC, ideal gain elements, only nonideality due to sub- comparator offset EECS 247 Lecture 23: Data Converters 26 H.K. Page 45 Pipeline Model, ε q V res2 V res(n-) - G - G - 2 G n- ε q2 ε q(n-) D D 2 D (n-) D n ε qn D out /G d /G d2 /G d(n-) G ε G D V q2 2 out = in, εq G d G d G d2 ε G... G G ε q(n ) (n ) qn n 2 n dj d(n ) j= j= G dj EECS 247 Lecture 23: Data Converters 26 H.K. Page 46

Pipeline Model If the "Analog" and "Digital" gain/loss is precisely matched: εqn Dout = Vin, n G j j= n = B D. R. 2log 2 n G j j= n B Bn = log 2 G j j= EECS 247 Lecture 23: Data Converters 26 H.K. Page 47 Pipeline Observations The aggregate resolution is independent of sub- resolution Effective stage resolution B j =log 2 (G j ) Overall conversion error does not (directly) depend on sub- errors! Only error term in D out contains quantization error associated with the last stage So why do we care about sub- errors? Go back to two stage example EECS 247 Lecture 23: Data Converters 26 H.K. Page 48

Pipeline Sub- Errors, B bits qn out = Vin, n G j j= D D out = V in, ε ε G q2 Vref ε q2 Grows outside ½ LSB bounds EECS 247 Lecture 23: Data Converters 26 H.K. Page 49 Ideal 2-Stage Pipelined Pipeline Sub- Errors 2-Stage Pipelined with Coarse Comp. Offset EECS 247 Lecture 23: Data Converters 26 H.K. Page 5

Pipeline st -Stage Comparator Offset Problem: exceeds 2 nd pipeline stage overload range V res2 Overall Transfer Curve First stage Levels: (Levels normalized to LSB) Ideal comparator threshold: -,, Comparator threshold including offset: -,.3, Missing Code! EECS 247 Lecture 23: Data Converters 26 H.K. Page 5 Pipeline Three Ways to Deal with Errors All involve "sub- redundancy Redundancy in stage that produces errors Choose gain for 2 nd stage < 2 B Higher resolution sub- Redundancy in succeeding stage(s) EECS 247 Lecture 23: Data Converters 26 H.K. Page 52

() Inter-Stage Gain Following st stage < 2 B, B bits Choose G slightly less than 2 B Effective stage resolution becomes noninteger B eff =log 2 G ε q2 Ref: A. Karanicolas et. al., JSSC 2/993 EECS 247 Lecture 23: Data Converters 26 H.K. Page 53 Correction Through Redundancy enlarged residuum still within input range of next stage V res2 Overall Transfer Curve If G=2 instead of 4 Only Bit resolution from first stage (3-Bit total) No overall error! EECS 247 Lecture 23: Data Converters 26 H.K. Page 54

(2) Higher Resolution Sub-, B bits Keep G =2 B (e.g. keep G =4) Add extra decision levels in sub- (e.g. add extra bit to st stage) E.g. B =B eff ε q2 Ref: Singer et. al., VSLI996 EECS 247 Lecture 23: Data Converters 26 H.K. Page 55 (3) Over-Range Accommodation Through Increase in Following Stage Resolution, B bits No redundancy in stage with errors Add extra decision levels in succeeding stage ε q2 Ref: Opris et. al., JSSC 2/998 EECS 247 Lecture 23: Data Converters 26 H.K. Page 56

Redundancy The preceding analysis applies to any stage in an an n-stage pipeline Can always perceive a multi-stage pipelined as a single stage backend B bits B 2 bits B 3 bits B 4 bits B bits B 2 B 3 B 4 bits EECS 247 Lecture 23: Data Converters 26 H.K. Page 57 Redundancy In literature, sub- redundancy schemes are often called "digital correction" a misnomer! No error correction takes place We can tolerate sub- errors as long as: The residues stay "within the box", or Another stage downstream "returns the residue to within the box" before it reaches last quantizer Let's calculate tolerable errors for popular ".5 bits/stage" topology EECS 247 Lecture 23: Data Converters 26 H.K. Page 58

.5 Bits/Stage Example Comparators placed strategically to minimize overhead G=2 B eff =log 2 G=log 2 2= /8 B=log 2 (2)=.589... Ref: Lewis et. al., JSSC 3/992 EECS 247 Lecture 23: Data Converters 26 H.K. Page 59 3-Stage.5-bps Pipelined V res3 V res2 Overall Transfer Curve All three stages Comparator with offset Overall transfer curve No missing codes Some DNL error Ref: S. Lewis et al, A -b 2-MS/s Analog-to-Digital Converter, J. Solid-State Circ., pp. 35-8, March 992 EECS 247 Lecture 23: Data Converters 26 H.K. Page 6

Inter-Stage Amplifier Offset V os DAC - V os G V res -V os D Input referred converter offset usually no problem Equivalent sub- offset - accommodated through adequate redundancy EECS 247 Lecture 23: Data Converters 26 H.K. Page 6 Gain Stage Errors, ε q V res V res2 V res(n-) - G δ - G - 2 G n- ε q2 ε q(n-) D D 2 D (n-) D n ε qn D out /(G d δ ) /G d2 /G d(n-) D G = V ε G out in, q d δ δ ε G ε G ε G G G q2 2 q( n ) ( n ) qn... n 2 n d d2 d( n ) G dj Gdj j= j= Small amount of gain error can be tolerated EECS 247 Lecture 23: Data Converters 26 H.K. Page 62

Interstage Gain Error First Stage Residue (Gain Error) Converter Transfer Function (Gain Error) Vres Dout.5.5 Vin.5.5 Vin Dout(ideal) - Dout Transfer Function Error(Gain Error).2.2.5.5 Vin EECS 247 Lecture 23: Data Converters 26 H.K. Page 63 Gain Errors Gain error can be compensated in digital domain "Digital Calibration" Problem: Need to measure/calibrate digital correction coefficient Example: Calibrate -bit first stage Objective: Measure G in digital domain EECS 247 Lecture 23: Data Converters 26 H.K. Page 64

Model G V in 2 V res = G ( V V ) in DAC GV in V V DAC DAC ( D = ) = ( D = ) = V ref / 2 EECS 247 Lecture 23: Data Converters 26 H.K. Page 65 Calibration Step = const. - G () Backend D back () -bit D M U X -bit DAC V () res D () back = G = G ( Vin Vref / 2) ( V V / 2) in V ref ref store EECS 247 Lecture 23: Data Converters 26 H.K. Page 66

Calibration Step 2 = const. - G (2) Backend D back (2) -bit D M U X -bit DAC V (2) res D (2) back = G = G ( Vin ) ( V ) in V ref store EECS 247 Lecture 23: Data Converters 26 H.K. Page 67 Calibration Evaluate D D D () back (2) back () back = G = G D (2) back ( V V / 2) in ( V ) in V V ref ref ref = G 2 EECS 247 Lecture 23: Data Converters 26 H.K. Page 68

Accuracy Bootstrapping, ε q V res2 V res(n-) - G - G - 2 G n- ε q2 ε q(n-) D D 2 D (n-) D n ε qn D out /G d /G d2 /G d(n-) D G ε G G = q2 2 q( n ) ( n ) qn out Vin, ε q... n 2 n Gd Gd Gd 2 Gd ( n ) G dj Gdj j= j= Highest sensitivity to gain errors in front-end stages ε ε EECS 247 Lecture 23: Data Converters 26 H.K. Page 69 "Accuracy Bootstrapping" Direction of Calibration Sufficiently Accurate Stage Stage 2 Stage 3 Stage k B n bits Calibration in opposite direction... Ref: A. N. Karanicolas et al. "A 5-b -Msample/s digitally self-calibrated pipeline," IEEE J. Of Solid-State Circuits, pp. 27-5, Dec. 993 E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined s," TCAS II, pp. 43-53, March 995 L. Singer et al., "A 2 b 65 MSample/s CMOS with 82 db SFDR at 2 MHz," ISSCC 2, Digest of Tech. Papers., pp. 38-9 EECS 247 Lecture 23: Data Converters 26 H.K. Page 7

DAC Errors - G Backend B -bit B -bit DAC D D out /G - ε DAC D back Can be corrected digitally as well Same calibration concept as gain errors EECS 247 Lecture 23: Data Converters 26 H.K. Page 7 DAC Calibration Step = const. - G Backend B -bit D M U X B -bit DAC ε DAC () D out /G D back ε DAC () equivalent to offset - ignore EECS 247 Lecture 23: Data Converters 26 H.K. Page 72

DAC Calibration Step 2...2 B = const. - G Backend B -bit D M U X B -bit DAC ε DAC (...2 B -) D out /G...2 B - Cal. Register - D back Stepping through DAC codes...2 B - yields all incremental correction values EECS 247 Lecture 23: Data Converters 26 H.K. Page 73 Calibration Hardware Digital is "free" and easier to build than precise analog circuits... Ref: E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined s," TCAS II, pp. 43-53, March 995 EECS 247 Lecture 23: Data Converters 26 H.K. Page 74