ISSN 2322-0929 Vol.03, Issue.03, June-2015, Pages:0288-0292 www.ijvdcs.org NAVEEN T.N 1, S.L. MUKTHI 2 1 Research Scholar, Dept of ECE (VLSI Design & ES), Bangalore Institute of Technology, Bengaluru, India, E-mail: naveentn27@gmail.com. 2 Assistant Professor, Dept of ECE, Bangalore Institute of Technology, Bengaluru, India, E-mail: chakshu.son@gmail.com. Abstract: The main aim of this paper is to design an effective discrete Digital PID controller with fast adder algorithms. The Proportional Integral Derivative controller aplenty used in automation Industries (approximately 90% [1]). 20th Century Semiconductor revolution drastically changed the PID controller design from mechanical to electronics sector; because of which the PID Controllers have escalated usage in aerospace, automobiles, robotics, electrical power systems etc. Fast growing world implores VLSI designers to design controllers which can provide low power, fast computation and low cost PIDs. This paper s trivial idea of using fast adders instead of normal CLA (Carry Lookahead Adder) on FPGA helps designers to please the next generation. In this paper, firstly discrete PID controller algorithm is implemented followed by design of parallel prefix adders which have very less computation time like Kogge Stone Adder, Brent Kung Adder and Han Carlson. Han Carlson adders stood out to be the best among these three adders with very less computation time, low power consumption. Their synthesis parameters like Timing, Area and Power are compared. This design is implemented on FPGA and is verified for high speed DC motor using Spartan3 FPGA kit which provides an optimal balance of low cost, low risk and low power for this application. PID Controller s computation time is reduced by 9.87% for each iteration by using parallel prefix Han Carlson Adder. The power consumption can be reduced by 4.35% with a tradeoff of 6% increase in area Keywords: Digital PID Controller; Brent Kung Adder; Kogge-Stone Adder; Han Carlson Adder; FPGA. I. INTRODUCTION Fast growing world demands automation in almost all the fields. To create any automated system, controller is must and should. The major controller used in almost all the fields like the industries, aerospace, automotives, power systems, electrical system, robotics, and drives control etc. are PID Controllers. In industries approximately 89% of control loop still depends on various forms of pervasive PID controller which are commercially available from last 70 years. Proportional integral derivative (PID) controller which are most commonly used in the industry are mechanical or pneumatic PID controllers which demands for human interaction for manual tuning by rotating various mechanical wheels. 20th Century Semiconductor revolution has changed the entire world and influenced all to use semiconductors in all the fields. PID Controllers which were just mechanical and pneumatic were replaced by electronic elements like Register, Capacitor and Inductor. Invention of Microprocessor and Micro Controller also forced the scientists to implement PID Controller using them. Usage of these Controllers predominantly increased due to their low cost, low power consumption and low risk factors. The best method to achieve all these demands is to use FPGA to implement PID Controllers. FPGA is a semiconductor device containing programmable logic blocks (PLBs) and a hierarchy of reconfigurable interconnects to realize any complex combinational or sequential logic functions. By programming the logical blocks and interconnections, any logic can be implemented. Today s FPGAs consist of configurable embedded static randomaccess memories (SRAMs), high-speed input/output (I/O) elements, hard-embedded processors, highspeed transceivers, and network interfaces. FPGAs are widely used in different applications, such as motor controllers, automobile controllers, fuzzy-logic controllers, finite-impulse-response (FIR) filter realization, etc. FPGA is a best option to do any ASIC design. In the recent years, the specifications of control systems are demanding to include a certain degree of intelligence. These systems must also be capable of selecting intelligent sensors, remote monitoring and implementing sophisticated control algorithms that has self adaptation mechanism. Hence in order to meet this specification; we are using a new approach in terms of hardware software codesign. We are presenting this design using reconfigurable hardware like FPGA which allows hardware/software codesign to take place. II. DESIGN OF DISCRETE PID CONTROLLER PID Controller is as 3 term controller because it uses the proportional, the integral and derivative values to generate control signal. The proportional term handles the present error, the integral term handles the past error by accumulating the past error and finally the derivative term handles the future error by predicting future error, sum of all these terms will help to handle the error effectively and provide fast response. P-I-D controller output of a continuous type is given by Copyright @ 2015 IJVDCS. All rights reserved.
NAVEEN T.N, S.L. MUKTHI (1) The above equation can be discretised at small sampling interval T0 as shown in figure below Figure2. Discrete Digital PID Controller. Figure1. Error v/s discrete time graph. First order derivative can be written as Using rectangular integration it is approximated as: Now replace the integral and derivative terms in eqn. (1), (2) From equation (2), the error signal at the (k-1) th instant can be written as: Subtracting eqn. (3) from (2) we can have Where, (3) (4) Each sampling period s previous output is fed as a feedback to the system and is stored in register as input. At every next clock cycle it will be complemented and subtracted with set point input to calculate error. Obtained e(k) is multiplied with calculated q0, similarly e(k-1) is multiplied with q1and e(k-2) with q2. Product of all the three multipliers and last previous output will be summed together to get the PID controller output u(k). This iteration will be carried out until the error e(k) terms to zero. III. DESIGN OF FAST ADDERS In the world of computations, adders play a very crucial role. All major functionality will have adder module as one of the prime sub module. Adders are used in ALU of processor, to calculate address, multiplication, decrement and increment operation etc. Right from 18 th Century many inventers have proposed many types of adders with different logics. Examples include Half Adder, Full Adder, Carry Select Adder, Ripple Carry Adder, Carry Lookahead Adder, Conditional Skip Adder, Carry Skip Adder, Carry Complete Adder and so on. Initial multi-bit adders Ripple Carry Adder was called Ripple Carry because their carry used to ripple from LSB to MSB. If carry gets generated in the LSB then that carry bit used to travel to the next bit position for addition so the time taken for computation mainly depends on how many bits needs to be added (8bit, 16bit or 32bit). RCA was taking O(n) time to send carry to MSB. Rapidly growing industrialization, population and people interest on electronics forced the engineers to reduce the computation time. Even engineers came up with a new faster way of adding binary number by using P&G (Propagation and Generation) signals. The above algorithm is known as Velocity algorithm. The major advantage of this algorithm is that it is of recursive type. It calculates the incremental output at each sample instant. As a result, it requires only to store three previous values: e(k), e(k-1) and e(k-2). A. Kogge Stone Adder In [5] a parallel prefix adder architecture which was a form of CLA is proposed. A 4 bit Kogge stone adder is shown in Figure 3. Each vertical stage is generating propagate and generate bit (square box). P&G signals of current bit and the P&G signals of previous bits are used to generate P & G for next stage (big circle). Finally the carry bits are produced in the last stage (small circle) and these bits are XOR d with
initial propagate signal to produce sum. All equations are mentioned in Figure 3. It used to take Olog(n) time to generate a carry. Hence it was considered as the fastest adder. Almost all the industries started to use this fast adder to get better performance in small interval of time. Advantages of Kogge Stone adder are lower fan outs at each stage and less computation time. Disadvantages of Kogge-Stone adder are more area for implementation and wiring congestion problems. Advantages of Brent Kung adder are less area for implementation O(n*log(n)), less wiring congestion, less Computation time O(log(n)), and cost of Production was less because of symmetry and regular fashion. Disadvantages include high logic depth and more fan outs at each stage. C. Han Carlson Adder Figure5. Han Carlson Adder Tree structure. Figure3. 4-bit Kogge - Stone adder example. B. Brent Kung Adder In [6], a parallel prefix adder architecture which is similar to Kogge Stone, consumed less area and had less wiring congestions is proposed. It also has O(log(n)) gate level depth and is faster than RCA. This adder is reverse to RCA here carry were calculated in parallel which reduced the computation time. It uses a tree structure and P&G logic as shown in Figure 4. In [6] Brent and Kung adder which was having a regular layout for prefix computation is used. It is suitable for VLSI implementation using pipelining. The area O(n) and O log(n) time considerations were minimum. Kogge Stone adder [5] was very effective in solving linear recurrences. So Han and Carlson [7] derived logic to integrate both adders algorithms to implement fastest area efficient and lower fan out adder architecture. Han Carlson adder has area A = O (n*log(n)) and lowest delay time. This was considered as the fastest possible area efficient adder. Advantages include low latency, area-efficiency and lower fan outs. Disadvantages include complexity in understanding, due to its Hybrid structure. IV. SOFTWARE SIMULATION MATLAB provides enormous options to compare various data. To compare Verilog simulation results we have used MATLAB. Simulation results of Verilog code written to a text file and the same data is used for plotting in MATLAB. The PID Controller, shown in Figure 6, is designed in both MATLAB and Verilog using the fast adders. The results of the both the modules compared is shown in Figure 8. Figure4. Brent - Kung Adder tree structure. Figure6. Simple PID Controller.
NAVEEN T.N, S.L. MUKTHI Figure7. PID Controller with Fast Adder. Figure10. Time response of FPGA. Figure8. Three Methods Comparison. Verilog response varies slightly as whole numbers were used for inputs. All the three simulation responses resemble the same. Software method of verifying the results helped in comparing the results by plotting them. VI. RESULTS Synthesis results of parallel prefix fast adders are compared with Normal adder (CLA) and the results are compared in Figure 11. It clearly indicates that Kogge-Stone adder takes very less computation time at the cost of area. Brent- Kung adder gives better power, area with increased time compared to Han Carlson Adder. Han Carlson Adder is best among these three adders with better timing, area and power consumption. Even though Brent Kung looks better than Han Carlson, as the number of bits increases the time taken for computation also increases. Due to this Han Carlson stands out to be the best among these three adders. V. HARDWARE IMPLEMENTATION PID Controller algorithm designed using Han Carlson adder for DC motor application is implemented on SPARTAN 3 FPGA kit as shown in the below Figure 9. The parameters like Desired speed (set point) speed, measured speed and controller output in terms of voltage are plotted. Figure11. Time response of FPGA. Figure9. Hardware module block diagram. Fast adders designed earlier are used in PID Controller algorithm and there synthesis parameters are compared with normal adder PID Controller. Han Carlson adder reduces the computation time by 9.87% and also reduces power consumption by 4.35% with tradeoff of increasing area by 6%.
Fig12. VII. CONCLUSION Currently industries are updating themselves with new types of controllers which are chiefly made up of electronic devices (Microcontrollers and FPGA). PID Controllers implemented on FPGA provides superior control compared to any other approaches. The computation time to provide a single output or response to input will be reduced by 9.87% by using parallel prefix Han Carlson Adder. By using Han Carlson adders in PID Controller power consumption can be reduced by 4.35% for each iteration with a tradeoff of 6% increase in area. VIII. REFRENCES [1] Michal Kocur, Stefan Kozak, Branislav Dvorscak Design and Implementation of FPGA - Digital Based PID Controller 978-1-4799-3528-4/14/ 2014 IEEE. [2] M. Baha Bayram, H. Ibrahim Bulbul, Celal Can and Ramazan Bayindir from Gazi University 06500 Ankara, Turkey Matlab/GUI Based Basic Design Principles of PID Controller in AVR 4th International Conference on Power Engineering, Energy and Electrical Drives Istanbul, Turkey, 13-17 May 2013. [3] Michal Kocur, Stefan Kozak, Branislav Dvorscak, Design and Implementation of FPGA - Digital Based PID Controller 2014 15th International Carpathian Control Conference (ICCC). [4] Swapna Gedam, Pravin Zode, Pradnya Zode of Deptt. of Electronics EngineeringY.C. College of Engg, Nagpur India- 441110 FPGA Implementation of Hybrid Han-Carlson Adder 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS). [5] Peter M. Kogge and Harold S. Stone A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations IEEE Transactions on computers, vol C-22, NO. 8, auguest 1973. [6] R. Brent and H. T. Kung, "A Regular Layout for Parallel Adders," IEEE Transaction on Computers, vol. C-31, Issue: 3, pp. 260-264, 1982. [7] Tackdon Han and David A. Carlson Department of Electrical and Computer EngineeringUniversity of Massachusetts, Amherst, MA 01003 ' Fast Area-Efficient VLSI Adders CH2419-0/87/000010049 1987 IEEE. [8] V.Subasri, K.Lavanya and B.Umamaheswari, Implementation of Digital PID controller in Field Programmable Gate Array (FPGA) India International Conference on Power Electronics 2006. [9] Somsubhra Ghosh1, Ranjit Kumar Barai2, Samar Bhattarcharya, Prarthana Bhattacharyya3,Shubhobrata Rudra4, Arka Dutta5, Rownick Pyne6 Dept. of Electrical Engineering Jadavpur University Kolkata, India An FPGA Based Implementation of a Flexible Digital PID Controller For a Motion Control System 2013 International Conference on Computer Communication and Informatics (ICCCI - 2013), Jan. 04 06, 2013, Coimbatore, INDIA [10] Dr. M. Meenakshi, Microprocessor Based Digital PID Controller for Speed Control of D.C. Motor 978-0-7695-3267-7/08 2008 IEEE DOI 10.1109/ICETET.2008.256. [11]Yajuan Chena, Qinghai Wub Faculty of Electronic and Electrical Engineering, Huaiyin Institute of Technology, Huai'an Jiangsu, China Design and Implementation of PID Controller Based on FPGA and Genetic Algorithm 2011 International Coriference on Electronics and Optoelectronics. [12] R.P.P. Singh, Parveen Kumar, Balwinder Singh Performance Analysis Of Fast Adders Using VHDL 2009 International Conference on Advances in Recent Technologies in Communication and Computing. [13] Adilakshmi Siliveru, M.Bharathi Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India. Design of Kogge-Stone and Brent-Kung adders using Degenerate Pass Transistor Logic nternational Journal of Emerging Science and Engineering (IJESE) ISSN: 2319 6378, Volume-1, Issue-4, February 2013.