Delay Comparison of 4 by 4 Vedic Multiplier based on Different Adder Architectures using VHDL

28 Delay Comparison of 4 by 4 Vedic Multiplier based on Different Adder Architectures using VHDL Gaurav Sharma, MTech Student, Jagannath University, Jaipur, India Arjun Singh Chauhan, Lecturer, Department of Electronics and Communication, Jaipur Institute of Engineering and Technology, Jaipur, India Himanshu Joshi, Assistant Professor, Department of Electronics and Communication, Jagannath University, Jaipur, India Satish Kumar Alaria, Lecturer, Department of Computer Science & Engg., Jaipur Engineering College, Jaipur, India ABSTRACT This paper presents a delay comparison of two different multipliers for unsigned data, one uses a ripple carry and the second one uses a carry-lookahead adder. The 4 4 Vedic multiplier module using Urdhva Tiryakbhyam Sutra uses four 2 2 Vedic multiplier modules. Urdhva tiryakbhyam Sutra is most powerful Sutra, giving minimum delay for multiplication of all types of numbers, either small or large. Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in the real process of multiplication itself. It causes parallel generation of intermediate products,removes unwanted multiplication steps with zeros and scaled to higher bit levels. The paper s main focus is on the speed/delay of the multiplication operation on 4-bit multipliers which are modeled using VHDL, A hardware description language. The 4 4 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 9.1 software. This multiplier is implemented on Spartan 3 FPGA device XC3S50-5pq208. The performance evaluation results in terms of speed and device utilization. The multiplier with a carry-look-ahead adder has shown a less delay over the multiplier with a ripple carry adder. The multiplier with a ripple adder uses time = 17.796 ns, while the multiplier with the carry-look-ahead adder uses time = 17.560 ns. Keywords: Vedic Multiplier, Carry-Look-Ahead Adder, Ripple Carry Adder, VHDL Simulation. 1. INTRODUCTION VEDIC mathematics [1] is the ancient Indian method of mathematics which mainly deals with Vedic mathematical formula and their application to various branches of mathematics. Vedic mathematics was reconstructed from the ancient Indian scriptures (Vedas) by Sri Bharati Krsna Tirthaji (1884-1960) after his eight years of research on Vedas [1]. According to his research, Vedic mathematics is mainly based on sixteen principles which are termed as Sutras. These Sutras along with their brief meanings are enlisted below alphabetically. 1) (Anurupye) Shunyamanyat If one is in ratio, the other is zero. 2) Chalana-Kalanabyham Differences and Similarities. 3) Ekadhikina Purvena By one more than the previous one. 4) Ekanyunena Purvena By one less than the previous one. 5) Gunakasamuchyah The factors of the sum is equal to the sum of the factors. 6) Gunitasamuchyah The product of the sum is equal to the sum of product. 7) Nikhilam Navatashcaramam Dashatah All from 9 and the last from 10. 8) Paraavartya Yojayet Transpose and adjust. 9) Puranapuranabyham By the completion or Non-completion. 10) Sankalana-vyavakalanabhyam By addition and by subtraction. 11) Shesanyankena Charamena The remainders by the last digit. 12) Shunyam Saamyasamuccaye When the sum is the same that sum is zero. 13) Sopaantyadvayamantyam The ultimate and twice the penultimate. 14) Urdhva-Tiryagbyham Vertically and crosswise. 15)Vyashtisamanstih Part and Whole. 16) Yaavadunam Whatever the extent of its deficiency. This is a very interesting field and presents some effective algorithms which can be applied to various branches of engineering such as computing and digital signal processing. This paper presents a simple digital multiplier architecture [4] based on the ancient Vedic mathematics Sutra (formula) called Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra in which two different adders like ripple carry adder and carry look ahead adder are used.in this paper we conclude that vedic multiplier with carry look ahead adder is faster than the multiplier with ripple carry adder

29 2. URDHVA TIRYAKBHYAM SUTRA Urdhva Tiryakbhyam (Vertical & Crosswise) algorithm can be generalized for n x n bit number. This Multiplier has the advantage that has the number of bits increases, gate delay and area increases very slowly as compared to other multipliers. Therefore it is time, space and power efficient. It is demonstrated that this architecture is quite efficient in terms of silicon area/speed [5]. Since in this multiplier the partial products and their sums are calculated in parallel, the multiplier is independent of the clock frequency of the processor. Therefore the multiplier will require the same amount of time to calculate the product and hence is independent of the clock frequency. By adopting the Vedic multiplier, structure. Due to its regular structure, it can be easily layout in microprocessors and designers can easily circumvent this power of multiplier. It can easily be increased by increasing the input and output data bus widths since it has a quite a regular problems to avoid catastrophic device failures. The net advantage is that it reduces the need of microprocessors to operate at increasingly high clock frequencies. While at higher clock frequency generally results in increased processing power, its disadvantage is that it also increases power dissipation which results in higher device operating temperatures. Multiplication of two decimal numbers- 325*738 To illustrate this multiplication scheme, let us consider the multiplication of two decimal numbers (325 * 738). Line diagram for the multiplication is shown in Figure 2. The digits on the both sides of the line are multiplied and added with the carry from the previous step. This generates one of the bits of the result and a carry. This carry is added in the next step and hence the process goes on. If more than one line are there in one step, all the results are added to the previous carry. In each step, least significant bit acts as the result bit and all other bits act as carry for the next step. Initially the carry is taken to be zero. To make the methodology more clear, an alternate illustration is given with he help of line diagrams in Figure 3 where the dots represent bit 0 or 1. [6] Fig1:-Multiplication of two decimal numbers Fig 2:- Line diagram of two 4 bit numbers 2.1 4 4 Vedic multiplication Let s analyze 4x4 multiplications, say A3A2 A1A0 and B3B2B1B0. Following are the output line for the multiplication result, S7S6S5S4S3S2S1S0. Let s divide A and B into two parts, say A3 A2 & A1 A0 for A and B3B2 & B1B0 for B. Using the fundamental of Vedic multiplication, taking two bit at a time and using 2 bit multiplier block, we can have the following structure for multiplication. Fig 3 :- Algorithm for 4 bit Vedic (Urdhva) Multiplier

30 Each block as shown above is 2x2 multiplier. First 2x2 multiplier inputs are A1 A0 and B1B0.The last block is 2x2 multiplier with inputs A3 A2 and B3 B2. The middle one shows two, 2x2 multiplier with inputs A3A2 & B1B0 and A1A0 & B3B2. So the final result of multiplication, which is of 8 bit, S7S6S5S4S3S2S1S0, can be interpreted as given below. A3A2 A3A2 A1A0 A1 A0 B3B2 B1B0 B3B2 B1 B0 ---------- ---------- ----------- ------------ S33S32S31S30 S23S22S21S20 S13S12S11S10 S03 S02S01S00 Algorithm for 4 x 4 bit Vedic multiplier CP = Cross Product (Vertically and Crosswise) X3 X2 X1 X0 Multiplicand Y3 Y2 Y1 Y0 Multiplier -------------------------------------------------------------------- H G F E D C B A --------------------------------------------------------------------- P7 P6 P5 P4 P3 P2 P1 P0 Product --------------------------------------------------------------------- PARALLEL COMPUTATION METHODOLOGY 1. CP X0 = X0 * Y0 = A Y0 2. CP X1 X0 = X1 * Y0+X0 * Y1 = B Y1 Y0 3. CP X2 X1 X0 = X2 * Y0 +X0 * Y2 +X1 * Y1 = C Y2 Y1 Y0 4. CP X3 X2 X1 X0 = X3 * Y0 +X0 * Y3+X2 * Y1 +X1 Y3 Y2 Y1 Y0 *Y2=D 5. CP X3 X2 X1 = X3 * Y1+X1 * Y3+X2 * Y2 = E Y3 Y2 Y1 6. CP X3 X2 = X3 * Y2+X2 * Y3 = F Y3 Y2 Fig.4 :- 4 bit Ripple Carry Adder The two Boolean functions for the sum and carry are: SUM = Ai Βi Ci Cout = Ci+1 = Ai Bi + (Ai Bi) Ci 3.2 Carry Look Ahead Adder To reduce the delay caused by the effect of carry propagation through the ripple carry adder, we can attempt to evaluate quickly for each stage whether the carry-in from previous stage will have a value of 0 or 1 [7]. Given the two Boolean functions for the sum and carry as follows: SUM = Ai Βi Ci Cout = Ci+1 = Ai Bi + (Ai Bi) Ci If we let: Gi = Ai Bi -- The Generate Function Pi = (Ai Bi) -- The propagate Function Then Ci+1 = Gi + Pi Ci -- The Carry Function Thus, for 4-bit adder, we can extend the carry, as shown below: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 7 CP X3 = X3 * Y3 = G Y3 3. ADDER STRUCTURE In this paper to implement the Vedic multiplier we use two different adders i.e. Ripple Carry Adder and Carry look Ahead Adder. 3.1 Ripple Carry Adder Ripple carry adders use multiple full adders with the carry ins and carry outs chained together, where the correct value of the carry bit ripples from one bit to the next [7]. Fig 5:- 4 bit CLA Adder 4. BLOCK IMPLEMENTATION OF 4 4 VEDIC MULTIPLIER The architecture of 4x4 Vedic multiplier using Urdhva Tiryagbhyam Sutra is shown in Fig.2. The 4x4 Vedic multiplier architecture is implemented using four 2x2 Vedic multiplier modules, three 4 bit ripple carry adder

31 and CLA Adder.The first step in the design of 4 4 block will be grouping the 2 bit of each 4 bit input. These pair terms will form vertical and crosswise product terms. Each input bit-pair is handled by a separate 2 2 Vedic the schematic of a 4 4 block designed using 2 2 blocks. The partial products represent the Urdhva vertical and cross product terms. schematic of 4x4 bit Vedic multiplier is shown in Fig. 8 and Fig. 9 while the simulation results obtained are shown in Fig. 10 for verification. Fig 8:-RTL view of 4 bit Urdhva Multiplier with Ripple Carry Adder Fig 6:- Block Diagram of 4 bit Urdhva multiplier with Ripple Carry Adder Fig 9:- RTL view of 4 bit Urdhva Multiplier with CLA Adder Fig7 :- Block Diagram of 4 bit Urdhva multiplier with CLA Adder 5. IMPLEMENTATION OF 4 4 MULTIPLIER In this work, 4x4 bit Vedic multiplier is designed in VHDL (Very High Speed Integrated Circuits Hardware Description Language). Logic synthesis and simulation was done using EDA (Electronic Design Automation) tool in XilinxISE9.1i - Project Navigator and ISE simulator integrated in the Xilinx package. The performance of circuit is evaluated on the Xilinx family Spartan3,device XC3S50,package pq208 and speed grade -5. The RTL Fig 10:-Simulation Results of 4 bit multiplier 6. RESULT AND CONCLUSION Type of Multiplier(4 bit) Urdhava Multiplier with Ripple Carry Adder Urdhava Multiplier with CLA Adder Delay(ns) 17.796 17.560 TABLE 1.Comparison of multipliers in terms of delay.

32 This paper represents the comparison between 4 bit vedic multiplier with carry look ahead adder and ripple carry adder using the Urdhvatiryakbhyam sutra.the 4 4 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 9.1 software. The synthesis result shows that 4 4 Vedic Multiplier with Carry Look Ahead Adder is having less delay or we say that 4 4 Vedic Multiplier with Carry Look Ahead Adder is faster than the Vedic Multiplier with Ripple Carry Adder. REFERENCES [1] Swami Bharati Krishna Tirtha, Vedic Mathematics. Delhi: Motilal Banarsidass Publishers, 1965. [2] D. Goldberg, Computer Arithmetic, in Computer Architecture: A Quantitative Approach, J.L. Hennessy and D.A. Patterson ed., pp. A1-A66, San Mateo, CA: Morgan Kaufmann, 1990. [3] A.D. Booth, A Signed Binary Multiplication Technique, Qrt. J. Mech.App. Math.,, vol. 4, pp.236 240, 1951 [4] A.P. Nicholas, K.R Williams, J. Pickles, Application of Urdhava Sutra, Spiritual Study Group, Roorkee (India),1984. [5] Ming-Chen Wen, Sying-Jyan Wang, and Yen-Nan Lin,.Low PowerParallel Multiplier with Column Bypassing., Electronics letters, 10,12 May 2005 Volume 41, Issue Page(s): 581-583. [6]Harpreet Singh Dhillon and Abhijit Mitra, A Reduced- Bit Multiplication Algorithm for Digital Arithmetics, International Journal of Computational and Mathematical Sciences 2;2 www.waset.org Spring 2008. [7] Stephen Brown and Zvonko Vranesic, 2005. Fundamentals of Digital Logic with VHDL Design, 2nd Edition. McGraw-Hill Publishing Companies.