Analog Circuit Test Analog circuits Analog circuit test methods Specification-based testing Direct measurement DSP-based testing Fault model based testing IEEE 1149.4 analog test bus standard Summary References 1
Analog Circuits Operational amplifier (analog) Programmable gain amplifier (mixed-signal) Filters, active and passive (analog) Comparator (mixed-signal) Voltage regulator (analog or mixed-signal) Analog mixer (analog) Analog switches (analog) Analog to digital converter (mixed-signal) Digital to analog converter (mixed-signal) Phase locked loop (PLL) (mixed-signal) 2
Test Parameters DC AC Continuity Leakage current Reference voltage Impedance Gain Power supply sensitivity, common mode rejection Gain frequency and phase response Distortion harmonic, intermodulation, nonlinearity, crosstalk Noise SNR, noise figure 3
Analog Test (Traditional) ~ Filter DC RMS DC ETC. Stimulus Analog device under test (DUT) Response PEAK ETC. Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 4
DSP-Based Mixed-Signal Test Synthesizer RAM D/A Send memory Analog Digital Mixed-signal device under test (DUT) Analog Digital Digitizer A/D Receive memory RAM Synchronization Vectors Digital signal processor (DSP) Vectors M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, Los Alamitos, California: IEEE Computer Society Press, 1987, pp. 1-14. Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 5
Waveform Synthesizer 1987 IEEE Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 6
Waveform Digitizer 1987 IEEE Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 7
Example: Circuit Specification Key Performance Specifications: TLC7524C 8-bit Multiplying Digital-to-Analog Converter Resolution Linearity error Power dissipation at V DD = 5 V Settling time Propagation delay time 8 Bits ½ LSB Max 5 mw Max 1 ns Max 8 ns Max M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, New York: Oxford University Press, 21, pp. 23-44. Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 8
Voltage Mode Operation R R R V O Analog Output Voltage 2R 2R 2R 2R 2R 1 1 1 1 R V I R FB Fixed Input Voltage OUT1 OUT2 CS WR DB7 (MSB) Data Latches DB6 DB5 DB (LSB) Digital data Input GND V O = V I (D/256) VDD = 5 V OUT1 = 2.5 V OUT2 = GND Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 9
Operational/Timing Spec. Parameter Test conditions For VDD = 5 V Linearity error Gain error Settling time to ½ LSB Prop. Delay, digital input to 9% final output current CS WR DB-DB7 Measured using the internal feedback resistor. Normal full scale range (FSR) = Vref 1 LSB OUT1 load = 1 Ω, Cext = 13 pf, etc. t su (CS) 4 ns t w (WR) 4 ns t su (D) 25 ns ±.5 LSB ±2.5 LSB 1 ns 8 ns t h (CS) ns t h (D) 1 ns Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 1
Operating Range Spec. Supply voltage, V DD Digital input voltage range Reference voltage, V ref Peak digital input current -.3 V to 16.5 V -.3 V to V DD +.3 V ±25 V 1μA Operating temperature -25ºC to 85ºC Storage temperature -65ºC to 15ºC Case temperature for 1 s 26ºC Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 11
Test Plan: Hardware Setup +Full-scale code D7-D DACOUT V o 2.5 V + - V I R LOAD 1 kω VM + V out - Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 12
Test Program Pseudocode dac_full_scale_voltage() { set VI1 = 2.5 V; /* Set the DAC voltage reference to 2.5 V */ start digital pattern = dac_full_scale ; /* Set DAC output to +full scale (2.5 V) */ connect meter: DAC_OUT /* Connect voltmeter to DAC output */ fsout = read_meter(), /* Read voltage level at DAC_OUT pin */ test fsout; /* Compare the DAC full scale output to data sheet limit */ } Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 13
Analog Fault Models Op Amp Low-pass filter amplifier High-pass filter A 1 First stage gain R 2 / R 1 A 2 High-pass filter gain R 3 and C 1 f C1 High-pass filter cutoff frequency C 1 A 3 Low-pass AC voltage gain R 4, R 5 and C 2 A 4 Low-pass DC voltage gain R 4 and R 5 f C2 Low-pass filter cutoff frequency C 2 Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 14
Bipartite Graph of Circuit Minimum set of parameters to be observed Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 15
Method of ATPG Using Sensitivities Compute analog circuit sensitivities Construct analog circuit bipartite graph From graph, find which output parameters (performances) to measure to guarantee maximal coverage of parametric faults Determine which output parameters are most sensitive to faults Evaluate test quality, add test points to complete the analog fault coverage N. B. Hamida and B. Kaminska, Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling, Proc. ITC, 1993. Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 16
Sensitivity Differential (small element variation): T j x i T j ΔT j / T j S = T = j x i Δx i / x i Δ x i x i Incremental (large element variation): T j ρ = x i x i T j ΔT j Δx i T j performance parameter x i network element Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 17
Incremental Sensitivity Matrix of Circuit -.91 1.58 -.91.38 -.89 -.96 -.97.48 -.97 -.88 -.48 -.91 A 1 A 2 fc 1 A 3 A 4 fc 2 R 1 R 2 C 1 R 3 R 4 R 5 C 2 Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 18
Tolerance Box: Single- Parameter Variation A 1 A 2 A 4 ΔR 1 5% 15.98% R 1 ΔR 2 5% 14.1% R 2 ΔR 3 5% 2.27% R 3 ΔC 1 5% 11.6% C 1 ΔR 4 5% 15.% R 4 5% ΔR 5 15.% R 5 C 2 Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 19 f C1 f C2 A 3 ΔR 3 5% 14.81% R 3 ΔC 1 5% 15.2% C 1 ΔR 5 5% 14.65% R 5 ΔC 2 5% 13.96% C 2 ΔR 4 5% 15.% R 4 ΔR 5 5% 35.% R 5 ΔC 2 5% 35.%
Weighted Bipartite Graph Five tests provide most sensitive measurement of all components Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 2
IEEE 1149.4 Standard Analog Test Bus (ATB) Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 21
Test Bus Interface Circuit (TBIC) Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 22
Analog Boundary Module (ABM) Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 23
TBIC Switch Controls Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 24
Digital/Analog Interfaces At any time, only 1 analog pin can be stimulated and only 1 analog pin can be read Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 25
Summary DSP-based tester has: Waveform synthesizer Waveform digitizer High frequency clock with dividers for synchronization Analog test methods Specification-based functional testing Model-based analog testing Analog test bus allows static analog tests of mixedsignal devices Boundary scan is a prerequisite Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 26
References: Analog & RF Test A. Afshar, Principles of Semiconductor Network Testing, Boston: Butterworth- Heinemann, 1995. M. Burns and G. Roberts, Introduction to Mixed-Signal IC Test and Measurement, New York: Oxford University Press, 2. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, 2. Chapters 1, 11 and 17. D. Gizopoulos, editor, Advances in Electronic Testing Challenges and Methodologies, Springer, 26. Chapters 9 and 1. J. L. Huertas, editor, Test and Design-for-Testability in Mixed-Signal Integrated Circuits, Boston: Springer, 24. P. Kabisatpathy, A Barua, and S. Sinha, Fault Diagnosis of Analog Integrated Circuits, Springer, 25. R. W. Liu, editor, Testing and Diagnosis of Analog Circuits and Systems, New York: Van Nostrand Reinhold, 1991. M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, Los Alamitos, California: IEEE Computer Society Press, 1987. A. Osseiran, Analog and Mixed-Signal Boundary Scan, Boston: Springer, 1999. T. Ozawa, editor, Analog Methods for Computer-Aided Circuit Analysis and Diagnosis, New York: Marcel Dekker, 1988. K. B. Schaub and J. Kelly, Production Testing of RF and System-on-a-Chip Devices for Wireless Communications, Boston: Artech House, 24. B. Vinnakota, editor, Analog and Mixed-Signal Test, Upper Saddle River, New Jersey: Prentice-Hall PTR, 1998. Copyright 25, Agrawal & Bushnell VLSI Test: Lecture 16alt 27