MMD50R380P 500V 0.38Ω N-channel MOSFET

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Transcription:

MMD50R380P 500V 0.38Ω N-channel MOSFET Description MMD50R380P is power MOSFET using magnachip s advanced super junction technology that can realize very low on-resistance and gate charge. It will provide much high efficiency by using optimized charge coupling technology. These user friendly devices give an advantage of Low EMI to designers as well as low switching loss. Key Parameters Package & Internal Circuit Parameter Value Unit D V DS @ T j,max 550 V R DS(on),max 0.38 Ω V TH,typ 3 V G I D 11 A Q g,typ 21.8 nc G D S TO-252 (DPAK) S Features Low Power Loss by High Speed Switching and Low On-Resistance 100% Avalanche Tested Green Package Pb Free Plating, Halogen Free Applications PFC Power Supply Stages Switching Applications Adapter Motor Control DC DC Converters Ordering Information Order Code Marking Temp. Range Package Packing RoHS Status MMD50R380PRH 50R380-55 ~ 150 TO-252 (DPAK) Reel Halogen Free 1

Absolute Maximum Rating (T c =25 unless otherwise specified) Parameter Symbol Rating Unit Note Drain Source voltage V DSS 500 V Gate Source voltage V GSS ±30 V Continuous drain current I D 11 A T C =25 6.95 A T C =100 Pulsed drain current (1) I DM 33 A Power dissipation P D 83 W Single - pulse avalanche energy E AS 220 mj MOSFET dv/dt ruggedness dv/dt 50 V/ns Diode dv/dt ruggedness dv/dt 15 V/ns Storage temperature T stg -55 ~150 Maximum operating junction temperature 1) Pulse width t P limited by T j,max 2) I SD I D, V DS peak V (BR)DSS T j 150 Thermal Characteristics Parameter Symbol Value Unit Thermal resistance, junction-case max R thjc 1.5 /W Thermal resistance, junction-ambient max R thja 62.5 /W 2

Static Characteristics (T c =25 unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Test Condition Drain Source Breakdown voltage V (BR)DSS 500 - - V V GS = 0V, I D =0.25mA Gate Threshold Voltage V GS(th) 2.5 3.0 3.5 V V DS = V GS, I D =0.25mA Zero Gate Voltage Drain Current I DSS - - 1 μa V DS = 500V, V GS = 0V Gate Leakage Current I GSS - - 100 na V GS = ±30V, V DS =0V Drain-Source On State Resistance R DS(ON) - 0.35 0.38 Ω V GS = 10V, I D = 3.8A Dynamic Characteristics (T c =25 unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Test Condition Input Capacitance C iss - 702 - Output Capacitance C oss - 357 - Reverse Transfer Capacitance C rss - 33.7 - Effective Output Capacitance Energy Related (3) C o(er) - 27.6 - Turn On Delay Time t d(on) - 15.2 - Rise Time t r - 32 - Turn Off Delay Time t d(off) - 59.6 - Fall Time t f - 28.4 - Total Gate Charge Q g - 21.8 - Gate Source Charge Q gs - 4.8 - Gate Drain Charge Q gd - 9.7 - pf ns nc V DS = 25V, V GS = 0V, f = 1.0MHz V DS = 0V to 400V, V GS = 0V,f = 1.0MHz V GS = 10V, R G = 25Ω, V DS = 250V, I D = 11A V GS = 10V, V DS = 400V, I D = 11A Gate Resistance R G - 3.0 - Ω V GS = 0V, f = 1.0MHz 3) C o(er) is a capacitance that gives the same stored energy as C OSS while V DS is rising from 0V to 80% V (BR)DSS 3

Reverse Diode Characteristics (T c =25 unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Test Condition Continuous Diode Forward Current I SD - - 11 A Diode Forward Voltage V SD - - 1.4 V I SD = 11 A, VGS = 0 V Reverse Recovery Time t rr - 256 - ns Reverse Recovery Charge Q rr - 2.3 - μc Reverse Recovery Current I rrm - 17.6 - A I SD = 11 A di/dt = 100 A/μs V DD = 100 V 4

Characteristic Graph 5

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Test Circuit Same type as DUT 10V 100KΩ V GS 10V Q g + - V DS Q gs Q gd 1mA DUT 10V Charge Fig15-1. Gate charge measurement circuit Fig15-2. Gate charge waveform DUT I F I FM 0.5 I RM t a t rr t b I S + V - DS L d i/d t 0.75 I RM I RM 0.25 I RM R g 10KΩ Same type as DUT + - V DD V R V gs ± 15V V RM(REC) Fig16-1. Diode reverse recovery test circuit Fig16-1. Diode reverse recovery test waveform I D R g 25Ω DUT R L V DS V DS 90% V gs t p + 10% - V DD V GS T d(on) t r t on T d(off) t f t off Fig17-1. Switching time test circuit for resistive load Fig17-2. Switching time waveform I AS DUT V DS BV DSS R g t p t AV L I AS V gs t p + V DD V DS(t) - V DD Rds(on) * I AS Fig18-1. Unclamped inductive load test circuit Fig18-2. Unclamped inductive waveform 8

Physical Dimension TO-252 (D-PAK), 3L Dimensions are in millimeters, unless otherwise specified Worldwide Sales Support Locations 9

DISCLAIMER: The Products are not designed for use in hostile environments, including, without limitation, aircraft, nuclear power generation, medical appliances, and devices or systems in which malfunction of any Product can reasonably be expected to result in a personal injury. Seller s customers using or selling Seller s products for use in such applications do so at their own risk and agree to fully defend and indemnify Seller. MagnaChip reserves the right to change the specifications and circuitry without notice at any time. MagnaChip does not consider responsibility for use of any circuitry other than circuitry entirely included in a MagnaChip product. is a registered trademark of MagnaChip Semiconductor Ltd. 10